OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:44-48 [...]	Coverage (incl. loops): 2.79% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:         post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

48:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

0x42e6e0 STP	X29, X30, [SP, #848]!

0x42e6e4 ADD	X29, SP, #0

0x42e6e8 STP	X19, X20, [SP, #16]

0x42e6ec ORR	X19, XZR, X0

0x42e6f0 STP	X23, X24, [SP, #48]

0x42e6f4 LDP	W23, W1, [X0, #48]

0x42e6f8 LDR	W0, [X0, #40]

0x42e6fc LDR	W2, [X19, #44]

0x42e700 ADD	W3, W1, #4

0x42e704 SUB	W24, W23, #1

0x42e708 SUB	W4, W0, #1

0x42e70c STP	W3, W4, [SP, #136]

0x42e710 CMP	W24, W3

0x42e714 B.GE	42ead8

0x42e718 STP	X21, X22, [SP, #32]

0x42e71c ADD	W22, W2, #4

0x42e720 SUB	W21, W3, W24

0x42e724 CMP	W4, W22

0x42e728 B.GE	42eae8

0x42e72c SUB	W5, W22, W4

0x42e730 MUL	W23, W21, W5

0x42e734 STR	W5, [SP, #144]

0x42e738 BL	410210

0x42e73c ORR	W20, WZR, W0

0x42e740 BL	410240

0x42e744 UDIV	W7, W23, W20

0x42e748 ORR	W6, WZR, W0

0x42e74c MSUB	W8, W7, W20, W23

0x42e750 CMP	W0, W8

0x42e754 B.CC	42eb04

0x42e758 MADD	W23, W7, W6, W8

0x42e75c ADD	W9, W7, W23

0x42e760 STR	W9, [SP, #148]

0x42e764 CMP	W23, W9

0x42e768 B.CS	42eae8

0x42e76c LDP	W10, W11, [SP, #140]

0x42e770 STP	X27, X28, [SP, #80]

0x42e774 STP	X25, X26, [SP, #64]

0x42e778 UDIV	W12, W23, W11

0x42e77c LDR	X27, [X19, #32]

0x42e780 LDP	X20, X25, [X19]

0x42e784 MSUB	W13, W12, W11, W23

0x42e788 ADD	W14, W12, W24

0x42e78c LDP	X24, X26, [X19, #16]

0x42e790 SBFM	X0, X14, #0, #31

0x42e794 ADD	W28, W13, W10

0x42e798 SUB	W22, W22, W28

0x42e79c CMP	W7, W22

0x42e7a0 CSEL	W3, W7, W22, #9

0x42e7a4 ADD	W19, W23, W3

0x42e7a8 CMP	W23, W19

0x42e7ac B.CS	42eab4

  (178) 0x42e7b0 LDR	X30, [X27]

  (178) 0x42e7b4 ADD	X16, X0, #1

  (178) 0x42e7b8 LDR	X18, [X25]

  (178) 0x42e7bc LDR	X17, [X20]

  (178) 0x42e7c0 MUL	X4, X0, X30

  (178) 0x42e7c4 LDR	X13, [X20, #16]

  (178) 0x42e7c8 MADD	X12, X0, X18, X18

  (178) 0x42e7cc LDR	X21, [X24, #16]

  (178) 0x42e7d0 MUL	X11, X0, X17

  (178) 0x42e7d4 LDR	X14, [X25, #16]

  (178) 0x42e7d8 SUB	X6, X12, X18

  (178) 0x42e7dc LDR	X22, [X26, #16]

  (178) 0x42e7e0 STR	X6, [SP, #120]

  (178) 0x42e7e4 LDR	X23, [X27, #16]

  (178) 0x42e7e8 STP	X16, X4, [SP, #104]

  (178) 0x42e7ec LDR	X1, [X24]

  (178) 0x42e7f0 LDR	X2, [X26]

  (178) 0x42e7f4 MUL	X5, X0, X1

  (178) 0x42e7f8 MUL	X30, X0, X2

  (178) 0x42e7fc STR	X5, [SP, #128]

  (178) 0x42e800 CMP	W3, #1

  (178) 0x42e804 B.EQ	42ea20

  (178) 0x42e808 SBFM	X8, X28, #0, #31

  (178) 0x42e80c UBFM	W7, W3, #1, #31

  (178) 0x42e810 ADD	X15, X11, X8

  (178) 0x42e814 UBFM	X10, X7, #60, #59

  (178) 0x42e818 ADD	X16, X15, #1

  (178) 0x42e81c SUB	X9, X10, #16

  (178) 0x42e820 UBFM	X7, X16, #61, #60

  (178) 0x42e824 UBFM	X17, X9, #4, #63

  (178) 0x42e828 ADD	X2, X13, X16,LSL #3

  (178) 0x42e82c ADD	X18, X17, #1

  (178) 0x42e830 ADD	X17, X5, X8

  (178) 0x42e834 STR	X7, [SP, #152]

  (178) 0x42e838 SUB	X7, X7, #8

  (178) 0x42e83c ADD	X5, X21, X17,LSL #3

  (178) 0x42e840 ADD	X1, X30, X8

  (178) 0x42e844 ADD	X15, X4, X8

  (178) 0x42e848 ADD	X4, X13, X7

  (178) 0x42e84c STR	X7, [SP, #160]

  (178) 0x42e850 UBFM	X7, X1, #61, #60

  (178) 0x42e854 ADD	X16, X6, X8

  (178) 0x42e858 ANDS	X9, X18, #0x3

  (178) 0x42e85c STR	X5, [SP, #96]

  (178) 0x42e860 ADD	X18, X12, X8

  (178) 0x42e864 STR	X7, [SP, #168]

  (178) 0x42e868 ADD	X6, X14, X16,LSL #3

  (178) 0x42e86c ADD	X8, X14, X18,LSL #3

  (178) 0x42e870 MOVZ	X0, #0

  (178) 0x42e874 UBFM	X17, X17, #61, #60

  (178) 0x42e878 ADD	X5, X23, X15,LSL #3

  (178) 0x42e87c UBFM	X18, X18, #61, #60

  (178) 0x42e880 UBFM	X16, X16, #61, #60

  (178) 0x42e884 ADD	X1, X22, X1,LSL #3

  (178) 0x42e888 UBFM	X15, X15, #61, #60

  (178) 0x42e88c B.EQ	42eafc

  (178) 0x42e890 CMP	X9, #1

  (178) 0x42e894 B.EQ	42e910

  (178) 0x42e898 CMP	X9, #2

  (178) 0x42e89c B.EQ	42e8dc

  (178) 0x42e8a0 LDR	Q1, [X14, X18]

  (178) 0x42e8a4 MOVZ	X0, #16

  (178) 0x42e8a8 LDR	Q0, [X21, X17]

  (178) 0x42e8ac LDR	Q29, [X14, X16]

  (178) 0x42e8b0 LDR	X9, [SP, #152]

  (178) 0x42e8b4 FADD	V2.2D, V1.2D, V0.2D

  (178) 0x42e8b8 LDR	X17, [SP, #160]

  (178) 0x42e8bc LDR	X18, [SP, #168]

  (178) 0x42e8c0 FSUB	V3.2D, V2.2D, V29.2D

  (178) 0x42e8c4 STR	Q3, [X23, X15]

  (178) 0x42e8c8 LDR	Q31, [X13, X9]

  (178) 0x42e8cc LDR	Q30, [X13, X17]

  (178) 0x42e8d0 FSUB	V4.2D, V31.2D, V30.2D

  (178) 0x42e8d4 FADD	V5.2D, V4.2D, V3.2D

  (178) 0x42e8d8 STR	Q5, [X22, X18]

  (178) 0x42e8dc LDR	X16, [SP, #96]

  (178) 0x42e8e0 LDR	Q6, [X8, X0]

  (178) 0x42e8e4 LDR	Q26, [X6, X0]

  (178) 0x42e8e8 LDR	Q7, [X16, X0]

  (178) 0x42e8ec FADD	V16.2D, V6.2D, V7.2D

  (178) 0x42e8f0 FSUB	V17.2D, V16.2D, V26.2D

  (178) 0x42e8f4 STR	Q17, [X5, X0]

  (178) 0x42e8f8 LDR	Q28, [X2, X0]

  (178) 0x42e8fc LDR	Q27, [X4, X0]

  (178) 0x42e900 FSUB	V18.2D, V28.2D, V27.2D

  (178) 0x42e904 FADD	V19.2D, V18.2D, V17.2D

  (178) 0x42e908 STR	Q19, [X1, X0]

  (178) 0x42e90c ADD	X0, X0, #16

  (178) 0x42e910 LDR	X7, [SP, #96]

  (178) 0x42e914 LDR	Q20, [X8, X0]

  (178) 0x42e918 LDR	Q23, [X6, X0]

  (178) 0x42e91c LDR	Q21, [X7, X0]

  (178) 0x42e920 FADD	V22.2D, V20.2D, V21.2D

  (178) 0x42e924 FSUB	V1.2D, V22.2D, V23.2D

  (178) 0x42e928 STR	Q1, [X5, X0]

  (178) 0x42e92c LDR	Q25, [X2, X0]

  (178) 0x42e930 LDR	Q24, [X4, X0]

  (178) 0x42e934 FSUB	V0.2D, V25.2D, V24.2D

  (178) 0x42e938 FADD	V29.2D, V0.2D, V1.2D

  (178) 0x42e93c STR	Q29, [X1, X0]

  (178) 0x42e940 ADD	X0, X0, #16

  (178) 0x42e944 CMP	X0, X10

  (178) 0x42e948 B.EQ	42ea14

    (179) 0x42e94c LDR	Q2, [X8, X0]

    (179) 0x42e950 ADD	X9, X0, #16

    (179) 0x42e954 ADD	X17, X0, #32

    (179) 0x42e958 ADD	X15, X0, #48

    (179) 0x42e95c LDR	Q3, [X7, X0]

    (179) 0x42e960 LDR	Q31, [X6, X0]

    (179) 0x42e964 FADD	V30.2D, V2.2D, V3.2D

    (179) 0x42e968 FSUB	V4.2D, V30.2D, V31.2D

    (179) 0x42e96c STR	Q4, [X5, X0]

    (179) 0x42e970 LDR	Q5, [X2, X0]

    (179) 0x42e974 LDR	Q6, [X4, X0]

    (179) 0x42e978 FSUB	V26.2D, V5.2D, V6.2D

    (179) 0x42e97c FADD	V7.2D, V26.2D, V4.2D

    (179) 0x42e980 STR	Q7, [X1, X0]

    (179) 0x42e984 ADD	X0, X0, #64

    (179) 0x42e988 LDR	Q16, [X8, X9]

    (179) 0x42e98c LDR	Q17, [X7, X9]

    (179) 0x42e990 LDR	Q28, [X6, X9]

    (179) 0x42e994 FADD	V27.2D, V16.2D, V17.2D

    (179) 0x42e998 FSUB	V18.2D, V27.2D, V28.2D

    (179) 0x42e99c STR	Q18, [X5, X9]

    (179) 0x42e9a0 LDR	Q19, [X2, X9]

    (179) 0x42e9a4 LDR	Q20, [X4, X9]

    (179) 0x42e9a8 FSUB	V23.2D, V19.2D, V20.2D

    (179) 0x42e9ac FADD	V21.2D, V23.2D, V18.2D

    (179) 0x42e9b0 STR	Q21, [X1, X9]

    (179) 0x42e9b4 LDR	Q22, [X8, X17]

    (179) 0x42e9b8 LDR	Q1, [X7, X17]

    (179) 0x42e9bc LDR	Q25, [X6, X17]

    (179) 0x42e9c0 FADD	V24.2D, V22.2D, V1.2D

    (179) 0x42e9c4 FSUB	V0.2D, V24.2D, V25.2D

    (179) 0x42e9c8 STR	Q0, [X5, X17]

    (179) 0x42e9cc LDR	Q29, [X2, X17]

    (179) 0x42e9d0 LDR	Q2, [X4, X17]

    (179) 0x42e9d4 FSUB	V3.2D, V29.2D, V2.2D

    (179) 0x42e9d8 FADD	V31.2D, V3.2D, V0.2D

    (179) 0x42e9dc STR	Q31, [X1, X17]

    (179) 0x42e9e0 LDR	Q30, [X8, X15]

    (179) 0x42e9e4 LDR	Q4, [X7, X15]

    (179) 0x42e9e8 LDR	Q5, [X6, X15]

    (179) 0x42e9ec FADD	V6.2D, V30.2D, V4.2D

    (179) 0x42e9f0 FSUB	V26.2D, V6.2D, V5.2D

    (179) 0x42e9f4 STR	Q26, [X5, X15]

    (179) 0x42e9f8 LDR	Q7, [X2, X15]

    (179) 0x42e9fc LDR	Q16, [X4, X15]

    (179) 0x42ea00 FSUB	V17.2D, V7.2D, V16.2D

    (179) 0x42ea04 FADD	V28.2D, V17.2D, V26.2D

    (179) 0x42ea08 STR	Q28, [X1, X15]

    (179) 0x42ea0c CMP	X0, X10

    (179) 0x42ea10 B.NE	42e94c

  (178) 0x42ea14 TBZ	W3, #0, 42ea7c

  (178) 0x42ea18 AND	W3, W3, #0xfffffffe

  (178) 0x42ea1c ADD	W28, W28, W3

  (178) 0x42ea20 LDR	X6, [SP, #128]

  (178) 0x42ea24 SBFM	X10, X28, #0, #31

  (178) 0x42ea28 ADD	W2, W28, #1

  (178) 0x42ea2c ADD	X12, X12, X10

  (178) 0x42ea30 ADD	X8, X11, W2,SXTW

  (178) 0x42ea34 ADD	X11, X11, X10

  (178) 0x42ea38 ADD	X30, X30, X10

  (178) 0x42ea3c LDR	D27, [X14, X12,LSL #3]

  (178) 0x42ea40 ADD	X4, X6, X10

  (178) 0x42ea44 LDR	D18, [X21, X4,LSL #3]

  (178) 0x42ea48 LDR	X21, [SP, #120]

  (178) 0x42ea4c FADD	D19, D27, D18

  (178) 0x42ea50 ADD	X5, X21, X10

  (178) 0x42ea54 LDR	D20, [X14, X5,LSL #3]

  (178) 0x42ea58 LDR	X14, [SP, #112]

  (178) 0x42ea5c FSUB	D23, D19, S20

  (178) 0x42ea60 ADD	X1, X14, X10

  (178) 0x42ea64 STR	D23, [X23, X1,LSL #3]

  (178) 0x42ea68 LDR	D21, [X13, X8,LSL #3]

  (178) 0x42ea6c LDR	D22, [X13, X11,LSL #3]

  (178) 0x42ea70 FSUB	D1, D21, S22

  (178) 0x42ea74 FADD	D25, D1, D23

  (178) 0x42ea78 STR	D25, [X22, X30,LSL #3]

  (178) 0x42ea7c LDR	X0, [SP, #104]

  (178) 0x42ea80 ORR	W23, WZR, W19

  (178) 0x42ea84 LDR	W19, [SP, #136]

  (178) 0x42ea88 CMP	W19, W0

  (178) 0x42ea8c B.LE	42eacc

  (178) 0x42ea90 LDR	W13, [SP, #148]

  (178) 0x42ea94 LDR	W22, [SP, #144]

  (178) 0x42ea98 LDR	W28, [SP, #140]

  (178) 0x42ea9c SUB	W7, W13, W23

  (178) 0x42eaa0 CMP	W7, W22

  (178) 0x42eaa4 CSEL	W3, W7, W22, #9

  (178) 0x42eaa8 ADD	W19, W23, W3

  (178) 0x42eaac CMP	W23, W19

  (178) 0x42eab0 B.CC	42e7b0

(180) 0x42eab4 ADD	X15, X0, #1

(180) 0x42eab8 LDR	W19, [SP, #136]

(180) 0x42eabc STR	X15, [SP, #104]

(180) 0x42eac0 LDR	X0, [SP, #104]

(180) 0x42eac4 CMP	W19, W0

(180) 0x42eac8 B.GT	42ea90

0x42eacc LDP	X21, X22, [SP, #32]

0x42ead0 LDP	X25, X26, [SP, #64]

0x42ead4 LDP	X27, X28, [SP, #80]

0x42ead8 LDP	X19, X20, [SP, #16]

0x42eadc LDP	X23, X24, [SP, #48]

0x42eae0 LDP	X29, X30, [SP], #176

0x42eae4 RET

0x42eae8 LDP	X21, X22, [SP, #32]

0x42eaec LDP	X19, X20, [SP, #16]

0x42eaf0 LDP	X23, X24, [SP, #48]

0x42eaf4 LDP	X29, X30, [SP], #176

0x42eaf8 RET

  (178) 0x42eafc LDR	X7, [SP, #96]

  (178) 0x42eb00 B	42e94c

0x42eb04 ADD	W7, W7, #1

0x42eb08 MOVZ	W8, #0

0x42eb0c B	42e758

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 25.00 to 6.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.83 cycles (2.83x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	67
nb uops	67
loop length	268
used w registers	23
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50
cycles	5.00	5.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	8.38
Dispatch	8.83
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	26%
load	41%
store	38%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42e6e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X19, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W24, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42ead8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W3, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42eae8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W23, W21, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W23, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W8, W7, W20, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42eb04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W23, W7, W6, W8	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [SP, #148]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W23, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42eae8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W10, W11, [SP, #140]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UDIV W12, W23, W11	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
LDR X27, [X19, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X20, X25, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W13, W12, W11, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W14, W12, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X24, X26, [X19, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X0, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W28, W13, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W22, W22, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W3, W7, W22, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W23, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W23, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42eab4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
B 42e758 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.83 cycles (2.83x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	67
nb uops	67
loop length	268
used w registers	23
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50
cycles	5.00	5.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	8.38
Dispatch	8.83
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	26%
load	41%
store	38%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42e6e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X19, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W24, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42ead8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W3, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42eae8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W23, W21, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W23, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W8, W7, W20, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42eb04 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W23, W7, W6, W8	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [SP, #148]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W23, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42eae8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W10, W11, [SP, #140]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UDIV W12, W23, W11	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
LDR X27, [X19, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X20, X25, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W13, W12, W11, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W14, W12, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X24, X26, [X19, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X0, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W28, W13, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W22, W22, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W3, W7, W22, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W23, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W23, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42eab4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
B 42e758 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.79	3.75
▼Loop 180 - advec_mom.cpp:44-48 - exec–	0.00	0.00
▼Loop 178 - advec_mom.cpp:44-48 - exec–	0.01	0.02
○Loop 179 - advec_mom.cpp:47-48 - exec	2.78	3.63

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Vectorization

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Expensive FP math instructions/calls

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Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code