OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:71-75 [...]	Coverage (incl. loops): 2.10% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 71 - 75

--------------------------------------------------------------------------------

71: #pragma omp parallel for simd collapse(2)

72:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

73:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

74:         post_vol(i, j) = volume(i, j);

75:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

0x42f38c STP	X29, X30, [SP, #896]!

0x42f390 ADD	X29, SP, #0

0x42f394 STP	X19, X20, [SP, #16]

0x42f398 ORR	X19, XZR, X0

0x42f39c STP	X23, X24, [SP, #48]

0x42f3a0 STP	X25, X26, [SP, #64]

0x42f3a4 LDP	W25, W1, [X0, #40]

0x42f3a8 LDR	W24, [X19, #36]

0x42f3ac LDR	W0, [X0, #32]

0x42f3b0 SUB	W26, W25, #1

0x42f3b4 ADD	W23, W1, #4

0x42f3b8 CMP	W26, W23

0x42f3bc B.GE	42f79c

0x42f3c0 STP	X21, X22, [SP, #32]

0x42f3c4 ADD	W22, W24, #4

0x42f3c8 SUB	W21, W23, W26

0x42f3cc STP	X27, X28, [SP, #80]

0x42f3d0 SUB	W28, W0, #1

0x42f3d4 CMP	W28, W22

0x42f3d8 B.GE	42f794

0x42f3dc SUB	W2, W22, W28

0x42f3e0 MUL	W27, W21, W2

0x42f3e4 STR	W2, [SP, #108]

0x42f3e8 BL	410210

0x42f3ec ORR	W20, WZR, W0

0x42f3f0 BL	410240

0x42f3f4 UDIV	W3, W27, W20

0x42f3f8 ORR	W4, WZR, W0

0x42f3fc MSUB	W5, W3, W20, W27

0x42f400 CMP	W0, W5

0x42f404 B.CC	42f7b0

0x42f408 MADD	W18, W3, W4, W5

0x42f40c ADD	W6, W3, W18

0x42f410 STR	W6, [SP, #120]

0x42f414 CMP	W18, W6

0x42f418 B.CS	42f794

0x42f41c LDR	W7, [SP, #108]

0x42f420 ORR	W30, WZR, W28

0x42f424 ORR	W24, WZR, W23

0x42f428 UDIV	W9, W18, W7

0x42f42c MSUB	W8, W9, W7, W18

0x42f430 ADD	W10, W9, W26

0x42f434 SBFM	X7, X10, #0, #31

0x42f438 ADD	W8, W8, W28

0x42f43c SUB	W17, W22, W8

0x42f440 LDP	X22, X21, [X19]

0x42f444 LDP	X20, X19, [X19, #16]

(187) 0x42f448 CMP	W3, W17

(187) 0x42f44c CSEL	W6, W3, W17, #9

(187) 0x42f450 ADD	W16, W18, W6

(187) 0x42f454 CMP	W18, W16

(187) 0x42f458 B.CS	42f774

(187) 0x42f45c LDR	X11, [X19]

(187) 0x42f460 LDR	X13, [X20]

(187) 0x42f464 LDR	X12, [X21]

(187) 0x42f468 MUL	X11, X7, X11

(187) 0x42f46c LDR	X14, [X22]

(187) 0x42f470 MUL	X13, X7, X13

(187) 0x42f474 LDR	X18, [X19, #16]

(187) 0x42f478 MUL	X12, X7, X12

(187) 0x42f47c LDR	X17, [X20, #16]

(187) 0x42f480 MUL	X10, X7, X14

(187) 0x42f484 LDR	X23, [X21, #16]

(187) 0x42f488 LDR	X15, [X22, #16]

(187) 0x42f48c CMP	W6, #1

(187) 0x42f490 B.EQ	42f738

(187) 0x42f494 UBFM	W25, W6, #1, #31

(187) 0x42f498 SBFM	X1, X8, #0, #31

(187) 0x42f49c UBFM	X9, X25, #60, #59

(187) 0x42f4a0 ADD	X26, X10, X1

(187) 0x42f4a4 SUB	X28, X9, #16

(187) 0x42f4a8 ADD	X25, X11, X1

(187) 0x42f4ac UBFM	X27, X28, #4, #63

(187) 0x42f4b0 ADD	X2, X26, #1

(187) 0x42f4b4 ADD	X4, X27, #1

(187) 0x42f4b8 UBFM	X28, X2, #61, #60

(187) 0x42f4bc ADD	X2, X15, X2,LSL #3

(187) 0x42f4c0 ANDS	X14, X4, #0x7

(187) 0x42f4c4 ADD	X4, X18, X25,LSL #3

(187) 0x42f4c8 UBFM	X25, X25, #61, #60

(187) 0x42f4cc ADD	X26, X12, X1

(187) 0x42f4d0 SUB	X27, X28, #8

(187) 0x42f4d4 ADD	X1, X13, X1

(187) 0x42f4d8 STR	X25, [SP, #112]

(187) 0x42f4dc ADD	X5, X23, X26,LSL #3

(187) 0x42f4e0 UBFM	X25, X1, #61, #60

(187) 0x42f4e4 MOVZ	X0, #0

(187) 0x42f4e8 ADD	X1, X17, X1,LSL #3

(187) 0x42f4ec ADD	X3, X15, X27

(187) 0x42f4f0 UBFM	X26, X26, #61, #60

(187) 0x42f4f4 B.EQ	42f614

(187) 0x42f4f8 CMP	X14, #1

(187) 0x42f4fc B.EQ	42f5ec

(187) 0x42f500 CMP	X14, #2

(187) 0x42f504 B.EQ	42f5cc

(187) 0x42f508 CMP	X14, #3

(187) 0x42f50c B.EQ	42f5ac

(187) 0x42f510 CMP	X14, #4

(187) 0x42f514 B.EQ	42f58c

(187) 0x42f518 CMP	X14, #5

(187) 0x42f51c B.EQ	42f56c

(187) 0x42f520 CMP	X14, #6

(187) 0x42f524 B.EQ	42f54c

(187) 0x42f528 LDR	Q0, [X23, X26]

(187) 0x42f52c MOVZ	X0, #16

(187) 0x42f530 LDR	X14, [SP, #112]

(187) 0x42f534 STR	Q0, [X18, X14]

(187) 0x42f538 LDR	Q30, [X15, X28]

(187) 0x42f53c LDR	Q31, [X15, X27]

(187) 0x42f540 FADD	V1.2D, V30.2D, V0.2D

(187) 0x42f544 FSUB	V2.2D, V1.2D, V31.2D

(187) 0x42f548 STR	Q2, [X17, X25]

(187) 0x42f54c LDR	Q3, [X5, X0]

(187) 0x42f550 STR	Q3, [X4, X0]

(187) 0x42f554 LDR	Q28, [X2, X0]

(187) 0x42f558 LDR	Q29, [X3, X0]

(187) 0x42f55c FADD	V4.2D, V28.2D, V3.2D

(187) 0x42f560 FSUB	V5.2D, V4.2D, V29.2D

(187) 0x42f564 STR	Q5, [X1, X0]

(187) 0x42f568 ADD	X0, X0, #16

(187) 0x42f56c LDR	Q6, [X5, X0]

(187) 0x42f570 STR	Q6, [X4, X0]

(187) 0x42f574 LDR	Q26, [X2, X0]

(187) 0x42f578 LDR	Q27, [X3, X0]

(187) 0x42f57c FADD	V7.2D, V26.2D, V6.2D

(187) 0x42f580 FSUB	V16.2D, V7.2D, V27.2D

(187) 0x42f584 STR	Q16, [X1, X0]

(187) 0x42f588 ADD	X0, X0, #16

(187) 0x42f58c LDR	Q17, [X5, X0]

(187) 0x42f590 STR	Q17, [X4, X0]

(187) 0x42f594 LDR	Q24, [X2, X0]

(187) 0x42f598 LDR	Q25, [X3, X0]

(187) 0x42f59c FADD	V18.2D, V24.2D, V17.2D

(187) 0x42f5a0 FSUB	V19.2D, V18.2D, V25.2D

(187) 0x42f5a4 STR	Q19, [X1, X0]

(187) 0x42f5a8 ADD	X0, X0, #16

(187) 0x42f5ac LDR	Q20, [X5, X0]

(187) 0x42f5b0 STR	Q20, [X4, X0]

(187) 0x42f5b4 LDR	Q22, [X2, X0]

(187) 0x42f5b8 LDR	Q23, [X3, X0]

(187) 0x42f5bc FADD	V21.2D, V22.2D, V20.2D

(187) 0x42f5c0 FSUB	V0.2D, V21.2D, V23.2D

(187) 0x42f5c4 STR	Q0, [X1, X0]

(187) 0x42f5c8 ADD	X0, X0, #16

(187) 0x42f5cc LDR	Q30, [X5, X0]

(187) 0x42f5d0 STR	Q30, [X4, X0]

(187) 0x42f5d4 LDR	Q31, [X2, X0]

(187) 0x42f5d8 LDR	Q1, [X3, X0]

(187) 0x42f5dc FADD	V2.2D, V31.2D, V30.2D

(187) 0x42f5e0 FSUB	V3.2D, V2.2D, V1.2D

(187) 0x42f5e4 STR	Q3, [X1, X0]

(187) 0x42f5e8 ADD	X0, X0, #16

(187) 0x42f5ec LDR	Q28, [X5, X0]

(187) 0x42f5f0 STR	Q28, [X4, X0]

(187) 0x42f5f4 LDR	Q29, [X2, X0]

(187) 0x42f5f8 LDR	Q4, [X3, X0]

(187) 0x42f5fc FADD	V5.2D, V29.2D, V28.2D

(187) 0x42f600 FSUB	V6.2D, V5.2D, V4.2D

(187) 0x42f604 STR	Q6, [X1, X0]

(187) 0x42f608 ADD	X0, X0, #16

(187) 0x42f60c CMP	X0, X9

(187) 0x42f610 B.EQ	42f72c

(187) 0x42f614 STR	W24, [SP, #112]

(187) 0x42f618 STR	W30, [SP, #124]

  (188) 0x42f61c LDR	Q26, [X5, X0]

  (188) 0x42f620 ADD	X14, X0, #16

  (188) 0x42f624 ADD	X30, X0, #32

  (188) 0x42f628 ADD	X28, X0, #48

  (188) 0x42f62c ADD	X27, X0, #64

  (188) 0x42f630 ADD	X26, X0, #80

  (188) 0x42f634 ADD	X25, X0, #96

  (188) 0x42f638 ADD	X24, X0, #112

  (188) 0x42f63c STR	Q26, [X4, X0]

  (188) 0x42f640 LDR	Q27, [X2, X0]

  (188) 0x42f644 LDR	Q7, [X3, X0]

  (188) 0x42f648 FADD	V16.2D, V27.2D, V26.2D

  (188) 0x42f64c FSUB	V17.2D, V16.2D, V7.2D

  (188) 0x42f650 STR	Q17, [X1, X0]

  (188) 0x42f654 ADD	X0, X0, #128

  (188) 0x42f658 LDR	Q24, [X5, X14]

  (188) 0x42f65c STR	Q24, [X4, X14]

  (188) 0x42f660 LDR	Q25, [X2, X14]

  (188) 0x42f664 LDR	Q18, [X3, X14]

  (188) 0x42f668 FADD	V19.2D, V25.2D, V24.2D

  (188) 0x42f66c FSUB	V20.2D, V19.2D, V18.2D

  (188) 0x42f670 STR	Q20, [X1, X14]

  (188) 0x42f674 LDR	Q21, [X5, X30]

  (188) 0x42f678 STR	Q21, [X4, X30]

  (188) 0x42f67c LDR	Q22, [X2, X30]

  (188) 0x42f680 LDR	Q23, [X3, X30]

  (188) 0x42f684 FADD	V0.2D, V22.2D, V21.2D

  (188) 0x42f688 FSUB	V30.2D, V0.2D, V23.2D

  (188) 0x42f68c STR	Q30, [X1, X30]

  (188) 0x42f690 LDR	Q31, [X5, X28]

  (188) 0x42f694 STR	Q31, [X4, X28]

  (188) 0x42f698 LDR	Q1, [X2, X28]

  (188) 0x42f69c LDR	Q2, [X3, X28]

  (188) 0x42f6a0 FADD	V3.2D, V1.2D, V31.2D

  (188) 0x42f6a4 FSUB	V28.2D, V3.2D, V2.2D

  (188) 0x42f6a8 STR	Q28, [X1, X28]

  (188) 0x42f6ac LDR	Q29, [X5, X27]

  (188) 0x42f6b0 STR	Q29, [X4, X27]

  (188) 0x42f6b4 LDR	Q4, [X2, X27]

  (188) 0x42f6b8 LDR	Q5, [X3, X27]

  (188) 0x42f6bc FADD	V6.2D, V4.2D, V29.2D

  (188) 0x42f6c0 FSUB	V26.2D, V6.2D, V5.2D

  (188) 0x42f6c4 STR	Q26, [X1, X27]

  (188) 0x42f6c8 LDR	Q27, [X5, X26]

  (188) 0x42f6cc STR	Q27, [X4, X26]

  (188) 0x42f6d0 LDR	Q7, [X2, X26]

  (188) 0x42f6d4 LDR	Q16, [X3, X26]

  (188) 0x42f6d8 FADD	V17.2D, V7.2D, V27.2D

  (188) 0x42f6dc FSUB	V24.2D, V17.2D, V16.2D

  (188) 0x42f6e0 STR	Q24, [X1, X26]

  (188) 0x42f6e4 LDR	Q25, [X5, X25]

  (188) 0x42f6e8 STR	Q25, [X4, X25]

  (188) 0x42f6ec LDR	Q18, [X2, X25]

  (188) 0x42f6f0 LDR	Q19, [X3, X25]

  (188) 0x42f6f4 FADD	V20.2D, V18.2D, V25.2D

  (188) 0x42f6f8 FSUB	V21.2D, V20.2D, V19.2D

  (188) 0x42f6fc STR	Q21, [X1, X25]

  (188) 0x42f700 LDR	Q22, [X5, X24]

  (188) 0x42f704 STR	Q22, [X4, X24]

  (188) 0x42f708 LDR	Q23, [X2, X24]

  (188) 0x42f70c LDR	Q0, [X3, X24]

  (188) 0x42f710 FADD	V30.2D, V23.2D, V22.2D

  (188) 0x42f714 FSUB	V31.2D, V30.2D, V0.2D

  (188) 0x42f718 STR	Q31, [X1, X24]

  (188) 0x42f71c CMP	X0, X9

  (188) 0x42f720 B.NE	42f61c

(187) 0x42f724 LDR	W24, [SP, #112]

(187) 0x42f728 LDR	W30, [SP, #124]

(187) 0x42f72c TBZ	W6, #0, 42f770

(187) 0x42f730 AND	W6, W6, #0xfffffffe

(187) 0x42f734 ADD	W8, W8, W6

(187) 0x42f738 SBFM	X9, X8, #0, #31

(187) 0x42f73c ADD	W2, W8, #1

(187) 0x42f740 ADD	X5, X10, W2,SXTW

(187) 0x42f744 ADD	X12, X12, X9

(187) 0x42f748 ADD	X11, X11, X9

(187) 0x42f74c ADD	X10, X10, X9

(187) 0x42f750 ADD	X13, X13, X9

(187) 0x42f754 LDR	D1, [X23, X12,LSL #3]

(187) 0x42f758 STR	D1, [X18, X11,LSL #3]

(187) 0x42f75c LDR	D2, [X15, X5,LSL #3]

(187) 0x42f760 LDR	D3, [X15, X10,LSL #3]

(187) 0x42f764 FSUB	D28, D2, S3

(187) 0x42f768 FADD	D29, D28, D1

(187) 0x42f76c STR	D29, [X17, X13,LSL #3]

(187) 0x42f770 ORR	W18, WZR, W16

(187) 0x42f774 ADD	X7, X7, #1

(187) 0x42f778 CMP	W24, W7

(187) 0x42f77c B.LE	42f794

(187) 0x42f780 LDR	W16, [SP, #120]

(187) 0x42f784 ORR	W8, WZR, W30

(187) 0x42f788 LDR	W17, [SP, #108]

(187) 0x42f78c SUB	W3, W16, W18

(187) 0x42f790 B	42f448

0x42f794 LDP	X21, X22, [SP, #32]

0x42f798 LDP	X27, X28, [SP, #80]

0x42f79c LDP	X19, X20, [SP, #16]

0x42f7a0 LDP	X23, X24, [SP, #48]

0x42f7a4 LDP	X25, X26, [SP, #64]

0x42f7a8 LDP	X29, X30, [SP], #128

0x42f7ac RET

0x42f7b0 ADD	W3, W3, #1

0x42f7b4 MOVZ	W5, #0

0x42f7b8 B	42f408

0x42f7bc HINT	#0

Coverage (%)	Name	Module
►98.42+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 7.50 cycles (3.33x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	58
nb uops	57
loop length	232
used w registers	24
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	6.67	6.67	6.67	4.00	4.00
cycles	4.00	4.00	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	6.67	6.67	6.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Dispatch	8.00
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	25%
load	38%
store	40%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42f38c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W25, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X19, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W26, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W23, W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W26, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42f79c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W24, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W23, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W28, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W28, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42f794 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W2, W22, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W27, W21, W2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W2, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W3, W27, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W4, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W5, W3, W20, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42f7b0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W18, W3, W4, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W6, W3, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W18, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42f794 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W7, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W30, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR W24, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UDIV W9, W18, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W8, W9, W7, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W10, W9, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X7, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W8, W8, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, W22, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X22, X21, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X20, X19, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42f408 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 7.50 cycles (3.33x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	58
nb uops	57
loop length	232
used w registers	24
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	6.67	6.67	6.67	4.00	4.00
cycles	4.00	4.00	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	6.67	6.67	6.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Dispatch	8.00
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	25%
load	38%
store	40%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42f38c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W25, W1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X19, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W26, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W23, W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W26, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42f79c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W24, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W23, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W28, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W28, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42f794 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W2, W22, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W27, W21, W2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W2, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W3, W27, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W4, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W5, W3, W20, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42f7b0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W18, W3, W4, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W6, W3, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W18, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42f794 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W7, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W30, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR W24, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UDIV W9, W18, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W8, W9, W7, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W10, W9, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X7, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W8, W8, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, W22, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X22, X21, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X20, X19, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42f408 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.10	2.82
▼Loop 187 - advec_mom.cpp:73-75 - exec–	0.00	0.02
○Loop 188 - advec_mom.cpp:74-75 - exec	2.09	2.73

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code