OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:146-149 [...]	Coverage (incl. loops): 4.60% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 146 - 149

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

148:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

149:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j);

0x42ff20 STP	X29, X30, [SP, #912]!

0x42ff24 ADD	X29, SP, #0

0x42ff28 STP	X19, X20, [SP, #16]

0x42ff2c ORR	X20, XZR, X0

0x42ff30 STP	X21, X22, [SP, #32]

0x42ff34 STP	X23, X24, [SP, #48]

0x42ff38 LDP	W22, W23, [X0, #40]

0x42ff3c LDR	W19, [X20, #36]

0x42ff40 LDR	W0, [X0, #32]

0x42ff44 ADD	W22, W22, #1

0x42ff48 ADD	W23, W23, #3

0x42ff4c CMP	W22, W23

0x42ff50 B.GE	430254

0x42ff54 STP	X27, X28, [SP, #80]

0x42ff58 ADD	W28, W0, #1

0x42ff5c ADD	W27, W19, #3

0x42ff60 SUB	W24, W23, W22

0x42ff64 CMP	W28, W27

0x42ff68 B.GE	430250

0x42ff6c SUB	W1, W27, W28

0x42ff70 MUL	W19, W24, W1

0x42ff74 STR	W1, [SP, #100]

0x42ff78 BL	410210

0x42ff7c ORR	W21, WZR, W0

0x42ff80 BL	410240

0x42ff84 UDIV	W2, W19, W21

0x42ff88 ORR	W3, WZR, W0

0x42ff8c MSUB	W4, W2, W21, W19

0x42ff90 CMP	W0, W4

0x42ff94 B.CC	430268

0x42ff98 MADD	W16, W2, W3, W4

0x42ff9c ADD	W5, W2, W16

0x42ffa0 STR	W5, [SP, #104]

0x42ffa4 CMP	W16, W5

0x42ffa8 B.CS	430250

0x42ffac LDR	W6, [SP, #100]

0x42ffb0 STP	X25, X26, [SP, #64]

0x42ffb4 LDP	X25, X24, [X20, #16]

0x42ffb8 UDIV	W7, W16, W6

0x42ffbc MSUB	W11, W7, W6, W16

0x42ffc0 ADD	W8, W7, W22

0x42ffc4 SBFM	X4, X8, #0, #31

0x42ffc8 ADD	W11, W11, W28

0x42ffcc SUB	W21, W27, W11

0x42ffd0 LDP	X27, X26, [X20]

0x42ffd4 STR	W28, [SP, #108]

0x42ffd8 HINT	#0

0x42ffdc HINT	#0

(193) 0x42ffe0 CMP	W2, W21

(193) 0x42ffe4 CSEL	W2, W2, W21, #9

(193) 0x42ffe8 ADD	W20, W16, W2

(193) 0x42ffec CMP	W16, W20

(193) 0x42fff0 B.CS	430230

(193) 0x42fff4 LDR	X13, [X24]

(193) 0x42fff8 LDR	X14, [X25]

(193) 0x42fffc LDR	X17, [X26]

(193) 0x430000 MUL	X13, X4, X13

(193) 0x430004 LDR	X10, [X27]

(193) 0x430008 MUL	X14, X4, X14

(193) 0x43000c LDR	X16, [X24, #16]

(193) 0x430010 MUL	X17, X4, X17

(193) 0x430014 LDR	X22, [X25, #16]

(193) 0x430018 MUL	X10, X4, X10

(193) 0x43001c LDR	X21, [X26, #16]

(193) 0x430020 LDR	X19, [X27, #16]

(193) 0x430024 CMP	W2, #1

(193) 0x430028 B.EQ	4301e8

(193) 0x43002c UBFM	W12, W2, #1, #31

(193) 0x430030 SBFM	X3, X11, #0, #31

(193) 0x430034 UBFM	X12, X12, #60, #59

(193) 0x430038 ADD	X15, X13, X3

(193) 0x43003c SUB	X9, X12, #16

(193) 0x430040 UBFM	X15, X15, #61, #60

(193) 0x430044 UBFM	X18, X9, #4, #63

(193) 0x430048 ADD	X5, X10, X3

(193) 0x43004c ADD	X28, X18, #1

(193) 0x430050 SUB	X30, X15, #8

(193) 0x430054 ADD	X1, X19, X5,LSL #3

(193) 0x430058 ANDS	X9, X28, #0x3

(193) 0x43005c ADD	X28, X14, X3

(193) 0x430060 ADD	X3, X17, X3

(193) 0x430064 ADD	X7, X22, X28,LSL #3

(193) 0x430068 UBFM	X18, X5, #61, #60

(193) 0x43006c MOVZ	X0, #0

(193) 0x430070 ADD	X5, X21, X3,LSL #3

(193) 0x430074 ADD	X6, X16, X30

(193) 0x430078 ADD	X8, X16, X15

(193) 0x43007c UBFM	X28, X28, #61, #60

(193) 0x430080 UBFM	X3, X3, #61, #60

(193) 0x430084 B.EQ	430124

(193) 0x430088 CMP	X9, #1

(193) 0x43008c B.EQ	4300f0

(193) 0x430090 CMP	X9, #2

(193) 0x430094 B.EQ	4300c4

(193) 0x430098 LDR	Q28, [X16, X15]

(193) 0x43009c MOVZ	X0, #16

(193) 0x4300a0 LDR	Q30, [X22, X28]

(193) 0x4300a4 LDR	Q0, [X19, X18]

(193) 0x4300a8 FNEG	V1.2D, V28.2D

(193) 0x4300ac LDR	Q31, [X16, X30]

(193) 0x4300b0 LDR	Q29, [X21, X3]

(193) 0x4300b4 FMLA	V1.2D, V30.2D, V0.2D

(193) 0x4300b8 FADD	V2.2D, V1.2D, V31.2D

(193) 0x4300bc FDIV	V3.2D, V2.2D, V29.2D

(193) 0x4300c0 STR	Q3, [X19, X18]

(193) 0x4300c4 LDR	Q24, [X8, X0]

(193) 0x4300c8 LDR	Q26, [X7, X0]

(193) 0x4300cc LDR	Q4, [X1, X0]

(193) 0x4300d0 FNEG	V5.2D, V24.2D

(193) 0x4300d4 LDR	Q27, [X6, X0]

(193) 0x4300d8 LDR	Q25, [X5, X0]

(193) 0x4300dc FMLA	V5.2D, V26.2D, V4.2D

(193) 0x4300e0 FADD	V6.2D, V5.2D, V27.2D

(193) 0x4300e4 FDIV	V7.2D, V6.2D, V25.2D

(193) 0x4300e8 STR	Q7, [X1, X0]

(193) 0x4300ec ADD	X0, X0, #16

(193) 0x4300f0 LDR	Q20, [X8, X0]

(193) 0x4300f4 LDR	Q22, [X7, X0]

(193) 0x4300f8 LDR	Q16, [X1, X0]

(193) 0x4300fc FNEG	V17.2D, V20.2D

(193) 0x430100 LDR	Q23, [X6, X0]

(193) 0x430104 LDR	Q21, [X5, X0]

(193) 0x430108 FMLA	V17.2D, V22.2D, V16.2D

(193) 0x43010c FADD	V18.2D, V17.2D, V23.2D

(193) 0x430110 FDIV	V19.2D, V18.2D, V21.2D

(193) 0x430114 STR	Q19, [X1, X0]

(193) 0x430118 ADD	X0, X0, #16

(193) 0x43011c CMP	X0, X12

(193) 0x430120 B.EQ	4301dc

  (194) 0x430124 LDR	Q28, [X8, X0]

  (194) 0x430128 ADD	X30, X0, #16

  (194) 0x43012c ADD	X15, X0, #32

  (194) 0x430130 ADD	X9, X0, #48

  (194) 0x430134 LDR	Q30, [X7, X0]

  (194) 0x430138 LDR	Q0, [X1, X0]

  (194) 0x43013c FNEG	V1.2D, V28.2D

  (194) 0x430140 LDR	Q31, [X6, X0]

  (194) 0x430144 LDR	Q29, [X5, X0]

  (194) 0x430148 FMLA	V1.2D, V30.2D, V0.2D

  (194) 0x43014c FADD	V2.2D, V1.2D, V31.2D

  (194) 0x430150 FDIV	V3.2D, V2.2D, V29.2D

  (194) 0x430154 STR	Q3, [X1, X0]

  (194) 0x430158 ADD	X0, X0, #64

  (194) 0x43015c LDR	Q24, [X8, X30]

  (194) 0x430160 LDR	Q26, [X7, X30]

  (194) 0x430164 LDR	Q4, [X1, X30]

  (194) 0x430168 FNEG	V5.2D, V24.2D

  (194) 0x43016c LDR	Q27, [X6, X30]

  (194) 0x430170 LDR	Q25, [X5, X30]

  (194) 0x430174 FMLA	V5.2D, V26.2D, V4.2D

  (194) 0x430178 FADD	V6.2D, V5.2D, V27.2D

  (194) 0x43017c FDIV	V7.2D, V6.2D, V25.2D

  (194) 0x430180 STR	Q7, [X1, X30]

  (194) 0x430184 LDR	Q20, [X8, X15]

  (194) 0x430188 LDR	Q22, [X7, X15]

  (194) 0x43018c LDR	Q16, [X1, X15]

  (194) 0x430190 FNEG	V17.2D, V20.2D

  (194) 0x430194 LDR	Q23, [X6, X15]

  (194) 0x430198 LDR	Q21, [X5, X15]

  (194) 0x43019c FMLA	V17.2D, V22.2D, V16.2D

  (194) 0x4301a0 FADD	V18.2D, V17.2D, V23.2D

  (194) 0x4301a4 FDIV	V19.2D, V18.2D, V21.2D

  (194) 0x4301a8 STR	Q19, [X1, X15]

  (194) 0x4301ac LDR	Q28, [X8, X9]

  (194) 0x4301b0 LDR	Q30, [X7, X9]

  (194) 0x4301b4 LDR	Q0, [X1, X9]

  (194) 0x4301b8 FNEG	V1.2D, V28.2D

  (194) 0x4301bc LDR	Q31, [X6, X9]

  (194) 0x4301c0 LDR	Q29, [X5, X9]

  (194) 0x4301c4 FMLA	V1.2D, V30.2D, V0.2D

  (194) 0x4301c8 FADD	V2.2D, V1.2D, V31.2D

  (194) 0x4301cc FDIV	V3.2D, V2.2D, V29.2D

  (194) 0x4301d0 STR	Q3, [X1, X9]

  (194) 0x4301d4 CMP	X0, X12

  (194) 0x4301d8 B.NE	430124

(193) 0x4301dc TBZ	W2, #0, 43022c

(193) 0x4301e0 AND	W2, W2, #0xfffffffe

(193) 0x4301e4 ADD	W11, W11, W2

(193) 0x4301e8 SBFM	X12, X11, #0, #31

(193) 0x4301ec SUB	W1, W11, #1

(193) 0x4301f0 ADD	X6, X13, W1,SXTW

(193) 0x4301f4 ADD	X10, X10, X12

(193) 0x4301f8 ADD	X14, X14, X12

(193) 0x4301fc LDR	D24, [X16, X6,LSL #3]

(193) 0x430200 UBFM	X7, X10, #61, #60

(193) 0x430204 ADD	X13, X13, X12

(193) 0x430208 LDR	D26, [X22, X14,LSL #3]

(193) 0x43020c ADD	X22, X17, X12

(193) 0x430210 LDR	D4, [X19, X7]

(193) 0x430214 LDR	D5, [X16, X13,LSL #3]

(193) 0x430218 LDR	D27, [X21, X22,LSL #3]

(193) 0x43021c FMADD	D25, D26, D4, D24

(193) 0x430220 FSUB	D6, D25, S5

(193) 0x430224 FDIV	D7, D6, D27

(193) 0x430228 STR	D7, [X19, X7]

(193) 0x43022c ORR	W16, WZR, W20

(193) 0x430230 ADD	X4, X4, #1

(193) 0x430234 CMP	W23, W4

(193) 0x430238 B.LE	43024c

(193) 0x43023c LDP	W20, W11, [SP, #104]

(193) 0x430240 LDR	W21, [SP, #100]

(193) 0x430244 SUB	W2, W20, W16

(193) 0x430248 B	42ffe0

0x43024c LDP	X25, X26, [SP, #64]

0x430250 LDP	X27, X28, [SP, #80]

0x430254 LDP	X19, X20, [SP, #16]

0x430258 LDP	X21, X22, [SP, #32]

0x43025c LDP	X23, X24, [SP, #48]

0x430260 LDP	X29, X30, [SP], #112

0x430264 RET

0x430268 ADD	W2, W2, #1

0x43026c MOVZ	W4, #0

0x430270 B	42ff98

0x430274 HINT	#0

0x430278 HINT	#0

0x43027c HINT	#0

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 7.17 cycles (3.49x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:147
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:147

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes. The binary function is storing 9 bytes.

General properties

nb instructions	61
nb uops	56
loop length	244
used w registers	19
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.17	6.83	7.00	4.50	4.50
cycles	4.00	4.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.17	6.83	7.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.00
Dispatch	7.50
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	26%
load	40%
store	37%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42ff20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W23, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W19, [X20, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W23, W23, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W22, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 430254 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W28, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W27, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W24, W23, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W28, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 430250 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, W27, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W19, W24, W1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W1, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W19, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W4, W2, W21, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 430268 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W2, W3, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W5, W2, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W16, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 430250 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W6, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X25, X24, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
UDIV W7, W16, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W11, W7, W6, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W8, W7, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X4, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W11, W11, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W27, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X27, X26, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR W28, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
HINT #0																			N/A
HINT #0																			N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42ff98 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 7.17 cycles (3.49x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:147
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:147

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes. The binary function is storing 9 bytes.

General properties

nb instructions	61
nb uops	56
loop length	244
used w registers	19
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.17	6.83	7.00	4.50	4.50
cycles	4.00	4.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.17	6.83	7.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.00
Dispatch	7.50
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	26%
load	40%
store	37%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42ff20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W23, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W19, [X20, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W23, W23, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W22, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 430254 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W28, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W27, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W24, W23, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W28, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 430250 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, W27, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W19, W24, W1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W1, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W19, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W4, W2, W21, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 430268 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W2, W3, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W5, W2, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W16, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 430250 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W6, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X25, X24, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
UDIV W7, W16, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W11, W7, W6, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W8, W7, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X4, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W11, W11, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W27, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X27, X26, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR W28, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
HINT #0																			N/A
HINT #0																			N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42ff98 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.60	6.18
▼Loop 193 - advec_mom.cpp:148-149 - exec–	0.00	0.02
○Loop 194 - advec_mom.cpp:149-149 - exec	4.59	6.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code