OV - exec - Loop 175

	Loop Id: 175	Module: exec	Source: advec_cell.cpp:71-110 [...]	Coverage: 2.99%

0x42d868 ORR	V1.16B, V2.16B, V2.16B

0x42d86c ADD	V2.4S, V2.4S, V11.4S

0x42d870 LDR	Q3, [X20, X11]    [25]

0x42d874 ADD	V24.4S, V1.4S, V12.4S

0x42d878 SSHLL	V28.2D, V1.2S, #32

0x42d87c LDR	Q4, [X20, X12]    [25]

0x42d880 ADD	V7.4S, V1.4S, V14.4S

0x42d884 ADD	V26.4S, V1.4S, V13.4S

0x42d888 SSHLL2	V31.2D, V1.4S, #32

0x42d88c LDR	Q27, [X21, X11]    [6]

0x42d890 FCMGT	V25.2D, V3.2D, #0.0000000

0x42d894 SSHLL	V20.2D, V24.2S, #32

0x42d898 SMIN	V17.4S, V7.4S, V10.4S

0x42d89c FCMGT	V22.2D, V4.2D, #0.0000000

0x42d8a0 SSHLL	V23.2D, V26.2S, #32

0x42d8a4 FABS	V18.2D, V3.2D

0x42d8a8 SSHLL2	V0.2D, V24.4S, #32

0x42d8ac SSHLL2	V1.2D, V26.4S, #32

0x42d8b0 ORR	V19.16B, V25.16B, V25.16B

0x42d8b4 SSHLL	V21.2D, V17.2S, #32

0x42d8b8 SSHLL2	V30.2D, V17.4S, #32

0x42d8bc ORR	V16.16B, V22.16B, V22.16B

0x42d8c0 BSL	V19.16B, V20.16B, V28.16B

0x42d8c4 BIF	V28.16B, V20.16B, V25.16B

0x42d8c8 BIF	V23.16B, V21.16B, V25.16B

0x42d8cc BSL	V16.16B, V0.16B, V31.16B

0x42d8d0 FMOV	X13, D19

0x42d8d4 MOV	D7, V19.D[1]

0x42d8d8 FMOV	X15, D28

0x42d8dc MOV	D28, V28.D[1]

0x42d8e0 FMOV	X3, D23

0x42d8e4 BIF	V31.16B, V0.16B, V22.16B

0x42d8e8 BSL	V25.16B, V20.16B, V21.16B

0x42d8ec FMOV	X27, D16

0x42d8f0 FMOV	X28, D7

0x42d8f4 MOV	D17, V23.D[1]

0x42d8f8 MOV	D20, V16.D[1]

0x42d8fc FMOV	X10, D28

0x42d900 BIF	V1.16B, V30.16B, V22.16B

0x42d904 MOV	D24, V31.D[1]

0x42d908 FMOV	X1, D31

0x42d90c UBFM	X9, X13, #61, #60

0x42d910 BIT	V30.16B, V0.16B, V22.16B

0x42d914 UBFM	X26, X15, #61, #60

0x42d918 FMOV	X22, D20

0x42d91c FABS	V0.2D, V4.2D

0x42d920 LDR	D26, [X7, X9]    [3]

0x42d924 UBFM	X13, X3, #61, #60

0x42d928 MOV	D22, V1.D[1]

0x42d92c UBFM	X8, X27, #61, #60

0x42d930 FMOV	X18, D24

0x42d934 LDR	D21, [X9, X0]    [5]

0x42d938 UBFM	X14, X28, #61, #60

0x42d93c ADD	X3, X7, X14

0x42d940 UBFM	X4, X10, #61, #60

0x42d944 LDR	D23, [X0, X26]    [15]

0x42d948 UBFM	X1, X1, #61, #60

0x42d94c MOV	X28, V25.D[1]

0x42d950 FMOV	D31, D26

0x42d954 FMOV	X6, D17

0x42d958 FMOV	X15, D1

0x42d95c LDR	D19, [X7, X8]    [3]

0x42d960 UBFM	X10, X22, #61, #60

0x42d964 UBFM	X22, X18, #61, #60

0x42d968 MOV	X27, V30.D[1]

0x42d96c LD1	{V31.D[1]}, [X3]    [27]

0x42d970 ADD	X3, X14, X0

0x42d974 LD1	{V21.D[1]}, [X3]    [26]

0x42d978 ADD	X3, X0, X4

0x42d97c UBFM	X18, X6, #61, #60

0x42d980 LD1	{V23.D[1]}, [X3]    [24]

0x42d984 UBFM	X6, X15, #61, #60

0x42d988 FMOV	X3, D25

0x42d98c LDR	D16, [X16, X28,LSL #3]    [16]

0x42d990 FMOV	X15, D22

0x42d994 LDR	D22, [X8, X0]    [21]

0x42d998 FMOV	X28, D30

0x42d99c FDIV	V18.2D, V18.2D, V31.2D

0x42d9a0 LDR	D25, [X0, X1]    [15]

0x42d9a4 LDR	D7, [X16, X3,LSL #3]    [16]

0x42d9a8 ADD	X3, X7, X10

0x42d9ac FSUB	V28.2D, V23.2D, V21.2D

0x42d9b0 LD1	{V19.D[1]}, [X3]    [14]

0x42d9b4 ADD	X3, X10, X0

0x42d9b8 UBFM	X15, X15, #61, #60

0x42d9bc FADD	V1.2D, V18.2D, V29.2D

0x42d9c0 LDR	D30, [X0, X13]    [15]

0x42d9c4 FSUB	V26.2D, V15.2D, V18.2D

0x42d9c8 FSUB	V18.2D, V29.2D, V18.2D

0x42d9cc LD1	{V22.D[1]}, [X3]    [13]

0x42d9d0 ADD	X3, X0, X22

0x42d9d4 MOV	V7.D[1], V16.D[0]

0x42d9d8 LDR	D20, [X16, X28,LSL #3]    [16]

0x42d9dc ADD	X28, X0, X15

0x42d9e0 LDR	D31, [X0, X6]    [15]

0x42d9e4 FDIV	V23.2D, V27.2D, V7.2D

0x42d9e8 FDIV	V24.2D, V0.2D, V19.2D

0x42d9ec FABS	V0.2D, V28.2D

0x42d9f0 LD1	{V25.D[1]}, [X3]    [12]

0x42d9f4 ADD	X3, X14, X0

0x42d9f8 LDR	D19, [X16, X27,LSL #3]    [16]

0x42d9fc ADD	X27, X0, X18

0x42da00 FMOV	D27, D20

0x42da04 FMUL	V23.2D, V23.2D, V1.2D

0x42da08 LD1	{V30.D[1]}, [X27]    [20]

0x42da0c ADD	X27, X10, X0

0x42da10 FADD	V20.2D, V24.2D, V29.2D

0x42da14 LD1	{V31.D[1]}, [X28]    [23]

0x42da18 LDR	Q17, [X21, X12]    [6]

0x42da1c MOV	V27.D[1], V19.D[0]

0x42da20 FSUB	V25.2D, V25.2D, V22.2D

0x42da24 FMUL	V19.2D, V26.2D, V0.2D

0x42da28 FSUB	V30.2D, V21.2D, V30.2D

0x42da2c FDIV	V1.2D, V17.2D, V27.2D

0x42da30 FSUB	V27.2D, V15.2D, V24.2D

0x42da34 FSUB	V31.2D, V22.2D, V31.2D

0x42da38 FABS	V16.2D, V25.2D

0x42da3c FMUL	V17.2D, V1.2D, V20.2D

0x42da40 FABS	V7.2D, V30.2D

0x42da44 FMUL	V30.2D, V30.2D, V28.2D

0x42da48 FMUL	V20.2D, V27.2D, V16.2D

0x42da4c FABS	V1.2D, V31.2D

0x42da50 FMLA	V19.2D, V23.2D, V7.2D

0x42da54 FMLA	V20.2D, V17.2D, V1.2D

0x42da58 FCMLE	V28.2D, V28.2D, #0.0000000

0x42da5c FMUL	V31.2D, V31.2D, V25.2D

0x42da60 FCMLE	V25.2D, V25.2D, #0.0000000

0x42da64 FMINNM	V0.2D, V7.2D, V0.2D

0x42da68 FMINNM	V16.2D, V1.2D, V16.2D

0x42da6c FMUL	V19.2D, V19.2D, V6.2D

0x42da70 FCMGT	V7.2D, V30.2D, #0.0000000

0x42da74 BSL	V28.16B, V5.16B, V29.16B

0x42da78 FMUL	V30.2D, V20.2D, V6.2D

0x42da7c FSUB	V24.2D, V29.2D, V24.2D

0x42da80 BSL	V25.16B, V5.16B, V29.16B

0x42da84 FMUL	V18.2D, V18.2D, V28.2D

0x42da88 FMINNM	V28.2D, V19.2D, V0.2D

0x42da8c FMINNM	V20.2D, V30.2D, V16.2D

0x42da90 ORR	V0.16B, V21.16B, V21.16B

0x42da94 ORR	V16.16B, V22.16B, V22.16B

0x42da98 FMUL	V24.2D, V24.2D, V25.2D

0x42da9c FCMGT	V1.2D, V31.2D, #0.0000000

0x42daa0 FMLA	V0.2D, V18.2D, V28.2D

0x42daa4 FMLA	V16.2D, V24.2D, V20.2D

0x42daa8 BSL	V7.16B, V0.16B, V21.16B

0x42daac BSL	V1.16B, V16.16B, V22.16B

0x42dab0 FMUL	V30.2D, V3.2D, V7.2D

0x42dab4 FMUL	V31.2D, V4.2D, V1.2D

0x42dab8 STR	Q30, [X19, X11]    [28]

0x42dabc FABS	V3.2D, V30.2D

0x42dac0 STR	Q31, [X19, X12]    [28]

0x42dac4 LDR	D4, [X9, X0]    [5]

0x42dac8 LDR	D7, [X8, X0]    [21]

0x42dacc LDR	D25, [X7, X9]    [3]

0x42dad0 LDR	D22, [X7, X14]    [3]

0x42dad4 LD1	{V4.D[1]}, [X3]    [11]

0x42dad8 LDR	D18, [X7, X8]    [3]

0x42dadc LD1	{V7.D[1]}, [X27]    [19]

0x42dae0 MOV	V25.D[1], V22.D[0]

0x42dae4 LDR	D21, [X14, X2]    [9]

0x42dae8 LDR	D20, [X9, X2]    [5]

0x42daec ADD	X9, X10, X2

0x42daf0 FMUL	V19.2D, V4.2D, V25.2D

0x42daf4 LDR	D1, [X4, X2]    [29]

0x42daf8 LDR	D0, [X26, X2]    [1]

0x42dafc MOV	V20.D[1], V21.D[0]

0x42db00 LDR	D21, [X8, X2]    [21]

0x42db04 FDIV	V16.2D, V3.2D, V19.2D

0x42db08 LDR	D28, [X22, X2]    [7]

0x42db0c LDR	D24, [X1, X2]    [17]

0x42db10 MOV	V0.D[1], V1.D[0]

0x42db14 FSUB	V19.2D, V29.2D, V16.2D

0x42db18 LDR	D3, [X18, X2]    [22]

0x42db1c LDR	D25, [X13, X2]    [8]

0x42db20 FSUB	V22.2D, V0.2D, V20.2D

0x42db24 LD1	{V21.D[1]}, [X9]    [4]

0x42db28 MOV	V24.D[1], V28.D[0]

0x42db2c LDR	D1, [X15, X2]    [10]

0x42db30 LDR	D0, [X6, X2]    [2]

0x42db34 MOV	V25.D[1], V3.D[0]

0x42db38 FABS	V4.2D, V22.2D

0x42db3c FSUB	V25.2D, V20.2D, V25.2D

0x42db40 FSUB	V24.2D, V24.2D, V21.2D

0x42db44 MOV	V0.D[1], V1.D[0]

0x42db48 LDR	D1, [X7, X10]    [3]

0x42db4c FMUL	V26.2D, V26.2D, V4.2D

0x42db50 FSUB	V28.2D, V21.2D, V0.2D

0x42db54 FABS	V3.2D, V24.2D

0x42db58 FABS	V16.2D, V25.2D

0x42db5c MOV	V18.D[1], V1.D[0]

0x42db60 FMUL	V0.2D, V25.2D, V22.2D

0x42db64 FCMLE	V22.2D, V22.2D, #0.0000000

0x42db68 FMUL	V27.2D, V27.2D, V3.2D

0x42db6c FMLA	V26.2D, V23.2D, V16.2D

0x42db70 FABS	V23.2D, V28.2D

0x42db74 FMINNM	V4.2D, V16.2D, V4.2D

0x42db78 FMUL	V28.2D, V28.2D, V24.2D

0x42db7c FMLA	V27.2D, V17.2D, V23.2D

0x42db80 FMINNM	V17.2D, V23.2D, V3.2D

0x42db84 FMUL	V26.2D, V26.2D, V6.2D

0x42db88 FMUL	V7.2D, V7.2D, V18.2D

0x42db8c FCMLE	V18.2D, V24.2D, #0.0000000

0x42db90 FABS	V3.2D, V31.2D

0x42db94 BSL	V22.16B, V5.16B, V29.16B

0x42db98 FMUL	V24.2D, V27.2D, V6.2D

0x42db9c FMINNM	V16.2D, V26.2D, V4.2D

0x42dba0 FDIV	V1.2D, V3.2D, V7.2D

0x42dba4 BSL	V18.16B, V5.16B, V29.16B

0x42dba8 FCMGT	V25.2D, V0.2D, #0.0000000

0x42dbac FMINNM	V27.2D, V24.2D, V17.2D

0x42dbb0 FSUB	V23.2D, V29.2D, V1.2D

0x42dbb4 FMUL	V4.2D, V16.2D, V22.2D

0x42dbb8 ORR	V22.16B, V20.16B, V20.16B

0x42dbbc FCMGT	V0.2D, V28.2D, #0.0000000

0x42dbc0 FMUL	V28.2D, V27.2D, V18.2D

0x42dbc4 FMLA	V22.2D, V4.2D, V19.2D

0x42dbc8 ORR	V19.16B, V21.16B, V21.16B

0x42dbcc FMLA	V19.2D, V23.2D, V28.2D

0x42dbd0 BSL	V25.16B, V22.16B, V20.16B

0x42dbd4 FMUL	V30.2D, V30.2D, V25.2D

0x42dbd8 BSL	V0.16B, V19.16B, V21.16B

0x42dbdc FMUL	V31.2D, V31.2D, V0.2D

0x42dbe0 STR	Q30, [X17, X11]    [18]

0x42dbe4 ADD	X11, X11, #32

0x42dbe8 STR	Q31, [X17, X12]    [18]

0x42dbec ADD	X12, X12, #32

0x42dbf0 CMP	X11, X24

0x42dbf4 B.NE	42d868

/usr/include/c++/14/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 71 - 110

--------------------------------------------------------------------------------

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.11 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7, P8, P9,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	stl_algobase.h:238-238,advec_cell.cpp:71-110,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	42.00
CQA cycles if no scalar integer	38.00 - 41.96
CQA cycles if FP arith vectorized	31.13 - 41.96
CQA cycles if fully vectorized	20.98 - 41.96
Front-end cycles	28.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	6.50
P5 cycles	6.50
P6 cycles	42.00
P7 cycles	42.00
P8 cycles	42.00
P9 cycles	42.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	20.98 - 41.96
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	228.00
Nb uops	228.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.95
Nb FLOP add-sub	32.00
Nb FLOP mul	48.00
Nb FLOP fma	16.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.10
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	22.00
Stride indirect	3.00
Vectorization ratio all	63.68
Vectorization ratio load	9.09
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	65.26
Vector-efficiency ratio all	39.93
Vector-efficiency ratio load	27.27
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	39.21

Metric	Value
CQA speedup if no scalar integer	1.11 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7, P8, P9,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	stl_algobase.h:238-238,advec_cell.cpp:71-110,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	42.00
CQA cycles if no scalar integer	38.00 - 41.96
CQA cycles if FP arith vectorized	31.13 - 41.96
CQA cycles if fully vectorized	20.98 - 41.96
Front-end cycles	28.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	6.50
P5 cycles	6.50
P6 cycles	42.00
P7 cycles	42.00
P8 cycles	42.00
P9 cycles	42.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	20.98 - 41.96
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	228.00
Nb uops	228.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.95
Nb FLOP add-sub	32.00
Nb FLOP mul	48.00
Nb FLOP fma	16.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.10
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	22.00
Stride indirect	3.00
Vectorization ratio all	63.68
Vectorization ratio load	9.09
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	65.26
Vector-efficiency ratio all	39.93
Vector-efficiency ratio load	27.27
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	39.21

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:71-110
Module	exec

The loop is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71-110
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 39% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 42.00 to 41.96 cycles (1.00x speedup).

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

9% of VPU loads are used in vector version.
65% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 22 occurrence(s)
Constant non-unit stride: 4 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 124 FP arithmetical operations:

48: addition or subtraction (16 inside FMA instructions)
64: multiply (16 inside FMA instructions)
12: divide

The binary loop is loading 88 bytes.

Arithmetic intensity

Arithmetic intensity is 1.41 FP operations per loaded or stored byte.

General properties

nb instructions	228
nb uops	228
loop length	912
used w registers	0
used x registers	26
used b registers	0
used h registers	0
used s registers	0
used d registers	20
used q registers	6
used v registers	30
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.50 cycles
front end	28.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	6.50	6.50	6.50	6.50	42.00	42.00	42.00	42.00	16.00	16.00	16.00	0.00	0.00
cycles	0.50	0.50	6.50	6.50	6.50	6.50	42.00	42.00	42.00	42.00	16.00	16.00	16.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	20.98-41.96
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	28.50
Dispatch	42.00
DIV/SQRT	20.98-41.96
Data deps.	2.00
Overall L1	42.00

Vectorization ratios

INT

all	43%
load	9%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	65%

all	84%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	65%

INT+FP

all	63%
load	9%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	65%

Vector efficiency ratios

INT

all	33%
load	27%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	41%

INT+FP

all	39%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	39%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 42.00 cycles. At this rate:

2% of peak load performance is reached (2.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42d868

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
ORR V1.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ADD V2.4S, V2.4S, V11.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR Q3, [X20, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD V24.4S, V1.4S, V12.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V28.2D, V1.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
LDR Q4, [X20, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD V7.4S, V1.4S, V14.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ADD V26.4S, V1.4S, V13.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL2 V31.2D, V1.4S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
LDR Q27, [X21, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FCMGT V25.2D, V3.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V20.2D, V24.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
SMIN V17.4S, V7.4S, V10.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCMGT V22.2D, V4.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V23.2D, V26.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
FABS V18.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL2 V0.2D, V24.4S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
SSHLL2 V1.2D, V26.4S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
ORR V19.16B, V25.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V21.2D, V17.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
SSHLL2 V30.2D, V17.4S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
ORR V16.16B, V22.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V19.16B, V20.16B, V28.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BIF V28.16B, V20.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BIF V23.16B, V21.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V16.16B, V0.16B, V31.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMOV X13, D19	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV D7, V19.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X15, D28	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV D28, V28.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X3, D23	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
BIF V31.16B, V0.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V25.16B, V20.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMOV X27, D16	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FMOV X28, D7	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV D17, V23.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV D20, V16.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X10, D28	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
BIF V1.16B, V30.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV D24, V31.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X1, D31	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
BIT V30.16B, V0.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
UBFM X26, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X22, D20	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FABS V0.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D26, [X7, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
UBFM X13, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV D22, V1.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
UBFM X8, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X18, D24	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D21, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
UBFM X14, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X7, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X4, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X0, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV X28, V25.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FMOV D31, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X6, D17	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FMOV X15, D1	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D19, [X7, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
UBFM X10, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X22, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV X27, V30.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LD1 {V31.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V21.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X18, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V23.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
UBFM X6, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X3, D25	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D16, [X16, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X15, D22	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D22, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X28, D30	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FDIV V18.2D, V18.2D, V31.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LDR D25, [X0, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X3, X7, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FSUB V28.2D, V23.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V19.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X15, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V1.2D, V18.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D30, [X0, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB V26.2D, V15.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V18.2D, V29.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V22.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV V7.D[1], V16.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D20, [X16, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X28, X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X0, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV V23.2D, V27.2D, V7.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FDIV V24.2D, V0.2D, V19.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FABS V0.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V25.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X16, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X27, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D27, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL V23.2D, V23.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
LD1 {V30.D[1]}, [X27]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X27, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V20.2D, V24.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V31.D[1]}, [X28]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
LDR Q17, [X21, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOV V27.D[1], V19.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB V25.2D, V25.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V19.2D, V26.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSUB V30.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V1.2D, V17.2D, V27.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FSUB V27.2D, V15.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V31.2D, V22.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V16.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V17.2D, V1.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FABS V7.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V30.2D, V30.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V27.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FABS V1.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V19.2D, V23.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V20.2D, V17.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FCMLE V28.2D, V28.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V31.2D, V31.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMLE V25.2D, V25.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V0.2D, V7.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V16.2D, V1.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V19.2D, V19.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMGT V7.2D, V30.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V28.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V30.2D, V20.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSUB V24.2D, V29.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V25.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V18.2D, V18.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMINNM V28.2D, V19.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V20.2D, V30.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ORR V0.16B, V21.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ORR V16.16B, V22.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V24.2D, V24.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMGT V1.2D, V31.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V0.2D, V18.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V16.2D, V24.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
BSL V7.16B, V0.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V1.16B, V16.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V30.2D, V3.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V31.2D, V4.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q30, [X19, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
FABS V3.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q31, [X19, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR D4, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D25, [X7, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X7, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V4.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
LDR D18, [X7, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V7.D[1]}, [X27]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV V25.D[1], V22.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D21, [X14, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D20, [X9, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X9, X10, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V19.2D, V4.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
LDR D1, [X4, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D0, [X26, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV V20.D[1], V21.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D21, [X8, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV V16.2D, V3.2D, V19.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LDR D28, [X22, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D24, [X1, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV V0.D[1], V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB V19.2D, V29.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D3, [X18, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D25, [X13, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB V22.2D, V0.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V21.D[1]}, [X9]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV V24.D[1], V28.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D1, [X15, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D0, [X6, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV V25.D[1], V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS V4.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V25.2D, V20.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V24.2D, V24.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V0.D[1], V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D1, [X7, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL V26.2D, V26.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSUB V28.2D, V21.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V3.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V16.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V18.D[1], V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL V0.2D, V25.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMLE V22.2D, V22.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V27.2D, V27.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMLA V26.2D, V23.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FABS V23.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V4.2D, V16.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V28.2D, V28.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMLA V27.2D, V17.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMINNM V17.2D, V23.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V26.2D, V26.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V7.2D, V7.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMLE V18.2D, V24.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V3.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V22.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V24.2D, V27.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMINNM V16.2D, V26.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V1.2D, V3.2D, V7.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
BSL V18.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCMGT V25.2D, V0.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V27.2D, V24.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V23.2D, V29.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V4.2D, V16.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
ORR V22.16B, V20.16B, V20.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCMGT V0.2D, V28.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V28.2D, V27.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMLA V22.2D, V4.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ORR V19.16B, V21.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V19.2D, V23.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
BSL V25.16B, V22.16B, V20.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V30.2D, V30.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
BSL V0.16B, V19.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V31.2D, V31.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q30, [X17, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X11, X11, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR Q31, [X17, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X12, X12, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 42d868 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:71-110
Module	exec

The loop is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71-110
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

9% of VPU loads are used in vector version.
65% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 22 occurrence(s)
Constant non-unit stride: 4 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 124 FP arithmetical operations:

48: addition or subtraction (16 inside FMA instructions)
64: multiply (16 inside FMA instructions)
12: divide

The binary loop is loading 88 bytes.

Arithmetic intensity

Arithmetic intensity is 1.41 FP operations per loaded or stored byte.

General properties

nb instructions	228
nb uops	228
loop length	912
used w registers	0
used x registers	26
used b registers	0
used h registers	0
used s registers	0
used d registers	20
used q registers	6
used v registers	30
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.50 cycles
front end	28.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	6.50	6.50	6.50	6.50	42.00	42.00	42.00	42.00	16.00	16.00	16.00	0.00	0.00
cycles	0.50	0.50	6.50	6.50	6.50	6.50	42.00	42.00	42.00	42.00	16.00	16.00	16.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	20.98-41.96
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	28.50
Dispatch	42.00
DIV/SQRT	20.98-41.96
Data deps.	2.00
Overall L1	42.00

Vectorization ratios

INT

all	43%
load	9%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	65%

all	84%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	65%

INT+FP

all	63%
load	9%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	65%

Vector efficiency ratios

INT

all	33%
load	27%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	41%

INT+FP

all	39%
load	27%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	39%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 42.00 cycles. At this rate:

2% of peak load performance is reached (2.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42d868

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
ORR V1.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ADD V2.4S, V2.4S, V11.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR Q3, [X20, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD V24.4S, V1.4S, V12.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V28.2D, V1.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
LDR Q4, [X20, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD V7.4S, V1.4S, V14.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ADD V26.4S, V1.4S, V13.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL2 V31.2D, V1.4S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
LDR Q27, [X21, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FCMGT V25.2D, V3.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V20.2D, V24.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
SMIN V17.4S, V7.4S, V10.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCMGT V22.2D, V4.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V23.2D, V26.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
FABS V18.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL2 V0.2D, V24.4S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
SSHLL2 V1.2D, V26.4S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
ORR V19.16B, V25.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
SSHLL V21.2D, V17.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
SSHLL2 V30.2D, V17.4S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
ORR V16.16B, V22.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V19.16B, V20.16B, V28.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BIF V28.16B, V20.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BIF V23.16B, V21.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V16.16B, V0.16B, V31.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMOV X13, D19	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV D7, V19.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X15, D28	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV D28, V28.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X3, D23	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
BIF V31.16B, V0.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V25.16B, V20.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMOV X27, D16	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FMOV X28, D7	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV D17, V23.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV D20, V16.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X10, D28	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
BIF V1.16B, V30.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV D24, V31.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X1, D31	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
BIT V30.16B, V0.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
UBFM X26, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X22, D20	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FABS V0.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D26, [X7, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
UBFM X13, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV D22, V1.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
UBFM X8, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X18, D24	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D21, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
UBFM X14, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X7, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X4, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X0, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV X28, V25.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FMOV D31, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV X6, D17	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FMOV X15, D1	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D19, [X7, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
UBFM X10, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X22, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV X27, V30.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LD1 {V31.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V21.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X18, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V23.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
UBFM X6, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X3, D25	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D16, [X16, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X15, D22	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D22, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X28, D30	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FDIV V18.2D, V18.2D, V31.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LDR D25, [X0, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X3, X7, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FSUB V28.2D, V23.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V19.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X15, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V1.2D, V18.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D30, [X0, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB V26.2D, V15.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V18.2D, V29.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V22.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV V7.D[1], V16.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D20, [X16, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X28, X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X0, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV V23.2D, V27.2D, V7.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FDIV V24.2D, V0.2D, V19.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FABS V0.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V25.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X3, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X16, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X27, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D27, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL V23.2D, V23.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
LD1 {V30.D[1]}, [X27]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X27, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V20.2D, V24.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V31.D[1]}, [X28]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
LDR Q17, [X21, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOV V27.D[1], V19.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB V25.2D, V25.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V19.2D, V26.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSUB V30.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V1.2D, V17.2D, V27.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FSUB V27.2D, V15.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V31.2D, V22.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V16.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V17.2D, V1.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FABS V7.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V30.2D, V30.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V27.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FABS V1.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V19.2D, V23.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V20.2D, V17.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FCMLE V28.2D, V28.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V31.2D, V31.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMLE V25.2D, V25.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V0.2D, V7.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V16.2D, V1.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V19.2D, V19.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMGT V7.2D, V30.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V28.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V30.2D, V20.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSUB V24.2D, V29.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V25.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V18.2D, V18.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMINNM V28.2D, V19.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V20.2D, V30.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ORR V0.16B, V21.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
ORR V16.16B, V22.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V24.2D, V24.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMGT V1.2D, V31.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V0.2D, V18.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V16.2D, V24.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
BSL V7.16B, V0.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V1.16B, V16.16B, V22.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V30.2D, V3.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V31.2D, V4.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q30, [X19, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
FABS V3.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q31, [X19, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR D4, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D25, [X7, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X7, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V4.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
LDR D18, [X7, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V7.D[1]}, [X27]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV V25.D[1], V22.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D21, [X14, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D20, [X9, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X9, X10, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V19.2D, V4.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
LDR D1, [X4, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D0, [X26, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV V20.D[1], V21.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D21, [X8, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV V16.2D, V3.2D, V19.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LDR D28, [X22, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D24, [X1, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV V0.D[1], V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB V19.2D, V29.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D3, [X18, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D25, [X13, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB V22.2D, V0.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V21.D[1]}, [X9]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV V24.D[1], V28.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D1, [X15, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D0, [X6, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV V25.D[1], V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS V4.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V25.2D, V20.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V24.2D, V24.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V0.D[1], V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D1, [X7, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL V26.2D, V26.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSUB V28.2D, V21.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V3.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V16.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V18.D[1], V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL V0.2D, V25.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMLE V22.2D, V22.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V27.2D, V27.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMLA V26.2D, V23.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FABS V23.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V4.2D, V16.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V28.2D, V28.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMLA V27.2D, V17.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMINNM V17.2D, V23.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V26.2D, V26.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V7.2D, V7.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FCMLE V18.2D, V24.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V3.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V22.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V24.2D, V27.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMINNM V16.2D, V26.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V1.2D, V3.2D, V7.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
BSL V18.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCMGT V25.2D, V0.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V27.2D, V24.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V23.2D, V29.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V4.2D, V16.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
ORR V22.16B, V20.16B, V20.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FCMGT V0.2D, V28.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V28.2D, V27.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMLA V22.2D, V4.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ORR V19.16B, V21.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMLA V19.2D, V23.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
BSL V25.16B, V22.16B, V20.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V30.2D, V30.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
BSL V0.16B, V19.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V31.2D, V31.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q30, [X17, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X11, X11, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR Q31, [X17, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X12, X12, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 42d868 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code