OV - exec - Loop 246

	Loop Id: 246	Module: exec	Source: ideal_gas.cpp:39-45 [...]	Coverage: 0.01%

0x437160 CMP	W2, W30

0x437164 CSEL	W2, W2, W30, #9

0x437168 ADD	W19, W21, W2

0x43716c CMP	W21, W19

0x437170 B.CS	437404

0x437174 LDR	X13, [X26]

0x437178 LDR	X14, [X25]

0x43717c LDR	X15, [X27]

0x437180 MUL	X12, X5, X13

0x437184 LDR	X16, [X28]

0x437188 MUL	X14, X5, X14

0x43718c LDR	X20, [X25, #16]

0x437190 MUL	X13, X5, X15

0x437194 LDR	X21, [X26, #16]

0x437198 MUL	X10, X5, X16

0x43719c LDR	X30, [X27, #16]

0x4371a0 LDR	X18, [X28, #16]

0x4371a4 CMP	W2, #1

0x4371a8 B.EQ	4373b4

0x4371ac UBFM	W17, W2, #1, #31

0x4371b0 SBFM	X3, X4, #0, #31

0x4371b4 UBFM	X11, X17, #60, #59

0x4371b8 ADD	X6, X10, X3

0x4371bc SUB	X7, X11, #16

0x4371c0 ADD	X17, X13, X3

0x4371c4 ADD	X1, X18, X6,LSL #3

0x4371c8 UBFM	X9, X7, #4, #63

0x4371cc ADD	X16, X12, X3

0x4371d0 ADD	X8, X30, X17,LSL #3

0x4371d4 ADD	X15, X9, #1

0x4371d8 ADD	X3, X14, X3

0x4371dc ADD	X7, X21, X16,LSL #3

0x4371e0 ANDS	X9, X15, #0x3

0x4371e4 MOVZ	X0, #0

0x4371e8 UBFM	X15, X6, #61, #60

0x4371ec UBFM	X17, X17, #61, #60

0x4371f0 ADD	X6, X20, X3,LSL #3

0x4371f4 UBFM	X16, X16, #61, #60

0x4371f8 UBFM	X3, X3, #61, #60

0x4371fc B.EQ	4372c0

0x437200 CMP	X9, #1

0x437204 B.EQ	437280

0x437208 CMP	X9, #2

0x43720c B.EQ	437248

0x437210 LDR	Q23, [X18, X15]

0x437214 MOVZ	X0, #16

0x437218 LDR	Q30, [X30, X17]

0x43721c FDIV	V31.2D, V27.2D, V23.2D

0x437220 FMUL	V0.2D, V30.2D, V23.2D

0x437224 FMUL	V1.2D, V31.2D, V31.2D

0x437228 FMUL	V2.2D, V0.2D, V28.2D

0x43722c STR	Q2, [X21, X16]

0x437230 LDR	Q3, [X18, X15]

0x437234 FMUL	V4.2D, V3.2D, V29.2D

0x437238 FMUL	V5.2D, V4.2D, V2.2D

0x43723c FMUL	V6.2D, V5.2D, V1.2D

0x437240 FSQRT	V7.2D, V6.2D

0x437244 STR	Q7, [X20, X3]

0x437248 LDR	Q16, [X1, X0]

0x43724c LDR	Q17, [X8, X0]

0x437250 FDIV	V18.2D, V27.2D, V16.2D

0x437254 FMUL	V19.2D, V17.2D, V16.2D

0x437258 FMUL	V20.2D, V18.2D, V18.2D

0x43725c FMUL	V21.2D, V19.2D, V28.2D

0x437260 STR	Q21, [X7, X0]

0x437264 LDR	Q22, [X1, X0]

0x437268 FMUL	V23.2D, V22.2D, V29.2D

0x43726c FMUL	V30.2D, V23.2D, V21.2D

0x437270 FMUL	V31.2D, V30.2D, V20.2D

0x437274 FSQRT	V0.2D, V31.2D

0x437278 STR	Q0, [X6, X0]

0x43727c ADD	X0, X0, #16

0x437280 LDR	Q1, [X1, X0]

0x437284 LDR	Q2, [X8, X0]

0x437288 FDIV	V3.2D, V27.2D, V1.2D

0x43728c FMUL	V4.2D, V2.2D, V1.2D

0x437290 FMUL	V5.2D, V3.2D, V3.2D

0x437294 FMUL	V6.2D, V4.2D, V28.2D

0x437298 STR	Q6, [X7, X0]

0x43729c LDR	Q7, [X1, X0]

0x4372a0 FMUL	V16.2D, V7.2D, V29.2D

0x4372a4 FMUL	V17.2D, V16.2D, V6.2D

0x4372a8 FMUL	V18.2D, V17.2D, V5.2D

0x4372ac FSQRT	V19.2D, V18.2D

0x4372b0 STR	Q19, [X6, X0]

0x4372b4 ADD	X0, X0, #16

0x4372b8 CMP	X11, X0

0x4372bc B.EQ	4373a8

  (247) 0x4372c0 LDR	Q20, [X1, X0]

  (247) 0x4372c4 ADD	X17, X0, #16

  (247) 0x4372c8 ADD	X15, X0, #32

  (247) 0x4372cc ADD	X9, X0, #48

  (247) 0x4372d0 LDR	Q21, [X8, X0]

  (247) 0x4372d4 FDIV	V22.2D, V27.2D, V20.2D

  (247) 0x4372d8 FMUL	V30.2D, V21.2D, V20.2D

  (247) 0x4372dc FMUL	V23.2D, V22.2D, V22.2D

  (247) 0x4372e0 FMUL	V0.2D, V30.2D, V28.2D

  (247) 0x4372e4 STR	Q0, [X7, X0]

  (247) 0x4372e8 LDR	Q31, [X1, X0]

  (247) 0x4372ec FMUL	V1.2D, V31.2D, V29.2D

  (247) 0x4372f0 FMUL	V2.2D, V1.2D, V0.2D

  (247) 0x4372f4 FMUL	V3.2D, V2.2D, V23.2D

  (247) 0x4372f8 FSQRT	V4.2D, V3.2D

  (247) 0x4372fc STR	Q4, [X6, X0]

  (247) 0x437300 ADD	X0, X0, #64

  (247) 0x437304 LDR	Q5, [X1, X17]

  (247) 0x437308 LDR	Q6, [X8, X17]

  (247) 0x43730c FDIV	V7.2D, V27.2D, V5.2D

  (247) 0x437310 FMUL	V16.2D, V6.2D, V5.2D

  (247) 0x437314 FMUL	V17.2D, V7.2D, V7.2D

  (247) 0x437318 FMUL	V18.2D, V16.2D, V28.2D

  (247) 0x43731c STR	Q18, [X7, X17]

  (247) 0x437320 LDR	Q19, [X1, X17]

  (247) 0x437324 FMUL	V20.2D, V19.2D, V29.2D

  (247) 0x437328 FMUL	V21.2D, V20.2D, V18.2D

  (247) 0x43732c FMUL	V22.2D, V21.2D, V17.2D

  (247) 0x437330 FSQRT	V30.2D, V22.2D

  (247) 0x437334 STR	Q30, [X6, X17]

  (247) 0x437338 LDR	Q23, [X1, X15]

  (247) 0x43733c LDR	Q0, [X8, X15]

  (247) 0x437340 FDIV	V31.2D, V27.2D, V23.2D

  (247) 0x437344 FMUL	V1.2D, V0.2D, V23.2D

  (247) 0x437348 FMUL	V2.2D, V31.2D, V31.2D

  (247) 0x43734c FMUL	V3.2D, V1.2D, V28.2D

  (247) 0x437350 STR	Q3, [X7, X15]

  (247) 0x437354 LDR	Q4, [X1, X15]

  (247) 0x437358 FMUL	V5.2D, V4.2D, V29.2D

  (247) 0x43735c FMUL	V6.2D, V5.2D, V3.2D

  (247) 0x437360 FMUL	V7.2D, V6.2D, V2.2D

  (247) 0x437364 FSQRT	V16.2D, V7.2D

  (247) 0x437368 STR	Q16, [X6, X15]

  (247) 0x43736c LDR	Q17, [X1, X9]

  (247) 0x437370 LDR	Q18, [X8, X9]

  (247) 0x437374 FDIV	V19.2D, V27.2D, V17.2D

  (247) 0x437378 FMUL	V20.2D, V18.2D, V17.2D

  (247) 0x43737c FMUL	V21.2D, V19.2D, V19.2D

  (247) 0x437380 FMUL	V22.2D, V20.2D, V28.2D

  (247) 0x437384 STR	Q22, [X7, X9]

  (247) 0x437388 LDR	Q30, [X1, X9]

  (247) 0x43738c FMUL	V23.2D, V30.2D, V29.2D

  (247) 0x437390 FMUL	V0.2D, V23.2D, V22.2D

  (247) 0x437394 FMUL	V31.2D, V0.2D, V21.2D

  (247) 0x437398 FSQRT	V1.2D, V31.2D

  (247) 0x43739c STR	Q1, [X6, X9]

  (247) 0x4373a0 CMP	X11, X0

  (247) 0x4373a4 B.NE	4372c0

0x4373a8 TBZ	W2, #0, 437400

0x4373ac AND	W2, W2, #0xfffffffe

0x4373b0 ADD	W4, W4, W2

0x4373b4 SBFM	X11, X4, #0, #31

0x4373b8 ADD	X10, X10, X11

0x4373bc ADD	X13, X13, X11

0x4373c0 UBFM	X1, X10, #61, #60

0x4373c4 ADD	X12, X12, X11

0x4373c8 LDR	D2, [X30, X13,LSL #3]

0x4373cc ADD	X14, X14, X11

0x4373d0 LDR	D3, [X18, X1]

0x4373d4 FMUL	D4, D3, D2

0x4373d8 FDIV	D5, D24, D3

0x4373dc FMUL	D6, D4, D25

0x4373e0 STR	D6, [X21, X12,LSL #3]

0x4373e4 LDR	D7, [X18, X1]

0x4373e8 FMUL	D16, D5, D5

0x4373ec FMUL	D17, D7, D26

0x4373f0 FMUL	D18, D17, D6

0x4373f4 FMUL	D19, D18, D16

0x4373f8 FSQRT	D20, D19

0x4373fc STR	D20, [X20, X14,LSL #3]

0x437400 ORR	W21, WZR, W19

0x437404 ADD	X5, X5, #1

0x437408 CMP	W22, W5

0x43740c B.LE	43743c

0x437410 LDR	W19, [SP, #108]

0x437414 ORR	W4, WZR, W23

0x437418 ORR	W30, WZR, W24

0x43741c SUB	W2, W19, W21

0x437420 B	437160

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 39 - 45

--------------------------------------------------------------------------------

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►96.74+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.17+	GOMP_parallel		libgomp.so.1.0.0
○	ideal_gas(global_variables&, i[...]	ideal_gas.cpp:47	exec
○	PdV(global_variables&, bool)	PdV.cpp:115	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:64	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.17 - 1.17
CQA speedup if FP arith vectorized	1.08
CQA speedup if fully vectorized	1.08 - 1.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.65 - 3.41
Bottlenecks	P6, P8,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	ideal_gas.cpp:39-45,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.48 - 50.78
CQA cycles if no scalar integer	20.98 - 43.54
CQA cycles if FP arith vectorized	22.73 - 47.16
CQA cycles if fully vectorized	22.73 - 47.16
Front-end cycles	14.88
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	12.25
P3 cycles	12.25
P4 cycles	12.25
P5 cycles	12.25
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	9.67
P11 cycles	9.67
P12 cycles	9.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	24.48 - 50.78
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	119.00
Nb uops	119.00
Nb loads	NA
Nb stores	8.00
Nb stack references	1.00
FLOP/cycle	2.29 - 1.10
Nb FLOP add-sub	0.00
Nb FLOP mul	42.00
Nb FLOP fma	0.00
Nb FLOP div	7.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	7.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.06 - 0.12
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	57.35
Vectorization ratio load	75.00
Vectorization ratio store	75.00
Vectorization ratio mul	72.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	75.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	39.34
Vector-efficiency ratio load	43.75
Vector-efficiency ratio store	43.75
Vector-efficiency ratio mul	43.00
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	43.75
Vector-efficiency ratio other	26.04

Metric	Value
CQA speedup if no scalar integer	1.17 - 1.17
CQA speedup if FP arith vectorized	1.08
CQA speedup if fully vectorized	1.08 - 1.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.65 - 3.41
Bottlenecks	P6, P8,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	ideal_gas.cpp:39-45,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.48 - 50.78
CQA cycles if no scalar integer	20.98 - 43.54
CQA cycles if FP arith vectorized	22.73 - 47.16
CQA cycles if fully vectorized	22.73 - 47.16
Front-end cycles	14.88
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	12.25
P3 cycles	12.25
P4 cycles	12.25
P5 cycles	12.25
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	9.67
P11 cycles	9.67
P12 cycles	9.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	24.48 - 50.78
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	119.00
Nb uops	119.00
Nb loads	NA
Nb stores	8.00
Nb stack references	1.00
FLOP/cycle	2.29 - 1.10
Nb FLOP add-sub	0.00
Nb FLOP mul	42.00
Nb FLOP fma	0.00
Nb FLOP div	7.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	7.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.06 - 0.12
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	57.35
Vectorization ratio load	75.00
Vectorization ratio store	75.00
Vectorization ratio mul	72.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	75.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	39.34
Vector-efficiency ratio load	43.75
Vector-efficiency ratio store	43.75
Vector-efficiency ratio mul	43.00
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	43.75
Vector-efficiency ratio other	26.04

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	ideal_gas.cpp:39-45
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39-45
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 50.78 to 43.54 cycles (1.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 39% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 50.78 to 47.16 cycles (1.08x speedup).

Details

57% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU loads are used in vector version.
75% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
72% of VPU multiply instructions are used in vector version.
75% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.78 to 13.88 cycles (3.66x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 56 FP arithmetical operations:

42: multiply
7: divide
7: square root

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 18.67 FP operations per loaded or stored byte.

General properties

nb instructions	119
nb uops	119
loop length	476
used w registers	11
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	14
used q registers	13
used v registers	21
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	12.25	12.25	12.25	12.25	10.00	10.00	10.00	10.00	9.67	9.67	9.67	0.00	0.00
cycles	4.50	4.50	12.25	12.25	12.25	12.25	10.00	10.00	10.00	10.00	9.67	9.67	9.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

24.48-50.78

Cycles summary

Front-end	14.88
Dispatch	12.25
DIV/SQRT	24.48-50.78
Overall L1	24.48-50.78

Vectorization ratios

INT

all	41%
load	75%
store	75%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	75%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	75%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	75%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	57%
load	75%
store	75%
mul	72%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	75%
other	0%

Vector efficiency ratios

INT

all	35%
load	43%
store	43%
mul	25%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	43%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	43%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	43%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	39%
load	43%
store	43%
mul	43%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	43%
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.78 cycles. At this rate:

0% of peak load performance is reached (0.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 437160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W2, W2, W30, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W19, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W21, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 437404 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X14, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X15, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X12, X5, X13	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X14, X5, X14	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X20, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X13, X5, X15	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X21, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X10, X5, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X30, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X28, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4373b4 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W17, W2, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X3, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X17, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X10, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X18, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X9, X7, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X30, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X21, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X9, X15, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X15, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X17, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X3, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 4372c0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437280 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437248 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q23, [X18, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q30, [X30, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V31.2D, V27.2D, V23.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V0.2D, V30.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V1.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V2.2D, V0.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q2, [X21, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q3, [X18, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V4.2D, V3.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V5.2D, V4.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V5.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V7.2D, V6.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q7, [X20, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q16, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q17, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V18.2D, V27.2D, V16.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V19.2D, V17.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V18.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V19.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q21, [X7, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q22, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V23.2D, V22.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V30.2D, V23.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V31.2D, V30.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V0.2D, V31.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q0, [X6, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q1, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q2, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V3.2D, V27.2D, V1.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V4.2D, V2.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V5.2D, V3.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V4.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q6, [X7, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q7, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V16.2D, V7.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V17.2D, V16.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V18.2D, V17.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V19.2D, V18.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q19, [X6, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4373a8 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBZ W2, #0, 437400 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W2, W2, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X11, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X14, X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D4, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D5, D24, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D6, D4, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D6, [X21, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D7, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D16, D5, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D17, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D18, D17, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D19, D18, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FSQRT D20, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
STR D20, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ORR W21, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W22, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 43743c <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR W4, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR W30, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W2, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 437160 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	ideal_gas.cpp:39-45
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39-45
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

57% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU loads are used in vector version.
75% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
72% of VPU multiply instructions are used in vector version.
75% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.78 to 13.88 cycles (3.66x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 56 FP arithmetical operations:

42: multiply
7: divide
7: square root

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 18.67 FP operations per loaded or stored byte.

General properties

nb instructions	119
nb uops	119
loop length	476
used w registers	11
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	14
used q registers	13
used v registers	21
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	12.25	12.25	12.25	12.25	10.00	10.00	10.00	10.00	9.67	9.67	9.67	0.00	0.00
cycles	4.50	4.50	12.25	12.25	12.25	12.25	10.00	10.00	10.00	10.00	9.67	9.67	9.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

24.48-50.78

Cycles summary

Front-end	14.88
Dispatch	12.25
DIV/SQRT	24.48-50.78
Overall L1	24.48-50.78

Vectorization ratios

INT

all	41%
load	75%
store	75%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	75%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	75%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	75%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	57%
load	75%
store	75%
mul	72%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	75%
other	0%

Vector efficiency ratios

INT

all	35%
load	43%
store	43%
mul	25%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	43%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	43%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	43%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	39%
load	43%
store	43%
mul	43%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	43%
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.78 cycles. At this rate:

0% of peak load performance is reached (0.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 437160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W2, W2, W30, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W19, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W21, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 437404 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X14, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X15, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X12, X5, X13	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X14, X5, X14	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X20, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X13, X5, X15	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X21, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X10, X5, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X30, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X28, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4373b4 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W17, W2, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X3, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X17, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X10, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X18, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X9, X7, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X30, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X21, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X9, X15, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X15, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X17, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X20, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X3, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 4372c0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437280 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 437248 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q23, [X18, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q30, [X30, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V31.2D, V27.2D, V23.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V0.2D, V30.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V1.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V2.2D, V0.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q2, [X21, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q3, [X18, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V4.2D, V3.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V5.2D, V4.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V5.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V7.2D, V6.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q7, [X20, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q16, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q17, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V18.2D, V27.2D, V16.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V19.2D, V17.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V18.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V19.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q21, [X7, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q22, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V23.2D, V22.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V30.2D, V23.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V31.2D, V30.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V0.2D, V31.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q0, [X6, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q1, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q2, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V3.2D, V27.2D, V1.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V4.2D, V2.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V5.2D, V3.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V4.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q6, [X7, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q7, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V16.2D, V7.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V17.2D, V16.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V18.2D, V17.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V19.2D, V18.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q19, [X6, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4373a8 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBZ W2, #0, 437400 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W2, W2, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X11, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X14, X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D4, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D5, D24, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D6, D4, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D6, [X21, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D7, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D16, D5, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D17, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D18, D17, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D19, D18, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FSQRT D20, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
STR D20, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ORR W21, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W22, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 43743c <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR W4, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR W30, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W2, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 437160 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code