OV - exec - Loop 247

	Loop Id: 247	Module: exec	Source: ideal_gas.cpp:40-45	Coverage: 4.59%

0x4372c0 LDR	Q20, [X1, X0]    [4]

0x4372c4 ADD	X17, X0, #16

0x4372c8 ADD	X15, X0, #32

0x4372cc ADD	X9, X0, #48

0x4372d0 LDR	Q21, [X8, X0]    [3]

0x4372d4 FDIV	V22.2D, V27.2D, V20.2D

0x4372d8 FMUL	V30.2D, V21.2D, V20.2D

0x4372dc FMUL	V23.2D, V22.2D, V22.2D

0x4372e0 FMUL	V0.2D, V30.2D, V28.2D

0x4372e4 STR	Q0, [X7, X0]    [2]

0x4372e8 LDR	Q31, [X1, X0]    [4]

0x4372ec FMUL	V1.2D, V31.2D, V29.2D

0x4372f0 FMUL	V2.2D, V1.2D, V0.2D

0x4372f4 FMUL	V3.2D, V2.2D, V23.2D

0x4372f8 FSQRT	V4.2D, V3.2D

0x4372fc STR	Q4, [X6, X0]    [1]

0x437300 ADD	X0, X0, #64

0x437304 LDR	Q5, [X1, X17]    [4]

0x437308 LDR	Q6, [X8, X17]    [3]

0x43730c FDIV	V7.2D, V27.2D, V5.2D

0x437310 FMUL	V16.2D, V6.2D, V5.2D

0x437314 FMUL	V17.2D, V7.2D, V7.2D

0x437318 FMUL	V18.2D, V16.2D, V28.2D

0x43731c STR	Q18, [X7, X17]    [2]

0x437320 LDR	Q19, [X1, X17]    [4]

0x437324 FMUL	V20.2D, V19.2D, V29.2D

0x437328 FMUL	V21.2D, V20.2D, V18.2D

0x43732c FMUL	V22.2D, V21.2D, V17.2D

0x437330 FSQRT	V30.2D, V22.2D

0x437334 STR	Q30, [X6, X17]    [1]

0x437338 LDR	Q23, [X1, X15]    [4]

0x43733c LDR	Q0, [X8, X15]    [3]

0x437340 FDIV	V31.2D, V27.2D, V23.2D

0x437344 FMUL	V1.2D, V0.2D, V23.2D

0x437348 FMUL	V2.2D, V31.2D, V31.2D

0x43734c FMUL	V3.2D, V1.2D, V28.2D

0x437350 STR	Q3, [X7, X15]    [2]

0x437354 LDR	Q4, [X1, X15]    [4]

0x437358 FMUL	V5.2D, V4.2D, V29.2D

0x43735c FMUL	V6.2D, V5.2D, V3.2D

0x437360 FMUL	V7.2D, V6.2D, V2.2D

0x437364 FSQRT	V16.2D, V7.2D

0x437368 STR	Q16, [X6, X15]    [1]

0x43736c LDR	Q17, [X1, X9]    [4]

0x437370 LDR	Q18, [X8, X9]    [3]

0x437374 FDIV	V19.2D, V27.2D, V17.2D

0x437378 FMUL	V20.2D, V18.2D, V17.2D

0x43737c FMUL	V21.2D, V19.2D, V19.2D

0x437380 FMUL	V22.2D, V20.2D, V28.2D

0x437384 STR	Q22, [X7, X9]    [2]

0x437388 LDR	Q30, [X1, X9]    [4]

0x43738c FMUL	V23.2D, V30.2D, V29.2D

0x437390 FMUL	V0.2D, V23.2D, V22.2D

0x437394 FMUL	V31.2D, V0.2D, V21.2D

0x437398 FSQRT	V1.2D, V31.2D

0x43739c STR	Q1, [X6, X9]    [1]

0x4373a0 CMP	X11, X0

0x4373a4 B.NE	4372c0

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 40 - 45

--------------------------------------------------------------------------------

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.80 - 5.80
Bottlenecks	P6, P8,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	ideal_gas.cpp:40-45
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 58.05
CQA cycles if no scalar integer	27.97 - 58.05
CQA cycles if FP arith vectorized	27.97 - 58.05
CQA cycles if fully vectorized	27.97 - 58.05
Front-end cycles	7.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	6.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 58.05
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	2.29 - 1.10
Nb FLOP add-sub	0.00
Nb FLOP mul	48.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.80 - 5.80
Bottlenecks	P6, P8,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	ideal_gas.cpp:40-45
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 58.05
CQA cycles if no scalar integer	27.97 - 58.05
CQA cycles if FP arith vectorized	27.97 - 58.05
CQA cycles if fully vectorized	27.97 - 58.05
Front-end cycles	7.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	6.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 58.05
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	2.29 - 1.10
Nb FLOP add-sub	0.00
Nb FLOP mul	48.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	ideal_gas.cpp:40-45
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:40-45.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 256 bits (SSE/AVX-128 instructions on AVX/AVX2 processors).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 58.05 to 8.00 cycles (7.26x speedup).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

48: multiply
8: divide
8: square root

The binary loop does not load or store any data.

General properties

nb instructions	58
nb uops	58
loop length	232
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	16
used v registers	21
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	10.00	10.00	10.00	10.00	6.67	6.67	6.67	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	10.00	10.00	10.00	10.00	6.67	6.67	6.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-58.05
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.25
Dispatch	10.00
DIV/SQRT	27.97-58.05
Data deps.	1.00
Overall L1	27.97-58.05

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	50%
load	50%
store	50%
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 58.05 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4372c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR Q20, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X17, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X0, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q21, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V22.2D, V27.2D, V20.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V30.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V23.2D, V22.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V0.2D, V30.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q0, [X7, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q31, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V1.2D, V31.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V2.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V3.2D, V2.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V4.2D, V3.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q4, [X6, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q5, [X1, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q6, [X8, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V7.2D, V27.2D, V5.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V16.2D, V6.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V17.2D, V7.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V18.2D, V16.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q18, [X7, X17]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q19, [X1, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V20.2D, V19.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V20.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V22.2D, V21.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V30.2D, V22.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q30, [X6, X17]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q23, [X1, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q0, [X8, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V31.2D, V27.2D, V23.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V1.2D, V0.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V2.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V3.2D, V1.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q3, [X7, X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q4, [X1, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V5.2D, V4.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V5.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V7.2D, V6.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V16.2D, V7.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q16, [X6, X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q17, [X1, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q18, [X8, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V19.2D, V27.2D, V17.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V20.2D, V18.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V19.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V22.2D, V20.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q22, [X7, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q30, [X1, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V23.2D, V30.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V0.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V31.2D, V0.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V1.2D, V31.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q1, [X6, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4372c0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	ideal_gas.cpp:40-45
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 256 bits (SSE/AVX-128 instructions on AVX/AVX2 processors).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 58.05 to 8.00 cycles (7.26x speedup).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

48: multiply
8: divide
8: square root

The binary loop does not load or store any data.

General properties

nb instructions	58
nb uops	58
loop length	232
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	16
used v registers	21
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	10.00	10.00	10.00	10.00	6.67	6.67	6.67	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	10.00	10.00	10.00	10.00	6.67	6.67	6.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-58.05
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.25
Dispatch	10.00
DIV/SQRT	27.97-58.05
Data deps.	1.00
Overall L1	27.97-58.05

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	50%
load	50%
store	50%
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 58.05 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4372c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR Q20, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X17, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X0, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q21, [X8, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V22.2D, V27.2D, V20.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V30.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V23.2D, V22.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V0.2D, V30.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q0, [X7, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q31, [X1, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V1.2D, V31.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V2.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V3.2D, V2.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V4.2D, V3.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q4, [X6, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q5, [X1, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q6, [X8, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V7.2D, V27.2D, V5.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V16.2D, V6.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V17.2D, V7.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V18.2D, V16.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q18, [X7, X17]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q19, [X1, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V20.2D, V19.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V20.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V22.2D, V21.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V30.2D, V22.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q30, [X6, X17]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q23, [X1, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q0, [X8, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V31.2D, V27.2D, V23.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V1.2D, V0.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V2.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V3.2D, V1.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q3, [X7, X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q4, [X1, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V5.2D, V4.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V5.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V7.2D, V6.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V16.2D, V7.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q16, [X6, X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q17, [X1, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q18, [X8, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FDIV V19.2D, V27.2D, V17.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMUL V20.2D, V18.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V19.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V22.2D, V20.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q22, [X7, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q30, [X1, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V23.2D, V30.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V0.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V31.2D, V0.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FSQRT V1.2D, V31.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
STR Q1, [X6, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4372c0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code