OV - exec - Function generate_chunk(int, global_variables&) [clone ._omp

	Function: generate_chunk(int, global_variables&) [clone ._omp_fn.1]	Module: exec	Source: generate_chunk.cpp:85-123 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

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46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 85 - 123

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

[...]

105:               std::sqrt((field.cellx[i] - x_cent) * (field.cellx[i] - x_cent) + (field.celly[j] - y_cent) * (field.celly[j] - y_cent));

106:           if (radius <= state_radius[state]) {

107:             field.energy0(i, j) = state_energy[state];

108:             field.density0(i, j) = state_density[state];

109:             for (int kt = j; kt <= j + 1; ++kt) {

110:               for (int jt = i; jt <= i + 1; ++jt) {

111:                 field.xvel0(jt, kt) = state_xvel[state];

112:                 field.yvel0(jt, kt) = state_yvel[state];

113:               }

114:             }

115:           }

116:         } else if (state_geometry[state] == g_point) {

117:           if (field.vertexx[i] == x_cent && field.vertexy[j] == y_cent) {

118:             field.energy0(i, j) = state_energy[state];

119:             field.density0(i, j) = state_density[state];

120:             for (int kt = j; kt <= j + 1; ++kt) {

121:               for (int jt = i; jt <= i + 1; ++jt) {

122:                 field.xvel0(jt, kt) = state_xvel[state];

123:                 field.yvel0(jt, kt) = state_yvel[state];

0x436180 STP	X29, X30, [SP, #896]!

0x436184 ADD	X29, SP, #0

0x436188 STP	X19, X20, [SP, #16]

0x43618c STP	X21, X22, [SP, #32]

0x436190 LDP	W20, W21, [X0, #88]

0x436194 CMP	W21, #0

0x436198 B.LE	436284

0x43619c CMP	W20, #0

0x4361a0 B.LE	436284

0x4361a4 ORR	X19, XZR, X0

0x4361a8 STP	X23, X24, [SP, #48]

0x4361ac MUL	W23, W21, W20

0x4361b0 BL	410210

0x4361b4 ORR	W22, WZR, W0

0x4361b8 BL	410240

0x4361bc UDIV	W2, W23, W22

0x4361c0 MSUB	W1, W2, W22, W23

0x4361c4 CMP	W0, W1

0x4361c8 B.CC	436644

0x4361cc MADD	W8, W2, W0, W1

0x4361d0 ADD	W13, W2, W8

0x4361d4 CMP	W8, W13

0x4361d8 B.CS	436294

0x4361dc UDIV	W3, W8, W20

0x4361e0 STP	X25, X26, [SP, #64]

0x4361e4 STP	X27, X28, [SP, #80]

0x4361e8 LDRSW	X4, [X19, #96]

0x4361ec LDP	X15, X16, [X19, #32]

0x4361f0 MSUB	W22, W3, W20, W8

0x4361f4 LDP	X26, X14, [X19, #64]

0x4361f8 SBFM	X3, X3, #0, #31

0x4361fc UBFM	X5, X4, #61, #60

0x436200 UBFM	X28, X4, #62, #61

0x436204 SUB	W7, W20, W22

0x436208 LDR	X27, [X19, #48]

0x43620c LDR	X9, [X19, #80]

(240) 0x436210 CMP	W2, W7

(240) 0x436214 CSEL	W12, W2, W7, #9

(240) 0x436218 ADD	W7, W8, W12

(240) 0x43621c CMP	W8, W7

(240) 0x436220 B.CS	43625c

(240) 0x436224 LDR	X0, [X14, #8]

(240) 0x436228 UBFM	X11, X3, #61, #60

(240) 0x43622c LDR	X17, [X15, #8]

(240) 0x436230 LDR	X18, [X27, #8]

(240) 0x436234 LDR	W6, [X0, X28]

(240) 0x436238 ADD	X2, X17, X5

(240) 0x43623c ADD	X8, X18, X5

(240) 0x436240 CMP	W6, #1

(240) 0x436244 B.EQ	436348

(240) 0x436248 CMP	W6, #2

(240) 0x43624c B.EQ	436570

(240) 0x436250 CMP	W6, #3

(240) 0x436254 B.EQ	4362a8

(240) 0x436258 ORR	W8, WZR, W7

(240) 0x43625c ADD	X3, X3, #1

(240) 0x436260 CMP	W21, W3

(240) 0x436264 B.LE	436278

(240) 0x436268 SUB	W2, W13, W8

(240) 0x43626c ORR	W7, WZR, W20

(240) 0x436270 MOVZ	W22, #0

(240) 0x436274 B	436210

0x436278 LDP	X23, X24, [SP, #48]

0x43627c LDP	X25, X26, [SP, #64]

0x436280 LDP	X27, X28, [SP, #80]

0x436284 LDP	X19, X20, [SP, #16]

0x436288 LDP	X21, X22, [SP, #32]

0x43628c LDP	X29, X30, [SP], #128

0x436290 RET

0x436294 LDP	X23, X24, [SP, #48]

0x436298 LDP	X19, X20, [SP, #16]

0x43629c LDP	X21, X22, [SP, #32]

0x4362a0 LDP	X29, X30, [SP], #128

0x4362a4 RET

(240) 0x4362a8 SBFM	X0, X22, #0, #31

(240) 0x4362ac SUB	W12, W12, #1

(240) 0x4362b0 LDR	X4, [X9, #600]

(240) 0x4362b4 ADD	X1, X0, #1

(240) 0x4362b8 ADD	X6, X1, X12

(240) 0x4362bc TBZ	W12, #0, 4362ec

(240) 0x4362c0 LDR	D22, [X4, W0,UXTW #3]

(240) 0x4362c4 LDR	D23, [X17, X5]

(240) 0x4362c8 FCMP	D22, D23

(240) 0x4362cc B.NE	4362e4

(240) 0x4362d0 LDR	X10, [X9, #632]

(240) 0x4362d4 LDR	D21, [X18, X5]

(240) 0x4362d8 LDR	D20, [X10, X11]

(240) 0x4362dc FCMP	D20, D21

(240) 0x4362e0 B.EQ	436b5c

(240) 0x4362e4 ORR	X0, XZR, X1

(240) 0x4362e8 ADD	X1, X1, #1

  (243) 0x4362ec LDR	D0, [X4, W0,UXTW #3]

  (243) 0x4362f0 LDR	D1, [X2]

  (243) 0x4362f4 FCMP	D0, D1

  (243) 0x4362f8 B.NE	436310

  (243) 0x4362fc LDR	X22, [X9, #632]

  (243) 0x436300 LDR	D3, [X8]

  (243) 0x436304 LDR	D2, [X22, X11]

  (243) 0x436308 FCMP	D2, D3

  (243) 0x43630c B.EQ	4368dc

  (243) 0x436310 CMP	X1, X6

  (243) 0x436314 B.EQ	436258

  (243) 0x436318 LDR	D19, [X4, W1,UXTW #3]

  (243) 0x43631c ADD	X0, X1, #1

  (243) 0x436320 LDR	D18, [X2]

  (243) 0x436324 FCMP	D19, D18

  (243) 0x436328 B.NE	436340

  (243) 0x43632c LDR	X22, [X9, #632]

  (243) 0x436330 LDR	D31, [X8]

  (243) 0x436334 LDR	D30, [X22, X11]

  (243) 0x436338 FCMP	D30, D31

  (243) 0x43633c B.EQ	4369a8

  (243) 0x436340 ADD	X1, X0, #1

  (243) 0x436344 B	4362ec

(240) 0x436348 SBFM	X10, X22, #0, #31

(240) 0x43634c SUB	W24, W12, #1

(240) 0x436350 LDR	X6, [X9, #600]

(240) 0x436354 ADD	X4, X10, #1

(240) 0x436358 UBFM	X0, X22, #61, #31

(240) 0x43635c ADD	X12, X4, X24

(240) 0x436360 TBZ	W24, #0, 4363cc

(240) 0x436364 ORR	X25, XZR, X0

(240) 0x436368 ADD	X0, X0, #8

(240) 0x43636c LDR	D31, [X17, X5]

(240) 0x436370 ORR	X1, XZR, X10

(240) 0x436374 ORR	X10, XZR, X4

(240) 0x436378 LDR	D30, [X6, X0]

(240) 0x43637c FCMPE	D31, D30

(240) 0x436380 B.GT	4363c8

(240) 0x436384 LDR	X30, [X16, #8]

(240) 0x436388 LDR	D29, [X6, X25]

(240) 0x43638c LDR	D28, [X30, X5]

(240) 0x436390 FCMPE	D29, D28

(240) 0x436394 B.GE	4363c8

(240) 0x436398 LDR	X22, [X9, #632]

(240) 0x43639c LDR	D27, [X18, X5]

(240) 0x4363a0 ADD	X23, X22, X11

(240) 0x4363a4 LDR	D26, [X23, #8]

(240) 0x4363a8 FCMPE	D27, D26

(240) 0x4363ac B.GT	4363c8

(240) 0x4363b0 LDR	X17, [X19, #56]

(240) 0x4363b4 LDR	D25, [X22, X11]

(240) 0x4363b8 LDR	X18, [X17, #8]

(240) 0x4363bc LDR	D24, [X18, X5]

(240) 0x4363c0 FCMPE	D25, D24

(240) 0x4363c4 B.MI	436a78

(240) 0x4363c8 ADD	X4, X4, #1

  (241) 0x4363cc ADD	X1, X0, #8

  (241) 0x4363d0 LDR	D23, [X2]

  (241) 0x4363d4 LDR	D22, [X6, X1]

  (241) 0x4363d8 FCMPE	D23, D22

  (241) 0x4363dc B.GT	436424

  (241) 0x4363e0 LDR	D21, [X6, X0]

  (241) 0x4363e4 LDR	X0, [X16, #8]

  (241) 0x4363e8 LDR	D20, [X0, X5]

  (241) 0x4363ec FCMPE	D21, D20

  (241) 0x4363f0 B.GE	436424

  (241) 0x4363f4 LDR	X23, [X9, #632]

  (241) 0x4363f8 LDR	D19, [X8]

  (241) 0x4363fc ADD	X22, X23, X11

  (241) 0x436400 LDR	D18, [X22, #8]

  (241) 0x436404 FCMPE	D19, D18

  (241) 0x436408 B.GT	436424

  (241) 0x43640c LDR	X18, [X19, #56]

  (241) 0x436410 LDR	D31, [X23, X11]

  (241) 0x436414 LDR	X17, [X18, #8]

  (241) 0x436418 LDR	D30, [X17, X5]

  (241) 0x43641c FCMPE	D31, D30

  (241) 0x436420 B.MI	436804

  (241) 0x436424 CMP	X4, X12

  (241) 0x436428 B.EQ	436258

  (241) 0x43642c ADD	X0, X1, #8

  (241) 0x436430 LDR	D5, [X2]

  (241) 0x436434 ADD	X17, X4, #1

  (241) 0x436438 ORR	X10, XZR, X17

  (241) 0x43643c LDR	D4, [X6, X0]

  (241) 0x436440 FCMPE	D5, D4

  (241) 0x436444 B.GT	436568

  (241) 0x436448 LDR	D6, [X6, X1]

  (241) 0x43644c LDR	X1, [X16, #8]

  (241) 0x436450 LDR	D7, [X1, X5]

  (241) 0x436454 FCMPE	D6, D7

  (241) 0x436458 B.GE	436568

  (241) 0x43645c LDR	X23, [X9, #632]

  (241) 0x436460 LDR	D16, [X8]

  (241) 0x436464 ADD	X22, X23, X11

  (241) 0x436468 LDR	D17, [X22, #8]

  (241) 0x43646c FCMPE	D16, D17

  (241) 0x436470 B.GT	436568

  (241) 0x436474 LDR	X18, [X19, #56]

  (241) 0x436478 LDR	D22, [X23, X11]

  (241) 0x43647c LDR	X25, [X18, #8]

  (241) 0x436480 LDR	D23, [X25, X5]

  (241) 0x436484 FCMPE	D22, D23

  (241) 0x436488 B.GE	436568

  (241) 0x43648c LDP	X23, X22, [X19]

  (241) 0x436490 LDR	X1, [X9, #48]

  (241) 0x436494 LDR	X25, [X22, #8]

  (241) 0x436498 LDR	X24, [X9, #64]

  (241) 0x43649c MADD	X18, X3, X1, X4

  (241) 0x4364a0 LDR	X23, [X23, #8]

  (241) 0x4364a4 LDR	D21, [X25, X5]

  (241) 0x4364a8 LDR	X1, [X9]

  (241) 0x4364ac LDR	X30, [X9, #168]

  (241) 0x4364b0 STR	D21, [X24, X18,LSL #3]

  (241) 0x4364b4 LDP	X24, X18, [X19, #16]

  (241) 0x4364b8 MADD	X25, X3, X1, X4

  (241) 0x4364bc LDR	D20, [X23, X5]

  (241) 0x4364c0 LDR	X22, [X9, #16]

  (241) 0x4364c4 LDR	X24, [X24, #8]

  (241) 0x4364c8 LDR	X1, [X9, #216]

  (241) 0x4364cc LDR	X23, [X9, #184]

  (241) 0x4364d0 STR	D20, [X22, X25,LSL #3]

  (241) 0x4364d4 LDR	X22, [X18, #8]

  (241) 0x4364d8 MUL	X18, X30, X3

  (241) 0x4364dc STR	X1, [SP, #96]

  (241) 0x4364e0 LDR	D19, [X24, X5]

  (241) 0x4364e4 ADD	X1, X18, X17

  (241) 0x4364e8 ADD	X25, X18, X4

  (241) 0x4364ec ADD	X30, X30, X18

  (241) 0x4364f0 LDR	X18, [X9, #232]

  (241) 0x4364f4 STR	X1, [SP, #104]

  (241) 0x4364f8 LDR	X1, [SP, #96]

  (241) 0x4364fc STR	D19, [X23, X25,LSL #3]

  (241) 0x436500 ADD	X25, X30, X4

  (241) 0x436504 ADD	X30, X30, X17

  (241) 0x436508 LDR	D18, [X22, X5]

  (241) 0x43650c STP	X25, X30, [SP, #112]

  (241) 0x436510 MUL	X25, X1, X3

  (241) 0x436514 ADD	X30, X25, X4

  (241) 0x436518 ADD	X1, X1, X25

  (241) 0x43651c ADD	X25, X25, X17

  (241) 0x436520 ADD	X4, X1, X4

  (241) 0x436524 STR	D18, [X18, X30,LSL #3]

  (241) 0x436528 ADD	X1, X1, X17

  (241) 0x43652c LDR	D31, [X24, X5]

  (241) 0x436530 LDR	X30, [SP, #104]

  (241) 0x436534 STR	D31, [X23, X30,LSL #3]

  (241) 0x436538 LDR	D30, [X22, X5]

  (241) 0x43653c STR	D30, [X18, X25,LSL #3]

  (241) 0x436540 LDR	D29, [X24, X5]

  (241) 0x436544 LDR	X25, [SP, #112]

  (241) 0x436548 STR	D29, [X23, X25,LSL #3]

  (241) 0x43654c LDR	D28, [X22, X5]

  (241) 0x436550 STR	D28, [X18, X4,LSL #3]

  (241) 0x436554 LDR	D27, [X24, X5]

  (241) 0x436558 LDR	X24, [SP, #120]

  (241) 0x43655c STR	D27, [X23, X24,LSL #3]

  (241) 0x436560 LDR	D26, [X22, X5]

  (241) 0x436564 STR	D26, [X18, X1,LSL #3]

  (241) 0x436568 ADD	X4, X17, #1

  (241) 0x43656c B	4363cc

(240) 0x436570 LDR	X23, [X26, #8]

(240) 0x436574 SBFM	X0, X22, #0, #31

(240) 0x436578 SUB	W22, W12, #1

(240) 0x43657c ADD	X1, X0, #1

(240) 0x436580 LDR	X30, [X9, #568]

(240) 0x436584 ADD	X12, X1, X22

(240) 0x436588 LDR	X4, [X9, #536]

(240) 0x43658c ADD	X6, X23, X5

(240) 0x436590 ADD	X10, X30, X11

(240) 0x436594 TBZ	W22, #0, 4365d0

(240) 0x436598 LDR	D25, [X30, X11]

(240) 0x43659c LDR	D24, [X18, X5]

(240) 0x4365a0 LDR	D0, [X4, W0,UXTW #3]

(240) 0x4365a4 LDR	D1, [X17, X5]

(240) 0x4365a8 FSUB	D2, D25, S24

(240) 0x4365ac LDR	D3, [X23, X5]

(240) 0x4365b0 FSUB	D4, D0, S1

(240) 0x4365b4 FMUL	D5, D2, D2

(240) 0x4365b8 FMADD	D6, D4, D4, D5

(240) 0x4365bc FSQRT	D7, D6

(240) 0x4365c0 FCMPE	D7, D3

(240) 0x4365c4 B.LS	436c28

(240) 0x4365c8 ORR	X0, XZR, X1

(240) 0x4365cc ADD	X1, X1, #1

  (242) 0x4365d0 LDR	D27, [X8]

  (242) 0x4365d4 LDR	D24, [X10]

  (242) 0x4365d8 LDR	D29, [X4, W0,UXTW #3]

  (242) 0x4365dc LDR	D28, [X2]

  (242) 0x4365e0 FSUB	D0, D24, S27

  (242) 0x4365e4 LDR	D25, [X6]

  (242) 0x4365e8 FSUB	D26, D29, S28

  (242) 0x4365ec FMUL	D1, D0, D0

  (242) 0x4365f0 FMADD	D2, D26, D26, D1

  (242) 0x4365f4 FSQRT	D3, D2

  (242) 0x4365f8 FCMPE	D3, D25

  (242) 0x4365fc B.LS	436650

  (242) 0x436600 CMP	X12, X1

  (242) 0x436604 B.EQ	436258

  (242) 0x436608 LDR	D29, [X8]

  (242) 0x43660c ADD	X0, X1, #1

  (242) 0x436610 LDR	D28, [X10]

  (242) 0x436614 LDR	D19, [X4, W1,UXTW #3]

  (242) 0x436618 LDR	D18, [X2]

  (242) 0x43661c FSUB	D26, D28, S29

  (242) 0x436620 LDR	D30, [X6]

  (242) 0x436624 FSUB	D31, D19, S18

  (242) 0x436628 FMUL	D25, D26, D26

  (242) 0x43662c FMADD	D27, D31, D31, D25

  (242) 0x436630 FSQRT	D24, D27

  (242) 0x436634 FCMPE	D24, D30

  (242) 0x436638 B.LS	436728

  (242) 0x43663c ADD	X1, X0, #1

  (242) 0x436640 B	4365d0

0x436644 ADD	W2, W2, #1

0x436648 MOVZ	W1, #0

0x43664c B	4361cc

  (242) 0x436650 LDP	X18, X17, [X19]

  (242) 0x436654 LDR	X22, [X9, #48]

  (242) 0x436658 LDR	X11, [X17, #8]

  (242) 0x43665c LDR	X23, [X9, #64]

  (242) 0x436660 MADD	X25, X3, X22, X0

  (242) 0x436664 LDR	X24, [X18, #8]

  (242) 0x436668 LDR	D4, [X11, X5]

  (242) 0x43666c LDR	X30, [X9]

  (242) 0x436670 LDR	X22, [X9, #16]

  (242) 0x436674 STR	D4, [X23, X25,LSL #3]

  (242) 0x436678 LDR	X25, [X19, #16]

  (242) 0x43667c MADD	X11, X3, X30, X0

  (242) 0x436680 LDR	D5, [X24, X5]

  (242) 0x436684 LDR	X18, [X19, #24]

  (242) 0x436688 LDR	X24, [X25, #8]

  (242) 0x43668c LDR	X17, [X9, #168]

  (242) 0x436690 LDR	X23, [X9, #184]

  (242) 0x436694 STR	D5, [X22, X11,LSL #3]

  (242) 0x436698 LDR	D6, [X24, X5]

  (242) 0x43669c LDR	X22, [X18, #8]

  (242) 0x4366a0 MUL	X18, X17, X3

  (242) 0x4366a4 LDR	X11, [X9, #216]

  (242) 0x4366a8 ADD	X30, X18, X0

  (242) 0x4366ac ADD	X25, X18, X1

  (242) 0x4366b0 ADD	X17, X17, X18

  (242) 0x4366b4 LDR	X18, [X9, #232]

  (242) 0x4366b8 STR	D6, [X23, X30,LSL #3]

  (242) 0x4366bc ADD	X30, X17, X1

  (242) 0x4366c0 LDR	D7, [X22, X5]

  (242) 0x4366c4 STR	X25, [SP, #96]

  (242) 0x4366c8 ADD	X25, X17, X0

  (242) 0x4366cc MUL	X17, X11, X3

  (242) 0x4366d0 STR	X30, [SP, #104]

  (242) 0x4366d4 ADD	X30, X17, X0

  (242) 0x4366d8 ADD	X11, X11, X17

  (242) 0x4366dc ADD	X17, X17, X1

  (242) 0x4366e0 ADD	X0, X11, X0

  (242) 0x4366e4 STR	D7, [X18, X30,LSL #3]

  (242) 0x4366e8 ADD	X11, X11, X1

  (242) 0x4366ec LDR	D16, [X24, X5]

  (242) 0x4366f0 LDR	X30, [SP, #96]

  (242) 0x4366f4 STR	D16, [X23, X30,LSL #3]

  (242) 0x4366f8 LDR	D17, [X22, X5]

  (242) 0x4366fc STR	D17, [X18, X17,LSL #3]

  (242) 0x436700 LDR	D22, [X24, X5]

  (242) 0x436704 STR	D22, [X23, X25,LSL #3]

  (242) 0x436708 LDR	D23, [X22, X5]

  (242) 0x43670c STR	D23, [X18, X0,LSL #3]

  (242) 0x436710 LDR	D21, [X24, X5]

  (242) 0x436714 LDR	X24, [SP, #104]

  (242) 0x436718 STR	D21, [X23, X24,LSL #3]

  (242) 0x43671c LDR	D20, [X22, X5]

  (242) 0x436720 STR	D20, [X18, X11,LSL #3]

  (242) 0x436724 B	436600

  (242) 0x436728 LDP	X18, X17, [X19]

  (242) 0x43672c LDR	X22, [X9, #48]

  (242) 0x436730 LDR	X11, [X17, #8]

  (242) 0x436734 LDR	X23, [X9, #64]

  (242) 0x436738 MADD	X25, X3, X22, X1

  (242) 0x43673c LDR	X24, [X18, #8]

  (242) 0x436740 LDR	D0, [X11, X5]

  (242) 0x436744 LDR	X30, [X9]

  (242) 0x436748 LDR	X22, [X9, #16]

  (242) 0x43674c STR	D0, [X23, X25,LSL #3]

  (242) 0x436750 LDR	X25, [X19, #16]

  (242) 0x436754 MADD	X11, X3, X30, X1

  (242) 0x436758 LDR	D1, [X24, X5]

  (242) 0x43675c LDR	X18, [X19, #24]

  (242) 0x436760 LDR	X24, [X25, #8]

  (242) 0x436764 LDR	X17, [X9, #168]

  (242) 0x436768 LDR	X23, [X9, #184]

  (242) 0x43676c STR	D1, [X22, X11,LSL #3]

  (242) 0x436770 LDR	D2, [X24, X5]

  (242) 0x436774 LDR	X22, [X18, #8]

  (242) 0x436778 MUL	X18, X17, X3

  (242) 0x43677c LDR	X11, [X9, #216]

  (242) 0x436780 ADD	X30, X18, X1

  (242) 0x436784 ADD	X25, X18, X0

  (242) 0x436788 ADD	X17, X17, X18

  (242) 0x43678c LDR	X18, [X9, #232]

  (242) 0x436790 STR	D2, [X23, X30,LSL #3]

  (242) 0x436794 ADD	X30, X17, X0

  (242) 0x436798 LDR	D3, [X22, X5]

  (242) 0x43679c STR	X25, [SP, #96]

  (242) 0x4367a0 ADD	X25, X17, X1

  (242) 0x4367a4 MUL	X17, X11, X3

  (242) 0x4367a8 STR	X30, [SP, #104]

  (242) 0x4367ac ADD	X30, X17, X1

  (242) 0x4367b0 ADD	X11, X11, X17

  (242) 0x4367b4 ADD	X17, X17, X0

  (242) 0x4367b8 ADD	X1, X11, X1

  (242) 0x4367bc STR	D3, [X18, X30,LSL #3]

  (242) 0x4367c0 ADD	X11, X11, X0

  (242) 0x4367c4 LDR	D4, [X24, X5]

  (242) 0x4367c8 LDR	X30, [SP, #96]

  (242) 0x4367cc STR	D4, [X23, X30,LSL #3]

  (242) 0x4367d0 LDR	D5, [X22, X5]

  (242) 0x4367d4 STR	D5, [X18, X17,LSL #3]

  (242) 0x4367d8 LDR	D6, [X24, X5]

  (242) 0x4367dc STR	D6, [X23, X25,LSL #3]

  (242) 0x4367e0 LDR	D7, [X22, X5]

  (242) 0x4367e4 STR	D7, [X18, X1,LSL #3]

  (242) 0x4367e8 ADD	X1, X0, #1

  (242) 0x4367ec LDR	D16, [X24, X5]

  (242) 0x4367f0 LDR	X24, [SP, #104]

  (242) 0x4367f4 STR	D16, [X23, X24,LSL #3]

  (242) 0x4367f8 LDR	D17, [X22, X5]

  (242) 0x4367fc STR	D17, [X18, X11,LSL #3]

  (242) 0x436800 B	4365d0

  (241) 0x436804 LDP	X23, X0, [X19]

  (241) 0x436808 LDR	X30, [X9, #48]

  (241) 0x43680c LDR	X22, [X0, #8]

  (241) 0x436810 LDR	X25, [X9, #64]

  (241) 0x436814 MADD	X24, X3, X30, X10

  (241) 0x436818 LDR	X17, [X23, #8]

  (241) 0x43681c LDR	D29, [X22, X5]

  (241) 0x436820 LDR	X18, [X9]

  (241) 0x436824 LDR	X22, [X19, #24]

  (241) 0x436828 STR	D29, [X25, X24,LSL #3]

  (241) 0x43682c LDR	X24, [X19, #16]

  (241) 0x436830 MADD	X30, X3, X18, X10

  (241) 0x436834 LDR	D28, [X17, X5]

  (241) 0x436838 LDR	X25, [X9, #16]

  (241) 0x43683c LDR	X24, [X24, #8]

  (241) 0x436840 LDR	X17, [X9, #168]

  (241) 0x436844 LDR	X23, [X9, #184]

  (241) 0x436848 STR	D28, [X25, X30,LSL #3]

  (241) 0x43684c LDR	D27, [X24, X5]

  (241) 0x436850 MUL	X18, X17, X3

  (241) 0x436854 LDR	X22, [X22, #8]

  (241) 0x436858 LDR	X0, [X9, #216]

  (241) 0x43685c ADD	X30, X18, X10

  (241) 0x436860 ADD	X25, X18, X4

  (241) 0x436864 ADD	X17, X17, X18

  (241) 0x436868 LDR	X18, [X9, #232]

  (241) 0x43686c STR	D27, [X23, X30,LSL #3]

  (241) 0x436870 ADD	X30, X17, X4

  (241) 0x436874 LDR	D26, [X22, X5]

  (241) 0x436878 STR	X25, [SP, #96]

  (241) 0x43687c ADD	X25, X17, X10

  (241) 0x436880 MUL	X17, X0, X3

  (241) 0x436884 STR	X30, [SP, #104]

  (241) 0x436888 ADD	X30, X17, X10

  (241) 0x43688c ADD	X0, X0, X17

  (241) 0x436890 ADD	X17, X17, X4

  (241) 0x436894 ADD	X10, X0, X10

  (241) 0x436898 STR	D26, [X18, X30,LSL #3]

  (241) 0x43689c ADD	X0, X0, X4

  (241) 0x4368a0 LDR	D25, [X24, X5]

  (241) 0x4368a4 LDR	X30, [SP, #96]

  (241) 0x4368a8 STR	D25, [X23, X30,LSL #3]

  (241) 0x4368ac LDR	D24, [X22, X5]

  (241) 0x4368b0 STR	D24, [X18, X17,LSL #3]

  (241) 0x4368b4 LDR	D0, [X24, X5]

  (241) 0x4368b8 STR	D0, [X23, X25,LSL #3]

  (241) 0x4368bc LDR	D1, [X22, X5]

  (241) 0x4368c0 STR	D1, [X18, X10,LSL #3]

  (241) 0x4368c4 LDR	D2, [X24, X5]

  (241) 0x4368c8 LDR	X24, [SP, #104]

  (241) 0x4368cc STR	D2, [X23, X24,LSL #3]

  (241) 0x4368d0 LDR	D3, [X22, X5]

  (241) 0x4368d4 STR	D3, [X18, X0,LSL #3]

  (241) 0x4368d8 B	436424

  (243) 0x4368dc LDP	X17, X12, [X19]

  (243) 0x4368e0 LDR	X18, [X9, #48]

  (243) 0x4368e4 LDR	X10, [X12, #8]

  (243) 0x4368e8 LDR	X23, [X9, #64]

  (243) 0x4368ec MADD	X24, X3, X18, X0

  (243) 0x4368f0 LDR	X22, [X17, #8]

  (243) 0x4368f4 LDR	D4, [X10, X5]

  (243) 0x4368f8 LDR	X25, [X9]

  (243) 0x4368fc LDR	X30, [X9, #168]

  (243) 0x436900 STR	D4, [X23, X24,LSL #3]

  (243) 0x436904 LDP	X23, X18, [X19, #16]

  (243) 0x436908 MADD	X10, X3, X25, X0

  (243) 0x43690c MUL	X17, X30, X3

  (243) 0x436910 LDR	D5, [X22, X5]

  (243) 0x436914 ADD	X12, X17, X0

  (243) 0x436918 ADD	X25, X17, X1

  (243) 0x43691c LDR	X23, [X23, #8]

  (243) 0x436920 ADD	X30, X30, X17

  (243) 0x436924 LDR	X24, [X9, #16]

  (243) 0x436928 LDR	X18, [X18, #8]

  (243) 0x43692c LDR	X22, [X9, #184]

  (243) 0x436930 STR	D5, [X24, X10,LSL #3]

  (243) 0x436934 ADD	X24, X30, X0

  (243) 0x436938 ADD	X30, X30, X1

  (243) 0x43693c LDR	D6, [X23, X5]

  (243) 0x436940 STR	X24, [SP, #96]

  (243) 0x436944 LDR	X10, [X9, #216]

  (243) 0x436948 LDR	X17, [X9, #232]

  (243) 0x43694c STR	D6, [X22, X12,LSL #3]

  (243) 0x436950 LDR	D7, [X18, X5]

  (243) 0x436954 MUL	X12, X10, X3

  (243) 0x436958 ADD	X24, X12, X0

  (243) 0x43695c ADD	X10, X10, X12

  (243) 0x436960 ADD	X12, X12, X1

  (243) 0x436964 ADD	X0, X10, X0

  (243) 0x436968 ADD	X10, X10, X1

  (243) 0x43696c STR	D7, [X17, X24,LSL #3]

  (243) 0x436970 LDR	D16, [X23, X5]

  (243) 0x436974 STR	D16, [X22, X25,LSL #3]

  (243) 0x436978 LDR	D17, [X18, X5]

  (243) 0x43697c LDR	X25, [SP, #96]

  (243) 0x436980 STR	D17, [X17, X12,LSL #3]

  (243) 0x436984 LDR	D22, [X23, X5]

  (243) 0x436988 STR	D22, [X22, X25,LSL #3]

  (243) 0x43698c LDR	D23, [X18, X5]

  (243) 0x436990 STR	D23, [X17, X0,LSL #3]

  (243) 0x436994 LDR	D21, [X23, X5]

  (243) 0x436998 STR	D21, [X22, X30,LSL #3]

  (243) 0x43699c LDR	D20, [X18, X5]

  (243) 0x4369a0 STR	D20, [X17, X10,LSL #3]

  (243) 0x4369a4 B	436310

  (243) 0x4369a8 LDP	X17, X12, [X19]

  (243) 0x4369ac LDR	X18, [X9, #48]

  (243) 0x4369b0 LDR	X10, [X12, #8]

  (243) 0x4369b4 LDR	X23, [X9, #64]

  (243) 0x4369b8 MADD	X24, X3, X18, X1

  (243) 0x4369bc LDR	X22, [X17, #8]

  (243) 0x4369c0 LDR	D29, [X10, X5]

  (243) 0x4369c4 LDR	X25, [X9]

  (243) 0x4369c8 LDR	X30, [X9, #168]

  (243) 0x4369cc STR	D29, [X23, X24,LSL #3]

  (243) 0x4369d0 LDP	X23, X18, [X19, #16]

  (243) 0x4369d4 MADD	X10, X3, X25, X1

  (243) 0x4369d8 MUL	X17, X30, X3

  (243) 0x4369dc LDR	D28, [X22, X5]

  (243) 0x4369e0 ADD	X12, X17, X1

  (243) 0x4369e4 ADD	X25, X17, X0

  (243) 0x4369e8 LDR	X23, [X23, #8]

  (243) 0x4369ec ADD	X30, X30, X17

  (243) 0x4369f0 LDR	X24, [X9, #16]

  (243) 0x4369f4 LDR	X18, [X18, #8]

  (243) 0x4369f8 LDR	X22, [X9, #184]

  (243) 0x4369fc STR	D28, [X24, X10,LSL #3]

  (243) 0x436a00 ADD	X24, X30, X1

  (243) 0x436a04 ADD	X30, X30, X0

  (243) 0x436a08 LDR	D26, [X23, X5]

  (243) 0x436a0c STR	X24, [SP, #96]

  (243) 0x436a10 LDR	X10, [X9, #216]

  (243) 0x436a14 LDR	X17, [X9, #232]

  (243) 0x436a18 STR	D26, [X22, X12,LSL #3]

  (243) 0x436a1c LDR	D25, [X18, X5]

  (243) 0x436a20 MUL	X12, X10, X3

  (243) 0x436a24 ADD	X24, X12, X1

  (243) 0x436a28 ADD	X10, X10, X12

  (243) 0x436a2c ADD	X12, X12, X0

  (243) 0x436a30 ADD	X1, X10, X1

  (243) 0x436a34 ADD	X10, X10, X0

  (243) 0x436a38 STR	D25, [X17, X24,LSL #3]

  (243) 0x436a3c LDR	D27, [X23, X5]

  (243) 0x436a40 STR	D27, [X22, X25,LSL #3]

  (243) 0x436a44 LDR	D24, [X18, X5]

  (243) 0x436a48 LDR	X25, [SP, #96]

  (243) 0x436a4c STR	D24, [X17, X12,LSL #3]

  (243) 0x436a50 LDR	D0, [X23, X5]

  (243) 0x436a54 STR	D0, [X22, X25,LSL #3]

  (243) 0x436a58 LDR	D1, [X18, X5]

  (243) 0x436a5c STR	D1, [X17, X1,LSL #3]

  (243) 0x436a60 ADD	X1, X0, #1

  (243) 0x436a64 LDR	D3, [X23, X5]

  (243) 0x436a68 STR	D3, [X22, X30,LSL #3]

  (243) 0x436a6c LDR	D2, [X18, X5]

  (243) 0x436a70 STR	D2, [X17, X10,LSL #3]

  (243) 0x436a74 B	4362ec

(240) 0x436a78 LDP	X22, X23, [X19]

(240) 0x436a7c LDR	X25, [X9, #48]

(240) 0x436a80 LDR	X17, [X23, #8]

(240) 0x436a84 LDR	X22, [X22, #8]

(240) 0x436a88 MADD	X18, X3, X25, X1

(240) 0x436a8c LDR	X24, [X9, #64]

(240) 0x436a90 LDR	D0, [X17, X5]

(240) 0x436a94 LDR	X25, [X9]

(240) 0x436a98 LDR	X30, [X9, #168]

(240) 0x436a9c STR	D0, [X24, X18,LSL #3]

(240) 0x436aa0 LDR	D1, [X22, X5]

(240) 0x436aa4 MADD	X17, X3, X25, X1

(240) 0x436aa8 LDP	X24, X18, [X19, #16]

(240) 0x436aac LDR	X25, [X9, #16]

(240) 0x436ab0 LDR	X24, [X24, #8]

(240) 0x436ab4 LDR	X23, [X9, #184]

(240) 0x436ab8 STR	D1, [X25, X17,LSL #3]

(240) 0x436abc LDR	X17, [X9, #216]

(240) 0x436ac0 LDR	X22, [X18, #8]

(240) 0x436ac4 MUL	X18, X30, X3

(240) 0x436ac8 LDR	D2, [X24, X5]

(240) 0x436acc STR	X17, [SP, #96]

(240) 0x436ad0 ADD	X17, X18, X4

(240) 0x436ad4 ADD	X25, X18, X1

(240) 0x436ad8 ADD	X30, X30, X18

(240) 0x436adc LDR	X18, [X9, #232]

(240) 0x436ae0 STR	X17, [SP, #104]

(240) 0x436ae4 LDR	X17, [SP, #96]

(240) 0x436ae8 STR	D2, [X23, X25,LSL #3]

(240) 0x436aec ADD	X25, X30, X1

(240) 0x436af0 ADD	X30, X30, X4

(240) 0x436af4 LDR	D3, [X22, X5]

(240) 0x436af8 STP	X25, X30, [SP, #112]

(240) 0x436afc MUL	X25, X17, X3

(240) 0x436b00 ADD	X30, X25, X1

(240) 0x436b04 ADD	X17, X17, X25

(240) 0x436b08 ADD	X25, X25, X4

(240) 0x436b0c ADD	X1, X17, X1

(240) 0x436b10 STR	D3, [X18, X30,LSL #3]

(240) 0x436b14 ADD	X17, X17, X4

(240) 0x436b18 ADD	X4, X4, #1

(240) 0x436b1c LDR	D4, [X24, X5]

(240) 0x436b20 LDR	X30, [SP, #104]

(240) 0x436b24 STR	D4, [X23, X30,LSL #3]

(240) 0x436b28 LDR	D5, [X22, X5]

(240) 0x436b2c STR	D5, [X18, X25,LSL #3]

(240) 0x436b30 LDR	D6, [X24, X5]

(240) 0x436b34 LDR	X25, [SP, #112]

(240) 0x436b38 STR	D6, [X23, X25,LSL #3]

(240) 0x436b3c LDR	D7, [X22, X5]

(240) 0x436b40 STR	D7, [X18, X1,LSL #3]

(240) 0x436b44 LDR	D16, [X24, X5]

(240) 0x436b48 LDR	X24, [SP, #120]

(240) 0x436b4c STR	D16, [X23, X24,LSL #3]

(240) 0x436b50 LDR	D17, [X22, X5]

(240) 0x436b54 STR	D17, [X18, X17,LSL #3]

(240) 0x436b58 B	4363cc

(240) 0x436b5c LDP	X18, X17, [X19]

(240) 0x436b60 LDR	X23, [X9, #48]

(240) 0x436b64 LDR	X24, [X17, #8]

(240) 0x436b68 LDR	X22, [X9, #64]

(240) 0x436b6c MADD	X25, X3, X23, X0

(240) 0x436b70 LDR	X23, [X18, #8]

(240) 0x436b74 LDR	D19, [X24, X5]

(240) 0x436b78 LDR	X12, [X9]

(240) 0x436b7c LDR	X30, [X9, #168]

(240) 0x436b80 STR	D19, [X22, X25,LSL #3]

(240) 0x436b84 LDP	X25, X18, [X19, #16]

(240) 0x436b88 MADD	X10, X3, X12, X0

(240) 0x436b8c MUL	X24, X30, X3

(240) 0x436b90 LDR	D18, [X23, X5]

(240) 0x436b94 ADD	X12, X24, X0

(240) 0x436b98 ADD	X30, X30, X24

(240) 0x436b9c LDR	X23, [X25, #8]

(240) 0x436ba0 ADD	X25, X24, X1

(240) 0x436ba4 ADD	X24, X30, X0

(240) 0x436ba8 ADD	X30, X30, X1

(240) 0x436bac LDR	X17, [X9, #16]

(240) 0x436bb0 STR	X24, [SP, #96]

(240) 0x436bb4 LDR	X18, [X18, #8]

(240) 0x436bb8 LDR	X22, [X9, #184]

(240) 0x436bbc STR	D18, [X17, X10,LSL #3]

(240) 0x436bc0 LDR	D31, [X23, X5]

(240) 0x436bc4 LDR	X10, [X9, #216]

(240) 0x436bc8 LDR	X17, [X9, #232]

(240) 0x436bcc STR	D31, [X22, X12,LSL #3]

(240) 0x436bd0 LDR	D30, [X18, X5]

(240) 0x436bd4 MUL	X12, X10, X3

(240) 0x436bd8 ADD	X24, X12, X0

(240) 0x436bdc ADD	X10, X10, X12

(240) 0x436be0 ADD	X12, X12, X1

(240) 0x436be4 ADD	X0, X10, X0

(240) 0x436be8 ADD	X10, X10, X1

(240) 0x436bec STR	D30, [X17, X24,LSL #3]

(240) 0x436bf0 LDR	D29, [X23, X5]

(240) 0x436bf4 STR	D29, [X22, X25,LSL #3]

(240) 0x436bf8 LDR	D28, [X18, X5]

(240) 0x436bfc LDR	X25, [SP, #96]

(240) 0x436c00 STR	D28, [X17, X12,LSL #3]

(240) 0x436c04 LDR	D26, [X23, X5]

(240) 0x436c08 STR	D26, [X22, X25,LSL #3]

(240) 0x436c0c LDR	D25, [X18, X5]

(240) 0x436c10 STR	D25, [X17, X0,LSL #3]

(240) 0x436c14 LDR	D27, [X23, X5]

(240) 0x436c18 STR	D27, [X22, X30,LSL #3]

(240) 0x436c1c LDR	D24, [X18, X5]

(240) 0x436c20 STR	D24, [X17, X10,LSL #3]

(240) 0x436c24 B	4362e4

(240) 0x436c28 LDP	X18, X24, [X19]

(240) 0x436c2c LDR	X11, [X9, #48]

(240) 0x436c30 LDR	X22, [X24, #8]

(240) 0x436c34 LDR	X23, [X18, #8]

(240) 0x436c38 MADD	X17, X3, X11, X0

(240) 0x436c3c LDR	X25, [X9, #64]

(240) 0x436c40 LDR	D16, [X22, X5]

(240) 0x436c44 LDR	X18, [X19, #16]

(240) 0x436c48 LDR	X30, [X9]

(240) 0x436c4c STR	D16, [X25, X17,LSL #3]

(240) 0x436c50 LDR	D17, [X23, X5]

(240) 0x436c54 LDR	X24, [X18, #8]

(240) 0x436c58 MADD	X11, X3, X30, X0

(240) 0x436c5c LDR	X25, [X9, #16]

(240) 0x436c60 LDR	X22, [X19, #24]

(240) 0x436c64 LDR	X17, [X9, #168]

(240) 0x436c68 LDR	X23, [X9, #184]

(240) 0x436c6c STR	D17, [X25, X11,LSL #3]

(240) 0x436c70 LDR	D22, [X24, X5]

(240) 0x436c74 MUL	X18, X17, X3

(240) 0x436c78 LDR	X22, [X22, #8]

(240) 0x436c7c LDR	X11, [X9, #216]

(240) 0x436c80 ADD	X30, X18, X0

(240) 0x436c84 ADD	X25, X18, X1

(240) 0x436c88 ADD	X17, X17, X18

(240) 0x436c8c LDR	X18, [X9, #232]

(240) 0x436c90 STR	D22, [X23, X30,LSL #3]

(240) 0x436c94 ADD	X30, X17, X1

(240) 0x436c98 LDR	D23, [X22, X5]

(240) 0x436c9c STR	X25, [SP, #96]

(240) 0x436ca0 ADD	X25, X17, X0

(240) 0x436ca4 MUL	X17, X11, X3

(240) 0x436ca8 STR	X30, [SP, #104]

(240) 0x436cac ADD	X30, X17, X0

(240) 0x436cb0 ADD	X11, X11, X17

(240) 0x436cb4 ADD	X17, X17, X1

(240) 0x436cb8 ADD	X0, X11, X0

(240) 0x436cbc STR	D23, [X18, X30,LSL #3]

(240) 0x436cc0 ADD	X11, X11, X1

(240) 0x436cc4 LDR	D21, [X24, X5]

(240) 0x436cc8 LDR	X30, [SP, #96]

(240) 0x436ccc STR	D21, [X23, X30,LSL #3]

(240) 0x436cd0 LDR	D20, [X22, X5]

(240) 0x436cd4 STR	D20, [X18, X17,LSL #3]

(240) 0x436cd8 LDR	D19, [X24, X5]

(240) 0x436cdc STR	D19, [X23, X25,LSL #3]

(240) 0x436ce0 LDR	D18, [X22, X5]

(240) 0x436ce4 STR	D18, [X18, X0,LSL #3]

(240) 0x436ce8 LDR	D31, [X24, X5]

(240) 0x436cec LDR	X24, [SP, #104]

(240) 0x436cf0 STR	D31, [X23, X24,LSL #3]

(240) 0x436cf4 LDR	D30, [X22, X5]

(240) 0x436cf8 STR	D30, [X18, X11,LSL #3]

(240) 0x436cfc B	4365c8

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►67.42+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec
►32.58+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

Coverage (%)	Name	Source Location	Module
►50.56+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec
►49.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

Coverage (%)	Name	Source Location	Module
►71.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►28.57+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►80.88+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►19.12+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►83.33+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►16.67+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►85.00+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►15.00+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►85.37+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►14.63+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►88.89+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.11+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►90.91+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►9.09+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►90.24+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►9.76+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-123

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 33% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 7.33 cycles (3.41x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	51
nb uops	51
loop length	204
used w registers	12
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00
cycles	4.50	4.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	6.38
Dispatch	7.33
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	33%
load	41%
store	50%
mul	12%
add-sub	16%
fma	12%
div/sqrt	12%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 436180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W20, W21, [X0, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 436284 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 436284 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL W23, W21, W20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W23, W22	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W2, W22, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 436644 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W8, W2, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W13, W2, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W8, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 436294 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W3, W8, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDRSW X4, [X19, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X15, X16, [X19, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W22, W3, W20, W8	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
LDP X26, X14, [X19, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X3, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
UBFM X5, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X28, X4, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W7, W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X27, [X19, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X19, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
B 4361cc <_Z14generate_chunkiR16global_variables._omp_fn.1+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-123

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 7.33 cycles (3.41x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	51
nb uops	51
loop length	204
used w registers	12
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00
cycles	4.50	4.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	7.33	7.33	7.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	6.38
Dispatch	7.33
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	33%
load	41%
store	50%
mul	12%
add-sub	16%
fma	12%
div/sqrt	12%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 436180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W20, W21, [X0, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 436284 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 436284 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL W23, W21, W20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W23, W22	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W2, W22, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 436644 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W8, W2, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W13, W2, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W8, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 436294 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W3, W8, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDRSW X4, [X19, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X15, X16, [X19, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W22, W3, W20, W8	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
LDP X26, X14, [X19, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X3, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
UBFM X5, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X28, X4, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W7, W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X27, [X19, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X19, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
B 4361cc <_Z14generate_chunkiR16global_variables._omp_fn.1+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	1	0	0.99	0	0.96	0	1.25	0	1.8	0	2.16	0	2.11	0	1.92	0	1.96	0	2.11	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.44499999284744	0.029939919710159
1x2	2	1	1.99	2	0.29999998211861	0.029764438048005
1x4	4	0.99	3.96	4	0.22499999403954	0.029286691918969
1x8	8	0.96	7.7	8	0.13000001013279	0.026615537703037
1x16	10	1.25	19.94	16	0.065000005066395	0.013265687972307
1x24	7	1.8	43.09	24	0.045000001788139	0.0065836305730045
1x32	7	2.16	69.07	32	0.035000000149012	0.0044610742479563
1x40	8	2.11	84.32	40	0.029999999329448	0.0038548556622118
1x48	10	1.92	92.16	48	0.025000000372529	0.0035877008922398
1x56	11	1.96	109.99	56	0.019999999552965	0.0030117474962026
1x64	13	2.11	135.12	64	0.02000000141561	0.00244783423841

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone ._omp_fn.1]–	0.03	0.44
▼Loop 240 - generate_chunk.cpp:85-123 - exec–	0.00	0.00
○Loop 241 - generate_chunk.cpp:91-98 - exec	0.03	0.44
○Loop 243 - generate_chunk.cpp:117-123 - exec	0.00	0.00
○Loop 242 - generate_chunk.cpp:105-112 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency