OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:44-48 [...]	Coverage (incl. loops): 0.71% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42be20 STP	X29, X30, [SP, #848]!

0x42be24 ADD	X29, SP, #0

0x42be28 STP	X19, X20, [SP, #16]

0x42be2c ORR	X19, XZR, X0

0x42be30 STP	X23, X24, [SP, #48]

0x42be34 LDP	W23, W1, [X0, #48]

0x42be38 LDR	W0, [X0, #40]

0x42be3c LDR	W2, [X19, #44]

0x42be40 ADD	W3, W1, #4

0x42be44 SUB	W24, W23, #1

0x42be48 SUB	W4, W0, #1

0x42be4c STP	W3, W4, [SP, #136]

0x42be50 CMP	W24, W3

0x42be54 B.GE	42c29c

0x42be58 STP	X21, X22, [SP, #32]

0x42be5c ADD	W22, W2, #4

0x42be60 SUB	W21, W3, W24

0x42be64 CMP	W4, W22

0x42be68 B.GE	42c2ac

0x42be6c SUB	W5, W22, W4

0x42be70 MUL	W23, W21, W5

0x42be74 STR	W5, [SP, #144]

0x42be78 BL	410210

0x42be7c ORR	W20, WZR, W0

0x42be80 BL	410240

0x42be84 UDIV	W7, W23, W20

0x42be88 ORR	W6, WZR, W0

0x42be8c MSUB	W8, W7, W20, W23

0x42be90 CMP	W0, W8

0x42be94 B.CC	42c2c8

0x42be98 MADD	W23, W7, W6, W8

0x42be9c ADD	W9, W7, W23

0x42bea0 STR	W9, [SP, #148]

0x42bea4 CMP	W23, W9

0x42bea8 B.CS	42c2ac

0x42beac LDP	W10, W11, [SP, #140]

0x42beb0 STP	X27, X28, [SP, #80]

0x42beb4 STP	X25, X26, [SP, #64]

0x42beb8 UDIV	W12, W23, W11

0x42bebc LDR	X28, [X19, #32]

0x42bec0 LDP	X4, X26, [X19, #16]

0x42bec4 MSUB	W13, W12, W11, W23

0x42bec8 ADD	W14, W12, W24

0x42becc LDP	X25, X24, [X19]

0x42bed0 SBFM	X9, X14, #0, #31

0x42bed4 ADD	W27, W13, W10

0x42bed8 SUB	W22, W22, W27

0x42bedc CMP	W7, W22

0x42bee0 CSEL	W5, W7, W22, #9

0x42bee4 ADD	W20, W23, W5

0x42bee8 CMP	W23, W20

0x42beec B.CS	42c278

  (159) 0x42bef0 LDR	X30, [X26]

  (159) 0x42bef4 ADD	X16, X9, #1

  (159) 0x42bef8 LDR	X17, [X4]

  (159) 0x42befc LDR	X18, [X24]

  (159) 0x42bf00 MUL	X3, X9, X30

  (159) 0x42bf04 LDR	X15, [X4, #16]

  (159) 0x42bf08 MADD	X14, X9, X17, X17

  (159) 0x42bf0c LDR	X13, [X24, #16]

  (159) 0x42bf10 MUL	X6, X9, X18

  (159) 0x42bf14 LDR	X21, [X25, #16]

  (159) 0x42bf18 SUB	X8, X14, X17

  (159) 0x42bf1c LDR	X23, [X26, #16]

  (159) 0x42bf20 STR	X8, [SP, #120]

  (159) 0x42bf24 LDR	X22, [X28, #16]

  (159) 0x42bf28 STP	X16, X3, [SP, #104]

  (159) 0x42bf2c LDR	X19, [X25]

  (159) 0x42bf30 LDR	X1, [X28]

  (159) 0x42bf34 MUL	X7, X9, X19

  (159) 0x42bf38 MUL	X30, X9, X1

  (159) 0x42bf3c STR	X7, [SP, #128]

  (159) 0x42bf40 CMP	W5, #1

  (159) 0x42bf44 B.EQ	42c1cc

  (159) 0x42bf48 SBFM	X2, X27, #0, #31

  (159) 0x42bf4c UBFM	W9, W5, #1, #31

  (159) 0x42bf50 ADD	X10, X6, X2

  (159) 0x42bf54 ADD	X19, X7, X2

  (159) 0x42bf58 ADD	X16, X10, #1

  (159) 0x42bf5c ADD	X7, X14, X2

  (159) 0x42bf60 ADD	X10, X21, X19,LSL #3

  (159) 0x42bf64 UBFM	X12, X9, #60, #59

  (159) 0x42bf68 UBFM	X9, X16, #61, #60

  (159) 0x42bf6c ADD	X1, X13, X16,LSL #3

  (159) 0x42bf70 SUB	X11, X12, #16

  (159) 0x42bf74 ADD	X16, X3, X2

  (159) 0x42bf78 ADD	X3, X15, X7,LSL #3

  (159) 0x42bf7c UBFM	X17, X11, #4, #63

  (159) 0x42bf80 STR	X9, [SP, #152]

  (159) 0x42bf84 SUB	X9, X9, #8

  (159) 0x42bf88 ADD	X18, X17, #1

  (159) 0x42bf8c ADD	X17, X8, X2

  (159) 0x42bf90 ADD	X2, X30, X2

  (159) 0x42bf94 STR	X3, [SP, #96]

  (159) 0x42bf98 ADD	X3, X13, X9

  (159) 0x42bf9c STR	X9, [SP, #160]

  (159) 0x42bfa0 UBFM	X9, X2, #61, #60

  (159) 0x42bfa4 ANDS	X11, X18, #0x3

  (159) 0x42bfa8 ADD	X8, X15, X17,LSL #3

  (159) 0x42bfac UBFM	X18, X7, #61, #60

  (159) 0x42bfb0 MOVZ	X0, #0

  (159) 0x42bfb4 STR	X9, [SP, #168]

  (159) 0x42bfb8 ADD	X7, X23, X16,LSL #3

  (159) 0x42bfbc UBFM	X19, X19, #61, #60

  (159) 0x42bfc0 ADD	X2, X22, X2,LSL #3

  (159) 0x42bfc4 UBFM	X17, X17, #61, #60

  (159) 0x42bfc8 UBFM	X16, X16, #61, #60

  (159) 0x42bfcc B.EQ	42c2c0

  (159) 0x42bfd0 CMP	X11, #1

  (159) 0x42bfd4 B.EQ	42c06c

  (159) 0x42bfd8 CMP	X11, #2

  (159) 0x42bfdc B.EQ	42c028

  (159) 0x42bfe0 LDR	Q2, [X21, X19]

  (159) 0x42bfe4 MOVZ	X0, #16

  (159) 0x42bfe8 LDP	X19, X11, [SP, #152]

  (159) 0x42bfec LDR	Q1, [X15, X18]

  (159) 0x42bff0 LDR	Q3, [X13, X19]

  (159) 0x42bff4 LDR	Q0, [X15, X17]

  (159) 0x42bff8 LDR	Q30, [X13, X11]

  (159) 0x42bffc FADD	V4.2D, V3.2D, V2.2D

  (159) 0x42c000 LDR	X18, [SP, #168]

  (159) 0x42c004 FADD	V5.2D, V0.2D, V30.2D

  (159) 0x42c008 FADD	V6.2D, V4.2D, V1.2D

  (159) 0x42c00c FSUB	V7.2D, V6.2D, V5.2D

  (159) 0x42c010 STR	Q7, [X23, X16]

  (159) 0x42c014 LDR	Q29, [X13, X11]

  (159) 0x42c018 LDR	Q31, [X13, X19]

  (159) 0x42c01c FSUB	V16.2D, V29.2D, V31.2D

  (159) 0x42c020 FADD	V17.2D, V16.2D, V7.2D

  (159) 0x42c024 STR	Q17, [X22, X18]

  (159) 0x42c028 LDR	Q18, [X1, X0]

  (159) 0x42c02c LDR	Q19, [X10, X0]

  (159) 0x42c030 LDR	X17, [SP, #96]

  (159) 0x42c034 LDR	Q20, [X8, X0]

  (159) 0x42c038 LDR	Q27, [X3, X0]

  (159) 0x42c03c FADD	V21.2D, V18.2D, V19.2D

  (159) 0x42c040 LDR	Q23, [X17, X0]

  (159) 0x42c044 FADD	V22.2D, V20.2D, V27.2D

  (159) 0x42c048 FADD	V24.2D, V21.2D, V23.2D

  (159) 0x42c04c FSUB	V25.2D, V24.2D, V22.2D

  (159) 0x42c050 STR	Q25, [X7, X0]

  (159) 0x42c054 LDR	Q26, [X3, X0]

  (159) 0x42c058 LDR	Q28, [X1, X0]

  (159) 0x42c05c FSUB	V2.2D, V26.2D, V28.2D

  (159) 0x42c060 FADD	V1.2D, V2.2D, V25.2D

  (159) 0x42c064 STR	Q1, [X2, X0]

  (159) 0x42c068 ADD	X0, X0, #16

  (159) 0x42c06c LDR	Q0, [X1, X0]

  (159) 0x42c070 LDR	Q3, [X10, X0]

  (159) 0x42c074 LDR	X9, [SP, #96]

  (159) 0x42c078 LDR	Q30, [X8, X0]

  (159) 0x42c07c LDR	Q4, [X3, X0]

  (159) 0x42c080 FADD	V5.2D, V0.2D, V3.2D

  (159) 0x42c084 LDR	Q7, [X9, X0]

  (159) 0x42c088 FADD	V6.2D, V30.2D, V4.2D

  (159) 0x42c08c FADD	V29.2D, V5.2D, V7.2D

  (159) 0x42c090 FSUB	V31.2D, V29.2D, V6.2D

  (159) 0x42c094 STR	Q31, [X7, X0]

  (159) 0x42c098 LDR	Q16, [X3, X0]

  (159) 0x42c09c LDR	Q17, [X1, X0]

  (159) 0x42c0a0 FSUB	V18.2D, V16.2D, V17.2D

  (159) 0x42c0a4 FADD	V19.2D, V18.2D, V31.2D

  (159) 0x42c0a8 STR	Q19, [X2, X0]

  (159) 0x42c0ac ADD	X0, X0, #16

  (159) 0x42c0b0 CMP	X0, X12

  (159) 0x42c0b4 B.EQ	42c1c0

    (160) 0x42c0b8 LDR	Q20, [X1, X0]

    (160) 0x42c0bc ADD	X19, X0, #16

    (160) 0x42c0c0 ADD	X11, X0, #32

    (160) 0x42c0c4 ADD	X16, X0, #48

    (160) 0x42c0c8 LDR	Q27, [X10, X0]

    (160) 0x42c0cc LDR	Q21, [X9, X0]

    (160) 0x42c0d0 LDR	Q22, [X8, X0]

    (160) 0x42c0d4 LDR	Q23, [X3, X0]

    (160) 0x42c0d8 FADD	V24.2D, V20.2D, V27.2D

    (160) 0x42c0dc FADD	V26.2D, V22.2D, V23.2D

    (160) 0x42c0e0 FADD	V25.2D, V24.2D, V21.2D

    (160) 0x42c0e4 FSUB	V28.2D, V25.2D, V26.2D

    (160) 0x42c0e8 STR	Q28, [X7, X0]

    (160) 0x42c0ec LDR	Q2, [X3, X0]

    (160) 0x42c0f0 LDR	Q1, [X1, X0]

    (160) 0x42c0f4 FSUB	V0.2D, V2.2D, V1.2D

    (160) 0x42c0f8 FADD	V3.2D, V0.2D, V28.2D

    (160) 0x42c0fc STR	Q3, [X2, X0]

    (160) 0x42c100 ADD	X0, X0, #64

    (160) 0x42c104 LDR	Q30, [X1, X19]

    (160) 0x42c108 LDR	Q4, [X10, X19]

    (160) 0x42c10c LDR	Q5, [X9, X19]

    (160) 0x42c110 LDR	Q6, [X8, X19]

    (160) 0x42c114 LDR	Q7, [X3, X19]

    (160) 0x42c118 FADD	V29.2D, V30.2D, V4.2D

    (160) 0x42c11c FADD	V31.2D, V6.2D, V7.2D

    (160) 0x42c120 FADD	V16.2D, V29.2D, V5.2D

    (160) 0x42c124 FSUB	V17.2D, V16.2D, V31.2D

    (160) 0x42c128 STR	Q17, [X7, X19]

    (160) 0x42c12c LDR	Q18, [X3, X19]

    (160) 0x42c130 LDR	Q19, [X1, X19]

    (160) 0x42c134 FSUB	V20.2D, V18.2D, V19.2D

    (160) 0x42c138 FADD	V27.2D, V20.2D, V17.2D

    (160) 0x42c13c STR	Q27, [X2, X19]

    (160) 0x42c140 LDR	Q21, [X1, X11]

    (160) 0x42c144 LDR	Q22, [X10, X11]

    (160) 0x42c148 LDR	Q23, [X9, X11]

    (160) 0x42c14c LDR	Q24, [X8, X11]

    (160) 0x42c150 LDR	Q25, [X3, X11]

    (160) 0x42c154 FADD	V26.2D, V21.2D, V22.2D

    (160) 0x42c158 FADD	V28.2D, V24.2D, V25.2D

    (160) 0x42c15c FADD	V2.2D, V26.2D, V23.2D

    (160) 0x42c160 FSUB	V1.2D, V2.2D, V28.2D

    (160) 0x42c164 STR	Q1, [X7, X11]

    (160) 0x42c168 LDR	Q0, [X3, X11]

    (160) 0x42c16c LDR	Q3, [X1, X11]

    (160) 0x42c170 FSUB	V30.2D, V0.2D, V3.2D

    (160) 0x42c174 FADD	V4.2D, V30.2D, V1.2D

    (160) 0x42c178 STR	Q4, [X2, X11]

    (160) 0x42c17c LDR	Q5, [X1, X16]

    (160) 0x42c180 LDR	Q6, [X10, X16]

    (160) 0x42c184 LDR	Q7, [X9, X16]

    (160) 0x42c188 LDR	Q29, [X8, X16]

    (160) 0x42c18c LDR	Q31, [X3, X16]

    (160) 0x42c190 FADD	V16.2D, V5.2D, V6.2D

    (160) 0x42c194 FADD	V17.2D, V29.2D, V31.2D

    (160) 0x42c198 FADD	V18.2D, V16.2D, V7.2D

    (160) 0x42c19c FSUB	V19.2D, V18.2D, V17.2D

    (160) 0x42c1a0 STR	Q19, [X7, X16]

    (160) 0x42c1a4 LDR	Q20, [X3, X16]

    (160) 0x42c1a8 LDR	Q27, [X1, X16]

    (160) 0x42c1ac FSUB	V21.2D, V20.2D, V27.2D

    (160) 0x42c1b0 FADD	V22.2D, V21.2D, V19.2D

    (160) 0x42c1b4 STR	Q22, [X2, X16]

    (160) 0x42c1b8 CMP	X0, X12

    (160) 0x42c1bc B.NE	42c0b8

  (159) 0x42c1c0 TBZ	W5, #0, 42c240

  (159) 0x42c1c4 AND	W5, W5, #0xfffffffe

  (159) 0x42c1c8 ADD	W27, W27, W5

  (159) 0x42c1cc LDR	X3, [SP, #128]

  (159) 0x42c1d0 SBFM	X12, X27, #0, #31

  (159) 0x42c1d4 ADD	W1, W27, #1

  (159) 0x42c1d8 ADD	X14, X14, X12

  (159) 0x42c1dc ADD	X10, X6, W1,SXTW

  (159) 0x42c1e0 ADD	X6, X6, X12

  (159) 0x42c1e4 UBFM	X8, X10, #61, #60

  (159) 0x42c1e8 UBFM	X7, X6, #61, #60

  (159) 0x42c1ec LDR	D23, [X15, X14,LSL #3]

  (159) 0x42c1f0 ADD	X30, X30, X12

  (159) 0x42c1f4 ADD	X2, X3, X12

  (159) 0x42c1f8 LDR	D24, [X13, X8]

  (159) 0x42c1fc LDR	D28, [X21, X2,LSL #3]

  (159) 0x42c200 LDR	X21, [SP, #120]

  (159) 0x42c204 LDR	D25, [X13, X7]

  (159) 0x42c208 FADD	D2, D23, D28

  (159) 0x42c20c ADD	X18, X21, X12

  (159) 0x42c210 LDR	D1, [X15, X18,LSL #3]

  (159) 0x42c214 FSUB	D26, D24, S25

  (159) 0x42c218 LDR	X15, [SP, #112]

  (159) 0x42c21c FSUB	D0, D2, S1

  (159) 0x42c220 ADD	X17, X15, X12

  (159) 0x42c224 FADD	D3, D0, D26

  (159) 0x42c228 STR	D3, [X23, X17,LSL #3]

  (159) 0x42c22c LDR	D30, [X13, X7]

  (159) 0x42c230 LDR	D4, [X13, X8]

  (159) 0x42c234 FSUB	D5, D30, S4

  (159) 0x42c238 FADD	D6, D5, D3

  (159) 0x42c23c STR	D6, [X22, X30,LSL #3]

  (159) 0x42c240 LDR	X9, [SP, #104]

  (159) 0x42c244 ORR	W23, WZR, W20

  (159) 0x42c248 LDR	W20, [SP, #136]

  (159) 0x42c24c CMP	W20, W9

  (159) 0x42c250 B.LE	42c290

  (159) 0x42c254 LDR	W13, [SP, #148]

  (159) 0x42c258 LDR	W22, [SP, #144]

  (159) 0x42c25c LDR	W27, [SP, #140]

  (159) 0x42c260 SUB	W7, W13, W23

  (159) 0x42c264 CMP	W7, W22

  (159) 0x42c268 CSEL	W5, W7, W22, #9

  (159) 0x42c26c ADD	W20, W23, W5

  (159) 0x42c270 CMP	W23, W20

  (159) 0x42c274 B.CC	42bef0

(161) 0x42c278 ADD	X15, X9, #1

(161) 0x42c27c LDR	W20, [SP, #136]

(161) 0x42c280 STR	X15, [SP, #104]

(161) 0x42c284 LDR	X9, [SP, #104]

(161) 0x42c288 CMP	W20, W9

(161) 0x42c28c B.GT	42c254

0x42c290 LDP	X21, X22, [SP, #32]

0x42c294 LDP	X25, X26, [SP, #64]

0x42c298 LDP	X27, X28, [SP, #80]

0x42c29c LDP	X19, X20, [SP, #16]

0x42c2a0 LDP	X23, X24, [SP, #48]

0x42c2a4 LDP	X29, X30, [SP], #176

0x42c2a8 RET

0x42c2ac LDP	X21, X22, [SP, #32]

0x42c2b0 LDP	X19, X20, [SP, #16]

0x42c2b4 LDP	X23, X24, [SP, #48]

0x42c2b8 LDP	X29, X30, [SP], #176

0x42c2bc RET

  (159) 0x42c2c0 LDR	X9, [SP, #96]

  (159) 0x42c2c4 B	42c0b8

0x42c2c8 ADD	W7, W7, #1

0x42c2cc MOVZ	W8, #0

0x42c2d0 B	42be98

0x42c2d4 HINT	#0

0x42c2d8 HINT	#0

0x42c2dc HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►50.09+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec
►49.91+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

Coverage (%)	Name	Source Location	Module
►74.47+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►25.53+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►87.23+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.77+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►93.64+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.36+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►95.79+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.21+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►96.88+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.12+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►97.48+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.52+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►97.90+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.10+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►98.19+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.81+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►98.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.83 cycles (2.83x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	70
nb uops	67
loop length	280
used w registers	22
used x registers	17
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50
cycles	5.00	5.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	8.38
Dispatch	8.83
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	27%
load	41%
store	38%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42be20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X19, #44]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W24, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42c29c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W3, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42c2ac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W23, W21, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W23, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W8, W7, W20, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42c2c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W23, W7, W6, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W23, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42c2ac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W10, W11, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UDIV W12, W23, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
LDR X28, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X4, X26, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W13, W12, W11, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W14, W12, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X25, X24, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X9, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W27, W13, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W22, W22, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W5, W7, W22, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W23, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W23, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42c278 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42be98 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.83 cycles (2.83x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	70
nb uops	67
loop length	280
used w registers	22
used x registers	17
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50
cycles	5.00	5.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	8.38
Dispatch	8.83
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	27%
load	41%
store	38%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42be20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W23, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X19, #44]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W3, W4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W24, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42c29c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W3, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42c2ac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W22, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W23, W21, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W5, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W23, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W8, W7, W20, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42c2c8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W23, W7, W6, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W23, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42c2ac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W10, W11, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UDIV W12, W23, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
LDR X28, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X4, X26, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W13, W12, W11, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W14, W12, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X25, X24, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X9, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W27, W13, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W22, W22, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W5, W7, W22, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W23, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W23, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42c278 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42be98 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	0.98	0.01	0.92	0.06	0.66	0.31	0.33	0.81	0.22	0.99	0.17	1.08	0.15	1.14	0.12	1.19	0.1	1.23	0.09	1.25

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	10.569999694824	0.711157143116
1x2	2	0.98	1.96	2	5.3750004768372	0.71769082546234
1x4	4	0.92	3.67	4	2.909999370575	0.75026577711105
1x8	8	0.66	5.31	8	2.0000002384186	0.91633504629135
1x16	16	0.33	5.23	16	1.9699996709824	1.2021052837372
1x24	24	0.22	5.29	24	1.9650001525879	1.2725608348846
1x32	32	0.17	5.59	32	1.8949998617172	1.3098828792572
1x40	40	0.15	5.81	40	1.80499958992	1.3296430110931
1x48	48	0.12	5.81	48	1.8000001907349	1.3521646261215
1x56	56	0.1	5.75	56	1.8149995803833	1.3677438497543
1x64	64	0.09	5.71	64	1.8399996757507	1.3757424354553

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	0.71	10.57
▼Loop 161 - advec_cell.cpp:44-48 - exec–	0.00	0.00
▼Loop 159 - advec_cell.cpp:44-48 - exec–	0.00	0.00
○Loop 160 - advec_cell.cpp:47-48 - exec	0.71	10.51

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency