OV - exec - Loop 174

	Loop Id: 174	Module: exec	Source: advec_cell.cpp:67-110 [...]	Coverage: NA%

0x42d780 CMP	W7, W19

0x42d784 CSEL	W1, W7, W19, #9

0x42d788 ADD	W30, W4, W1

0x42d78c STR	W30, [SP, #304]

0x42d790 CMP	W4, W30

0x42d794 B.CS	42dfd0

0x42d798 LDR	X19, [X14]

0x42d79c SUB	W21, W1, #1

0x42d7a0 LDR	X23, [X13]

0x42d7a4 LDR	X4, [X28]

0x42d7a8 MUL	X24, X25, X19

0x42d7ac LDR	X7, [X28, #16]

0x42d7b0 MUL	X3, X25, X23

0x42d7b4 LDR	X8, [X14, #16]

0x42d7b8 MUL	X23, X25, X4

0x42d7bc LDR	X11, [SP, #320]

0x42d7c0 STR	X7, [SP, #184]

0x42d7c4 LDR	X0, [X10]

0x42d7c8 LDR	X2, [X15]

0x42d7cc LDR	X20, [X27]

0x42d7d0 MUL	X30, X25, X0

0x42d7d4 LDR	X16, [X11, #8]

0x42d7d8 MUL	X18, X25, X2

0x42d7dc LDR	X9, [X10, #16]

0x42d7e0 MUL	X6, X25, X20

0x42d7e4 LDR	X5, [X13, #16]

0x42d7e8 LDR	X22, [X15, #16]

0x42d7ec LDR	X4, [X27, #16]

0x42d7f0 STP	X8, X24, [SP, #168]

0x42d7f4 CMP	W21, #2

0x42d7f8 B.LS	42e058

0x42d7fc SBFM	X12, X26, #0, #31

0x42d800 MOVZ	X11, #0

0x42d804 ADD	X2, X24, X12

0x42d808 DUP	V2.4S, W26

0x42d80c ADD	X0, X18, X12

0x42d810 ADD	X19, X8, X2,LSL #3

0x42d814 ADRP	X8,

0x42d818 ADD	X17, X23, X12

0x42d81c ADD	X20, X22, X0,LSL #3

0x42d820 UBFM	W24, W1, #2, #31

0x42d824 STR	W26, [SP, #192]

0x42d828 LDR	Q0, [X8, #576]

0x42d82c ADD	X17, X7, X17,LSL #3

0x42d830 UBFM	X24, X24, #59, #58

0x42d834 ADD	X7, X9, X30,LSL #3

0x42d838 STR	W1, [SP, #200]

0x42d83c ADD	X0, X4, X6,LSL #3

0x42d840 STP	X15, X22, [SP, #208]

0x42d844 ADD	X2, X5, X3,LSL #3

0x42d848 ADD	X21, X16, X12,LSL #3

0x42d84c MOVZ	X12, #16

0x42d850 STP	X10, X27, [SP, #224]

0x42d854 ADD	V2.4S, V2.4S, V0.4S

0x42d858 STP	X14, X13, [SP, #240]

0x42d85c STP	X18, X28, [SP, #256]

0x42d860 STP	X4, X6, [SP, #272]

0x42d864 STP	X9, X3, [SP, #288]

  (175) 0x42d868 ORR	V1.16B, V2.16B, V2.16B

  (175) 0x42d86c ADD	V2.4S, V2.4S, V11.4S

  (175) 0x42d870 LDR	Q3, [X20, X11]

  (175) 0x42d874 ADD	V24.4S, V1.4S, V12.4S

  (175) 0x42d878 SSHLL	V28.2D, V1.2S, #32

  (175) 0x42d87c LDR	Q4, [X20, X12]

  (175) 0x42d880 ADD	V7.4S, V1.4S, V14.4S

  (175) 0x42d884 ADD	V26.4S, V1.4S, V13.4S

  (175) 0x42d888 SSHLL2	V31.2D, V1.4S, #32

  (175) 0x42d88c LDR	Q27, [X21, X11]

  (175) 0x42d890 FCMGT	V25.2D, V3.2D, #0.0000000

  (175) 0x42d894 SSHLL	V20.2D, V24.2S, #32

  (175) 0x42d898 SMIN	V17.4S, V7.4S, V10.4S

  (175) 0x42d89c FCMGT	V22.2D, V4.2D, #0.0000000

  (175) 0x42d8a0 SSHLL	V23.2D, V26.2S, #32

  (175) 0x42d8a4 FABS	V18.2D, V3.2D

  (175) 0x42d8a8 SSHLL2	V0.2D, V24.4S, #32

  (175) 0x42d8ac SSHLL2	V1.2D, V26.4S, #32

  (175) 0x42d8b0 ORR	V19.16B, V25.16B, V25.16B

  (175) 0x42d8b4 SSHLL	V21.2D, V17.2S, #32

  (175) 0x42d8b8 SSHLL2	V30.2D, V17.4S, #32

  (175) 0x42d8bc ORR	V16.16B, V22.16B, V22.16B

  (175) 0x42d8c0 BSL	V19.16B, V20.16B, V28.16B

  (175) 0x42d8c4 BIF	V28.16B, V20.16B, V25.16B

  (175) 0x42d8c8 BIF	V23.16B, V21.16B, V25.16B

  (175) 0x42d8cc BSL	V16.16B, V0.16B, V31.16B

  (175) 0x42d8d0 FMOV	X13, D19

  (175) 0x42d8d4 MOV	D7, V19.D[1]

  (175) 0x42d8d8 FMOV	X15, D28

  (175) 0x42d8dc MOV	D28, V28.D[1]

  (175) 0x42d8e0 FMOV	X3, D23

  (175) 0x42d8e4 BIF	V31.16B, V0.16B, V22.16B

  (175) 0x42d8e8 BSL	V25.16B, V20.16B, V21.16B

  (175) 0x42d8ec FMOV	X27, D16

  (175) 0x42d8f0 FMOV	X28, D7

  (175) 0x42d8f4 MOV	D17, V23.D[1]

  (175) 0x42d8f8 MOV	D20, V16.D[1]

  (175) 0x42d8fc FMOV	X10, D28

  (175) 0x42d900 BIF	V1.16B, V30.16B, V22.16B

  (175) 0x42d904 MOV	D24, V31.D[1]

  (175) 0x42d908 FMOV	X1, D31

  (175) 0x42d90c UBFM	X9, X13, #61, #60

  (175) 0x42d910 BIT	V30.16B, V0.16B, V22.16B

  (175) 0x42d914 UBFM	X26, X15, #61, #60

  (175) 0x42d918 FMOV	X22, D20

  (175) 0x42d91c FABS	V0.2D, V4.2D

  (175) 0x42d920 LDR	D26, [X7, X9]

  (175) 0x42d924 UBFM	X13, X3, #61, #60

  (175) 0x42d928 MOV	D22, V1.D[1]

  (175) 0x42d92c UBFM	X8, X27, #61, #60

  (175) 0x42d930 FMOV	X18, D24

  (175) 0x42d934 LDR	D21, [X9, X0]

  (175) 0x42d938 UBFM	X14, X28, #61, #60

  (175) 0x42d93c ADD	X3, X7, X14

  (175) 0x42d940 UBFM	X4, X10, #61, #60

  (175) 0x42d944 LDR	D23, [X0, X26]

  (175) 0x42d948 UBFM	X1, X1, #61, #60

  (175) 0x42d94c MOV	X28, V25.D[1]

  (175) 0x42d950 FMOV	D31, D26

  (175) 0x42d954 FMOV	X6, D17

  (175) 0x42d958 FMOV	X15, D1

  (175) 0x42d95c LDR	D19, [X7, X8]

  (175) 0x42d960 UBFM	X10, X22, #61, #60

  (175) 0x42d964 UBFM	X22, X18, #61, #60

  (175) 0x42d968 MOV	X27, V30.D[1]

  (175) 0x42d96c LD1	{V31.D[1]}, [X3]

  (175) 0x42d970 ADD	X3, X14, X0

  (175) 0x42d974 LD1	{V21.D[1]}, [X3]

  (175) 0x42d978 ADD	X3, X0, X4

  (175) 0x42d97c UBFM	X18, X6, #61, #60

  (175) 0x42d980 LD1	{V23.D[1]}, [X3]

  (175) 0x42d984 UBFM	X6, X15, #61, #60

  (175) 0x42d988 FMOV	X3, D25

  (175) 0x42d98c LDR	D16, [X16, X28,LSL #3]

  (175) 0x42d990 FMOV	X15, D22

  (175) 0x42d994 LDR	D22, [X8, X0]

  (175) 0x42d998 FMOV	X28, D30

  (175) 0x42d99c FDIV	V18.2D, V18.2D, V31.2D

  (175) 0x42d9a0 LDR	D25, [X0, X1]

  (175) 0x42d9a4 LDR	D7, [X16, X3,LSL #3]

  (175) 0x42d9a8 ADD	X3, X7, X10

  (175) 0x42d9ac FSUB	V28.2D, V23.2D, V21.2D

  (175) 0x42d9b0 LD1	{V19.D[1]}, [X3]

  (175) 0x42d9b4 ADD	X3, X10, X0

  (175) 0x42d9b8 UBFM	X15, X15, #61, #60

  (175) 0x42d9bc FADD	V1.2D, V18.2D, V29.2D

  (175) 0x42d9c0 LDR	D30, [X0, X13]

  (175) 0x42d9c4 FSUB	V26.2D, V15.2D, V18.2D

  (175) 0x42d9c8 FSUB	V18.2D, V29.2D, V18.2D

  (175) 0x42d9cc LD1	{V22.D[1]}, [X3]

  (175) 0x42d9d0 ADD	X3, X0, X22

  (175) 0x42d9d4 MOV	V7.D[1], V16.D[0]

  (175) 0x42d9d8 LDR	D20, [X16, X28,LSL #3]

  (175) 0x42d9dc ADD	X28, X0, X15

  (175) 0x42d9e0 LDR	D31, [X0, X6]

  (175) 0x42d9e4 FDIV	V23.2D, V27.2D, V7.2D

  (175) 0x42d9e8 FDIV	V24.2D, V0.2D, V19.2D

  (175) 0x42d9ec FABS	V0.2D, V28.2D

  (175) 0x42d9f0 LD1	{V25.D[1]}, [X3]

  (175) 0x42d9f4 ADD	X3, X14, X0

  (175) 0x42d9f8 LDR	D19, [X16, X27,LSL #3]

  (175) 0x42d9fc ADD	X27, X0, X18

  (175) 0x42da00 FMOV	D27, D20

  (175) 0x42da04 FMUL	V23.2D, V23.2D, V1.2D

  (175) 0x42da08 LD1	{V30.D[1]}, [X27]

  (175) 0x42da0c ADD	X27, X10, X0

  (175) 0x42da10 FADD	V20.2D, V24.2D, V29.2D

  (175) 0x42da14 LD1	{V31.D[1]}, [X28]

  (175) 0x42da18 LDR	Q17, [X21, X12]

  (175) 0x42da1c MOV	V27.D[1], V19.D[0]

  (175) 0x42da20 FSUB	V25.2D, V25.2D, V22.2D

  (175) 0x42da24 FMUL	V19.2D, V26.2D, V0.2D

  (175) 0x42da28 FSUB	V30.2D, V21.2D, V30.2D

  (175) 0x42da2c FDIV	V1.2D, V17.2D, V27.2D

  (175) 0x42da30 FSUB	V27.2D, V15.2D, V24.2D

  (175) 0x42da34 FSUB	V31.2D, V22.2D, V31.2D

  (175) 0x42da38 FABS	V16.2D, V25.2D

  (175) 0x42da3c FMUL	V17.2D, V1.2D, V20.2D

  (175) 0x42da40 FABS	V7.2D, V30.2D

  (175) 0x42da44 FMUL	V30.2D, V30.2D, V28.2D

  (175) 0x42da48 FMUL	V20.2D, V27.2D, V16.2D

  (175) 0x42da4c FABS	V1.2D, V31.2D

  (175) 0x42da50 FMLA	V19.2D, V23.2D, V7.2D

  (175) 0x42da54 FMLA	V20.2D, V17.2D, V1.2D

  (175) 0x42da58 FCMLE	V28.2D, V28.2D, #0.0000000

  (175) 0x42da5c FMUL	V31.2D, V31.2D, V25.2D

  (175) 0x42da60 FCMLE	V25.2D, V25.2D, #0.0000000

  (175) 0x42da64 FMINNM	V0.2D, V7.2D, V0.2D

  (175) 0x42da68 FMINNM	V16.2D, V1.2D, V16.2D

  (175) 0x42da6c FMUL	V19.2D, V19.2D, V6.2D

  (175) 0x42da70 FCMGT	V7.2D, V30.2D, #0.0000000

  (175) 0x42da74 BSL	V28.16B, V5.16B, V29.16B

  (175) 0x42da78 FMUL	V30.2D, V20.2D, V6.2D

  (175) 0x42da7c FSUB	V24.2D, V29.2D, V24.2D

  (175) 0x42da80 BSL	V25.16B, V5.16B, V29.16B

  (175) 0x42da84 FMUL	V18.2D, V18.2D, V28.2D

  (175) 0x42da88 FMINNM	V28.2D, V19.2D, V0.2D

  (175) 0x42da8c FMINNM	V20.2D, V30.2D, V16.2D

  (175) 0x42da90 ORR	V0.16B, V21.16B, V21.16B

  (175) 0x42da94 ORR	V16.16B, V22.16B, V22.16B

  (175) 0x42da98 FMUL	V24.2D, V24.2D, V25.2D

  (175) 0x42da9c FCMGT	V1.2D, V31.2D, #0.0000000

  (175) 0x42daa0 FMLA	V0.2D, V18.2D, V28.2D

  (175) 0x42daa4 FMLA	V16.2D, V24.2D, V20.2D

  (175) 0x42daa8 BSL	V7.16B, V0.16B, V21.16B

  (175) 0x42daac BSL	V1.16B, V16.16B, V22.16B

  (175) 0x42dab0 FMUL	V30.2D, V3.2D, V7.2D

  (175) 0x42dab4 FMUL	V31.2D, V4.2D, V1.2D

  (175) 0x42dab8 STR	Q30, [X19, X11]

  (175) 0x42dabc FABS	V3.2D, V30.2D

  (175) 0x42dac0 STR	Q31, [X19, X12]

  (175) 0x42dac4 LDR	D4, [X9, X0]

  (175) 0x42dac8 LDR	D7, [X8, X0]

  (175) 0x42dacc LDR	D25, [X7, X9]

  (175) 0x42dad0 LDR	D22, [X7, X14]

  (175) 0x42dad4 LD1	{V4.D[1]}, [X3]

  (175) 0x42dad8 LDR	D18, [X7, X8]

  (175) 0x42dadc LD1	{V7.D[1]}, [X27]

  (175) 0x42dae0 MOV	V25.D[1], V22.D[0]

  (175) 0x42dae4 LDR	D21, [X14, X2]

  (175) 0x42dae8 LDR	D20, [X9, X2]

  (175) 0x42daec ADD	X9, X10, X2

  (175) 0x42daf0 FMUL	V19.2D, V4.2D, V25.2D

  (175) 0x42daf4 LDR	D1, [X4, X2]

  (175) 0x42daf8 LDR	D0, [X26, X2]

  (175) 0x42dafc MOV	V20.D[1], V21.D[0]

  (175) 0x42db00 LDR	D21, [X8, X2]

  (175) 0x42db04 FDIV	V16.2D, V3.2D, V19.2D

  (175) 0x42db08 LDR	D28, [X22, X2]

  (175) 0x42db0c LDR	D24, [X1, X2]

  (175) 0x42db10 MOV	V0.D[1], V1.D[0]

  (175) 0x42db14 FSUB	V19.2D, V29.2D, V16.2D

  (175) 0x42db18 LDR	D3, [X18, X2]

  (175) 0x42db1c LDR	D25, [X13, X2]

  (175) 0x42db20 FSUB	V22.2D, V0.2D, V20.2D

  (175) 0x42db24 LD1	{V21.D[1]}, [X9]

  (175) 0x42db28 MOV	V24.D[1], V28.D[0]

  (175) 0x42db2c LDR	D1, [X15, X2]

  (175) 0x42db30 LDR	D0, [X6, X2]

  (175) 0x42db34 MOV	V25.D[1], V3.D[0]

  (175) 0x42db38 FABS	V4.2D, V22.2D

  (175) 0x42db3c FSUB	V25.2D, V20.2D, V25.2D

  (175) 0x42db40 FSUB	V24.2D, V24.2D, V21.2D

  (175) 0x42db44 MOV	V0.D[1], V1.D[0]

  (175) 0x42db48 LDR	D1, [X7, X10]

  (175) 0x42db4c FMUL	V26.2D, V26.2D, V4.2D

  (175) 0x42db50 FSUB	V28.2D, V21.2D, V0.2D

  (175) 0x42db54 FABS	V3.2D, V24.2D

  (175) 0x42db58 FABS	V16.2D, V25.2D

  (175) 0x42db5c MOV	V18.D[1], V1.D[0]

  (175) 0x42db60 FMUL	V0.2D, V25.2D, V22.2D

  (175) 0x42db64 FCMLE	V22.2D, V22.2D, #0.0000000

  (175) 0x42db68 FMUL	V27.2D, V27.2D, V3.2D

  (175) 0x42db6c FMLA	V26.2D, V23.2D, V16.2D

  (175) 0x42db70 FABS	V23.2D, V28.2D

  (175) 0x42db74 FMINNM	V4.2D, V16.2D, V4.2D

  (175) 0x42db78 FMUL	V28.2D, V28.2D, V24.2D

  (175) 0x42db7c FMLA	V27.2D, V17.2D, V23.2D

  (175) 0x42db80 FMINNM	V17.2D, V23.2D, V3.2D

  (175) 0x42db84 FMUL	V26.2D, V26.2D, V6.2D

  (175) 0x42db88 FMUL	V7.2D, V7.2D, V18.2D

  (175) 0x42db8c FCMLE	V18.2D, V24.2D, #0.0000000

  (175) 0x42db90 FABS	V3.2D, V31.2D

  (175) 0x42db94 BSL	V22.16B, V5.16B, V29.16B

  (175) 0x42db98 FMUL	V24.2D, V27.2D, V6.2D

  (175) 0x42db9c FMINNM	V16.2D, V26.2D, V4.2D

  (175) 0x42dba0 FDIV	V1.2D, V3.2D, V7.2D

  (175) 0x42dba4 BSL	V18.16B, V5.16B, V29.16B

  (175) 0x42dba8 FCMGT	V25.2D, V0.2D, #0.0000000

  (175) 0x42dbac FMINNM	V27.2D, V24.2D, V17.2D

  (175) 0x42dbb0 FSUB	V23.2D, V29.2D, V1.2D

  (175) 0x42dbb4 FMUL	V4.2D, V16.2D, V22.2D

  (175) 0x42dbb8 ORR	V22.16B, V20.16B, V20.16B

  (175) 0x42dbbc FCMGT	V0.2D, V28.2D, #0.0000000

  (175) 0x42dbc0 FMUL	V28.2D, V27.2D, V18.2D

  (175) 0x42dbc4 FMLA	V22.2D, V4.2D, V19.2D

  (175) 0x42dbc8 ORR	V19.16B, V21.16B, V21.16B

  (175) 0x42dbcc FMLA	V19.2D, V23.2D, V28.2D

  (175) 0x42dbd0 BSL	V25.16B, V22.16B, V20.16B

  (175) 0x42dbd4 FMUL	V30.2D, V30.2D, V25.2D

  (175) 0x42dbd8 BSL	V0.16B, V19.16B, V21.16B

  (175) 0x42dbdc FMUL	V31.2D, V31.2D, V0.2D

  (175) 0x42dbe0 STR	Q30, [X17, X11]

  (175) 0x42dbe4 ADD	X11, X11, #32

  (175) 0x42dbe8 STR	Q31, [X17, X12]

  (175) 0x42dbec ADD	X12, X12, #32

  (175) 0x42dbf0 CMP	X11, X24

  (175) 0x42dbf4 B.NE	42d868

0x42dbf8 LDR	W1, [SP, #200]

0x42dbfc LDP	X15, X22, [SP, #208]

0x42dc00 LDP	X10, X27, [SP, #224]

0x42dc04 AND	W8, W1, #0xfffffffc

0x42dc08 LDP	X14, X13, [SP, #240]

0x42dc0c LDP	X18, X28, [SP, #256]

0x42dc10 LDP	X4, X6, [SP, #272]

0x42dc14 LDP	X9, X3, [SP, #288]

0x42dc18 LDR	W26, [SP, #192]

0x42dc1c ADD	W7, W8, W26

0x42dc20 ANDS	XZR, X1, #0x3

0x42dc24 B.EQ	42dfcc

0x42dc28 SUB	W1, W1, W8

0x42dc2c CMP	W1, #1

0x42dc30 B.EQ	42de78

0x42dc34 FMOV	S2, W7

0x42dc38 SBFM	X2, X26, #0, #31

0x42dc3c ADD	W24, W7, #1

0x42dc40 ADD	X20, X18, X2

0x42dc44 MVNI	V20.2S, #0

0x42dc48 LDR	D23, [SP, #328]

0x42dc4c ADD	X0, X20, X8

0x42dc50 MOVI	V26.2S, #1

0x42dc54 MVNI	V24.2S, #1

0x42dc58 UBFM	X26, X0, #61, #60

0x42dc5c ADD	X17, X2, X8

0x42dc60 ADD	X21, X9, X30,LSL #3

0x42dc64 UBFM	X11, X17, #61, #60

0x42dc68 LDR	X17, [SP, #176]

0x42dc6c ADD	X12, X4, X6,LSL #3

0x42dc70 ADD	X19, X5, X3,LSL #3

0x42dc74 LDR	Q17, [X22, X26]

0x42dc78 LDR	Q18, [X16, X11]

0x42dc7c MOV	V2.S[1], W24

0x42dc80 FCMGT	V16.2D, V17.2D, #0.0000000

0x42dc84 FABS	V19.2D, V17.2D

0x42dc88 ADD	V21.2S, V2.2S, V20.2S

0x42dc8c SSHLL	V25.2D, V2.2S, #32

0x42dc90 ORR	V1.16B, V16.16B, V16.16B

0x42dc94 ADD	V7.2S, V2.2S, V26.2S

0x42dc98 ADD	V3.2S, V2.2S, V24.2S

0x42dc9c SSHLL	V0.2D, V21.2S, #32

0x42dca0 SMIN	V22.2S, V7.2S, V23.2S

0x42dca4 SSHLL	V27.2D, V3.2S, #32

0x42dca8 BSL	V1.16B, V0.16B, V25.16B

0x42dcac BIF	V25.16B, V0.16B, V16.16B

0x42dcb0 SSHLL	V30.2D, V22.2S, #32

0x42dcb4 FMOV	X20, D1

0x42dcb8 MOV	D4, V1.D[1]

0x42dcbc MOV	D28, V25.D[1]

0x42dcc0 FMOV	X0, D25

0x42dcc4 BIF	V27.16B, V30.16B, V16.16B

0x42dcc8 BSL	V16.16B, V0.16B, V30.16B

0x42dccc FMOV	X24, D28

0x42dcd0 MOV	D20, V27.D[1]

0x42dcd4 UBFM	X11, X20, #61, #60

0x42dcd8 ADD	X20, X17, X2

0x42dcdc FMOV	X17, D4

0x42dce0 ADD	X2, X23, X2

0x42dce4 LDR	D31, [X21, X11]

0x42dce8 LDR	D2, [X11, X12]

0x42dcec UBFM	X26, X24, #61, #60

0x42dcf0 ADD	X24, X20, X8

0x42dcf4 ADD	X8, X2, X8

0x42dcf8 UBFM	X20, X24, #61, #60

0x42dcfc UBFM	X2, X8, #61, #60

0x42dd00 UBFM	X8, X0, #61, #60

0x42dd04 UBFM	X17, X17, #61, #60

0x42dd08 FMOV	X0, D27

0x42dd0c STR	X2, [SP, #192]

0x42dd10 ADD	X2, SP, #200

0x42dd14 LDR	D21, [X12, X8]

0x42dd18 ST1	{V16.D[1]}, [X2]

0x42dd1c ADD	X2, X21, X17

0x42dd20 FMOV	X24, D20

0x42dd24 LD1	{V31.D[1]}, [X2]

0x42dd28 UBFM	X0, X0, #61, #60

0x42dd2c FMOV	X2, D16

0x42dd30 LDR	D26, [X12, X0]

0x42dd34 UBFM	X24, X24, #61, #60

0x42dd38 LDR	D7, [X16, X2,LSL #3]

0x42dd3c ADD	X2, X17, X12

0x42dd40 FDIV	V25.2D, V19.2D, V31.2D

0x42dd44 LD1	{V2.D[1]}, [X2]

0x42dd48 ADD	X2, X12, X26

0x42dd4c LD1	{V21.D[1]}, [X2]

0x42dd50 FADD	V16.2D, V25.2D, V29.2D

0x42dd54 LDR	X2, [SP, #200]

0x42dd58 FSUB	V0.2D, V15.2D, V25.2D

0x42dd5c FSUB	V27.2D, V29.2D, V25.2D

0x42dd60 LDR	D24, [X16, X2,LSL #3]

0x42dd64 ADD	X2, X12, X24

0x42dd68 LD1	{V26.D[1]}, [X2]

0x42dd6c FSUB	V3.2D, V21.2D, V2.2D

0x42dd70 LDR	X2, [SP, #168]

0x42dd74 MOV	V7.D[1], V24.D[0]

0x42dd78 FABS	V1.2D, V3.2D

0x42dd7c FDIV	V18.2D, V18.2D, V7.2D

0x42dd80 FSUB	V28.2D, V2.2D, V26.2D

0x42dd84 FCMLE	V4.2D, V3.2D, #0.0000000

0x42dd88 FMUL	V23.2D, V0.2D, V1.2D

0x42dd8c FMUL	V7.2D, V18.2D, V16.2D

0x42dd90 FABS	V22.2D, V28.2D

0x42dd94 ORR	V30.16B, V4.16B, V4.16B

0x42dd98 FMUL	V19.2D, V28.2D, V3.2D

0x42dd9c ORR	V3.16B, V2.16B, V2.16B

0x42dda0 FMLA	V23.2D, V7.2D, V22.2D

0x42dda4 FMINNM	V20.2D, V22.2D, V1.2D

0x42dda8 BSL	V30.16B, V5.16B, V29.16B

0x42ddac FCMGT	V26.2D, V19.2D, #0.0000000

0x42ddb0 FMUL	V21.2D, V27.2D, V30.2D

0x42ddb4 FMUL	V31.2D, V23.2D, V6.2D

0x42ddb8 FMINNM	V25.2D, V31.2D, V20.2D

0x42ddbc FMLA	V3.2D, V21.2D, V25.2D

0x42ddc0 BSL	V26.16B, V3.16B, V2.16B

0x42ddc4 FMUL	V17.2D, V17.2D, V26.2D

0x42ddc8 STR	Q17, [X2, X20]

0x42ddcc FABS	V2.2D, V17.2D

0x42ddd0 LDR	D16, [X11, X19]

0x42ddd4 LDR	D1, [X26, X19]

0x42ddd8 ADD	X26, X17, X19

0x42dddc LDR	D23, [X8, X19]

0x42dde0 LD1	{V16.D[1]}, [X26]

0x42dde4 LDR	D24, [X24, X19]

0x42dde8 LDR	D4, [X0, X19]

0x42ddec MOV	V23.D[1], V1.D[0]

0x42ddf0 LDR	D28, [X17, X12]

0x42ddf4 LDR	D27, [X11, X12]

0x42ddf8 FSUB	V18.2D, V23.2D, V16.2D

0x42ddfc MOV	V4.D[1], V24.D[0]

0x42de00 LDR	D20, [X21, X11]

0x42de04 LDR	D22, [X21, X17]

0x42de08 LDP	X21, X12, [SP, #184]

0x42de0c FSUB	V30.2D, V16.2D, V4.2D

0x42de10 FABS	V19.2D, V18.2D

0x42de14 MOV	V27.D[1], V28.D[0]

0x42de18 FCMLE	V21.2D, V18.2D, #0.0000000

0x42de1c ORR	V28.16B, V16.16B, V16.16B

0x42de20 MOV	V20.D[1], V22.D[0]

0x42de24 FMUL	V0.2D, V0.2D, V19.2D

0x42de28 FABS	V31.2D, V30.2D

0x42de2c FMUL	V3.2D, V30.2D, V18.2D

0x42de30 FMUL	V26.2D, V27.2D, V20.2D

0x42de34 ORR	V25.16B, V21.16B, V21.16B

0x42de38 FMLA	V0.2D, V7.2D, V31.2D

0x42de3c FDIV	V7.2D, V2.2D, V26.2D

0x42de40 FMINNM	V2.2D, V31.2D, V19.2D

0x42de44 BSL	V25.16B, V5.16B, V29.16B

0x42de48 FCMGT	V1.2D, V3.2D, #0.0000000

0x42de4c FSUB	V4.2D, V29.2D, V7.2D

0x42de50 FMUL	V24.2D, V0.2D, V6.2D

0x42de54 FMINNM	V23.2D, V24.2D, V2.2D

0x42de58 FMUL	V27.2D, V23.2D, V25.2D

0x42de5c FMLA	V28.2D, V27.2D, V4.2D

0x42de60 BSL	V1.16B, V28.16B, V16.16B

0x42de64 FMUL	V17.2D, V17.2D, V1.2D

0x42de68 STR	Q17, [X21, X12]

0x42de6c TBZ	W1, #0, 42dfcc

0x42de70 AND	W1, W1, #0xfffffffe

0x42de74 ADD	W7, W7, W1

0x42de78 SBFM	X19, X7, #0, #31

0x42de7c SUB	W11, W7, #1

0x42de80 ADD	X18, X18, X19

0x42de84 LDR	D16, [X22, X18,LSL #3]

0x42de88 FCMPE	D16, #0

0x42de8c B.LS	42e008

0x42de90 SBFM	X8, X11, #0, #31

0x42de94 SUB	W2, W7, #2

0x42de98 SBFM	X26, X2, #0, #31

0x42de9c ORR	X24, XZR, X8

0x42dea0 ORR	X20, XZR, X19

0x42dea4 ADD	X30, X30, X8

0x42dea8 FABS	D18, D16

0x42deac ADD	X21, X6, X8

0x42deb0 UBFM	X1, X30, #61, #60

0x42deb4 LDR	D20, [X16, X24,LSL #3]

0x42deb8 ADD	X12, X6, X20

0x42debc UBFM	X11, X21, #61, #60

0x42dec0 ADD	X6, X6, X26

0x42dec4 FMOV	D1, #2.0000000

0x42dec8 LDR	D22, [X9, X1]

0x42decc LDR	D19, [X16, X19,LSL #3]

0x42ded0 LDR	D0, [X4, X11]

0x42ded4 FDIV	D30, D18, D22

0x42ded8 LDR	D21, [X4, X12,LSL #3]

0x42dedc LDR	D3, [X4, X6,LSL #3]

0x42dee0 FDIV	D26, D19, D20

0x42dee4 FSUB	D31, D21, S0

0x42dee8 FSUB	D7, D0, S3

0x42deec FCMPE	D31, #0

0x42def0 FMUL	D2, D7, D31

0x42def4 FADD	D25, D30, D9

0x42def8 FSUB	D4, D1, S30

0x42defc FCSEL	D24, D8, D9, #9

0x42df00 FCMPE	D2, #0

0x42df04 FMUL	D17, D26, D25

0x42df08 B.LS	42df38

0x42df0c FABS	D28, D31

0x42df10 FABS	D27, D7

0x42df14 LDR	D19, [SP, #336]

0x42df18 FSUB	D18, D9, S30

0x42df1c FMINNM	D23, D27, D28

0x42df20 FMUL	D20, D28, D4

0x42df24 FMADD	D22, D27, D17, D20

0x42df28 FMUL	D30, D22, D19

0x42df2c FMINNM	D21, D30, D23

0x42df30 FMUL	D3, D21, D18

0x42df34 FMADD	D0, D24, D3, D0

0x42df38 ADD	X18, X3, X20

0x42df3c ADD	X16, X3, X8

0x42df40 FMUL	D16, D16, D0

0x42df44 ADD	X7, X3, X26

0x42df48 LDP	X3, X22, [SP, #168]

0x42df4c ADD	X20, X22, X19

0x42df50 STR	D16, [X3, X20,LSL #3]

0x42df54 LDR	D0, [X5, X16,LSL #3]

0x42df58 LDR	D26, [X5, X18,LSL #3]

0x42df5c LDR	D7, [X5, X7,LSL #3]

0x42df60 FSUB	D31, D26, S0

0x42df64 FSUB	D2, D0, S7

0x42df68 FCMPE	D31, #0

0x42df6c FMUL	D25, D2, D31

0x42df70 FCSEL	D1, D8, D9, #9

0x42df74 FCMPE	D25, #0

0x42df78 B.LS	42dfbc

0x42df7c LDR	D24, [X4, X11]

0x42df80 FABS	D18, D16

0x42df84 FABS	D23, D31

0x42df88 FABS	D27, D2

0x42df8c FMINNM	D22, D27, D23

0x42df90 LDR	D20, [X9, X1]

0x42df94 FMUL	D4, D23, D4

0x42df98 LDR	D21, [SP, #336]

0x42df9c FMUL	D19, D24, D20

0x42dfa0 FMADD	D17, D27, D17, D4

0x42dfa4 FDIV	D30, D18, D19

0x42dfa8 FMUL	D3, D17, D21

0x42dfac FMINNM	D26, D3, D22

0x42dfb0 FSUB	D7, D9, S30

0x42dfb4 FMUL	D31, D7, D26

0x42dfb8 FMADD	D0, D1, D31, D0

0x42dfbc FMUL	D16, D0, D16

0x42dfc0 ADD	X5, X23, X19

0x42dfc4 LDR	X23, [SP, #184]

0x42dfc8 STR	D16, [X23, X5,LSL #3]

0x42dfcc LDR	W4, [SP, #304]

0x42dfd0 ADD	X25, X25, #1

0x42dfd4 LDR	W9, [SP, #344]

0x42dfd8 CMP	W9, W25

0x42dfdc B.LE	42e02c

0x42dfe0 LDR	W8, [SP, #316]

0x42dfe4 LDR	W26, [SP, #308]

0x42dfe8 LDR	W19, [SP, #312]

0x42dfec SUB	W7, W8, W4

0x42dff0 B	42d780

0x42e008 LDR	W0, [SP, #348]

0x42e00c ADD	W22, W7, #1

0x42e010 SBFM	X20, X11, #0, #31

0x42e014 ORR	X8, XZR, X19

0x42e018 CMP	W22, W0

0x42e01c CSEL	W17, W22, W0, #13

0x42e020 SBFM	X24, X17, #0, #31

0x42e024 ORR	X26, XZR, X24

0x42e028 B	42dea4

0x42e058 MOVZ	X8, #0

0x42e05c ORR	W7, WZR, W26

0x42e060 B	42dc28

/usr/include/c++/14/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 67 - 110

--------------------------------------------------------------------------------

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.89
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	3.10 - 1.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	micro-operation queue,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	stl_algobase.h:238-238,advec_cell.cpp:67-67,advec_cell.cpp:71-72,advec_cell.cpp:77-93,advec_cell.cpp:97-106,advec_cell.cpp:110-110,context.h:46-46,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.63
CQA cycles if no scalar integer	21.50
CQA cycles if FP arith vectorized	22.75 - 26.22
CQA cycles if fully vectorized	13.12 - 26.22
Front-end cycles	40.63
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	24.00
P3 cycles	24.00
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	34.75
P7 cycles	34.75
P8 cycles	34.75
P9 cycles	34.75
P10 cycles	29.83
P11 cycles	29.50
P12 cycles	29.67
P13 cycles	6.00
P14 cycles	6.00
DIV/SQRT cycles	15.74 - 31.47
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	325.00
Nb uops	325.00
Nb loads	NA
Nb stores	17.00
Nb stack references	36.00
FLOP/cycle	2.29
Nb FLOP add-sub	24.00
Nb FLOP mul	36.00
Nb FLOP fma	12.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.19
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	25.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.90
Vectorization ratio load	7.89
Vectorization ratio store	11.76
Vectorization ratio mul	48.00
Vectorization ratio add_sub	52.17
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	50.00
Vectorization ratio other	43.59
Vector-efficiency ratio all	32.95
Vector-efficiency ratio load	26.97
Vector-efficiency ratio store	36.03
Vector-efficiency ratio mul	37.00
Vector-efficiency ratio add_sub	34.24
Vector-efficiency ratio fma	37.50
Vector-efficiency ratio div_sqrt	37.50
Vector-efficiency ratio other	32.69

Metric	Value
CQA speedup if no scalar integer	1.89
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	3.10 - 1.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	micro-operation queue,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	stl_algobase.h:238-238,advec_cell.cpp:67-67,advec_cell.cpp:71-72,advec_cell.cpp:77-93,advec_cell.cpp:97-106,advec_cell.cpp:110-110,context.h:46-46,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	40.63
CQA cycles if no scalar integer	21.50
CQA cycles if FP arith vectorized	22.75 - 26.22
CQA cycles if fully vectorized	13.12 - 26.22
Front-end cycles	40.63
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	24.00
P3 cycles	24.00
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	34.75
P7 cycles	34.75
P8 cycles	34.75
P9 cycles	34.75
P10 cycles	29.83
P11 cycles	29.50
P12 cycles	29.67
P13 cycles	6.00
P14 cycles	6.00
DIV/SQRT cycles	15.74 - 31.47
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	325.00
Nb uops	325.00
Nb loads	NA
Nb stores	17.00
Nb stack references	36.00
FLOP/cycle	2.29
Nb FLOP add-sub	24.00
Nb FLOP mul	36.00
Nb FLOP fma	12.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.19
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	25.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.90
Vectorization ratio load	7.89
Vectorization ratio store	11.76
Vectorization ratio mul	48.00
Vectorization ratio add_sub	52.17
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	50.00
Vectorization ratio other	43.59
Vector-efficiency ratio all	32.95
Vector-efficiency ratio load	26.97
Vector-efficiency ratio store	36.03
Vector-efficiency ratio mul	37.00
Vector-efficiency ratio add_sub	34.24
Vector-efficiency ratio fma	37.50
Vector-efficiency ratio div_sqrt	37.50
Vector-efficiency ratio other	32.69

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:67-110
Module	exec

The loop is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:67-110
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 36 paths individually, rerun with max-paths=36
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 36 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.63 to 21.50 cycles (1.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 32% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 40.63 to 26.22 cycles (1.55x speedup).

Details

35% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
11% of VPU stores are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
48% of VPU multiply instructions are used in vector version.
50% of VPU fused multiply-add instructions are used in vector version.
50% of VPU divide and square root instructions are used in vector version.
43% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 93 FP arithmetical operations:

36: addition or subtraction (12 inside FMA instructions)
48: multiply (12 inside FMA instructions)
9: divide

The binary loop is loading 64 bytes. The binary loop is storing 25 bytes.

Arithmetic intensity

Arithmetic intensity is 1.04 FP operations per loaded or stored byte.

General properties

nb instructions	325
nb uops	325
loop length	1300
used w registers	17
used x registers	31
used b registers	0
used h registers	0
used s registers	6
used d registers	23
used q registers	3
used v registers	25
used z registers	0
nb stack references	36
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	40.63 cycles
front end	40.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	24.00	24.00	24.00	24.00	34.75	34.75	34.75	34.75	29.83	29.50	29.67	6.00	6.00
cycles	6.00	6.00	24.00	24.00	24.00	24.00	34.75	34.75	34.75	34.75	29.83	29.50	29.67	6.00	6.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.74-31.47

Cycles summary

Front-end	40.63
Dispatch	34.75
DIV/SQRT	15.74-31.47
Overall L1	40.63

Vectorization ratios

INT

all	28%
load	7%
store	11%
mul	0%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
other	51%

all	44%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	36%

INT+FP

all	35%
load	7%
store	11%
mul	48%
add-sub	52%
fma	50%
div/sqrt	50%
other	43%

Vector efficiency ratios

INT

all	30%
load	26%
store	36%
mul	25%
add-sub	26%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	37%
add-sub	37%
fma	37%
div/sqrt	37%
other	33%

INT+FP

all	32%
load	26%
store	36%
mul	37%
add-sub	34%
fma	37%
div/sqrt	37%
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.63 cycles. At this rate:

1% of peak load performance is reached (1.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.62 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 40.63 to 34.75 cycles (1.17x speedup).

ASM code

In the binary file, the address of the loop is: 42d780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP W7, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W7, W19, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W4, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W4, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42dfd0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x984>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W21, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X23, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X24, X25, X19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X7, [X28, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X3, X25, X23	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X8, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X23, X25, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X11, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X30, X25, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X16, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X18, X25, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X6, X25, X20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X5, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X24, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LS 42e058 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0xa0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X12, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X24, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V2.4S, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
ADD X0, X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X8, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X8, <462814>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X23, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X22, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM W24, W1, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR Q0, [X8, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X17, X7, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X24, X24, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X9, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD X0, X4, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X15, X22, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X5, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X16, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X10, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD V2.4S, V2.4S, V0.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP X14, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X28, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X6, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X22, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
AND W8, W1, #0xfffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X14, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X18, X28, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X6, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W7, W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X1, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 42dfcc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, W1, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42de78 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x82c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S2, W7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
SBFM X2, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W24, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X18, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MVNI V20.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
LDR D23, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V26.2S, #1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MVNI V24.2S, #1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
UBFM X26, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X9, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X4, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X5, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q17, [X22, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q18, [X16, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOV V2.S[1], W24	1	0	0	0	0	1	0	0.25	0.25	0.25	0.25	0	0	0	0	0	5	1	scal (12.5%)
FCMGT V16.2D, V17.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FABS V19.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V21.2S, V2.2S, V20.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
SSHLL V25.2D, V2.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (25.0%)
ORR V1.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V7.2S, V2.2S, V26.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
ADD V3.2S, V2.2S, V24.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
SSHLL V0.2D, V21.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (25.0%)
SMIN V22.2S, V7.2S, V23.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
SSHLL V27.2D, V3.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (25.0%)
BSL V1.16B, V0.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
BIF V25.16B, V0.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
SSHLL V30.2D, V22.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (25.0%)
FMOV X20, D1	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOV D4, V1.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOV D28, V25.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV X0, D25	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
BIF V27.16B, V30.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
BSL V16.16B, V0.16B, V30.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMOV X24, D28	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOV D20, V27.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UBFM X11, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X17, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X17, D4	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X2, X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X21, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D2, [X11, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
UBFM X26, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X20, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X8, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X17, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X0, D27	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X2, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, SP, #200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X12, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ST1 {V16.D[1]}, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	4	0.50	scal (25.0%)
ADD X2, X21, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X24, D20	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
LD1 {V31.D[1]}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
UBFM X0, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X2, D16	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR D26, [X12, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X2, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDIV V25.2D, V19.2D, V31.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LD1 {V2.D[1]}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
ADD X2, X12, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V21.D[1]}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
FADD V16.2D, V25.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X2, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FSUB V0.2D, V15.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FSUB V27.2D, V29.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR D24, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X2, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V26.D[1]}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
FSUB V3.2D, V21.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOV V7.D[1], V24.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FABS V1.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FDIV V18.2D, V18.2D, V7.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FSUB V28.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FCMLE V4.2D, V3.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V23.2D, V0.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V7.2D, V18.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FABS V22.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ORR V30.16B, V4.16B, V4.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V19.2D, V28.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
ORR V3.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMLA V23.2D, V7.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
FMINNM V20.2D, V22.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
BSL V30.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FCMGT V26.2D, V19.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V21.2D, V27.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V31.2D, V23.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMINNM V25.2D, V31.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMLA V3.2D, V21.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
BSL V26.16B, V3.16B, V2.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V17.2D, V17.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q17, [X2, X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FABS V2.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR D16, [X11, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X26, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X26, X17, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X8, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LD1 {V16.D[1]}, [X26]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
LDR D24, [X24, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D4, [X0, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
MOV V23.D[1], V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D28, [X17, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D27, [X11, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FSUB V18.2D, V23.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
MOV V4.D[1], V24.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D20, [X21, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D22, [X21, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X21, X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FSUB V30.2D, V16.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FABS V19.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
MOV V27.D[1], V28.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMLE V21.2D, V18.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ORR V28.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
MOV V20.D[1], V22.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL V0.2D, V0.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FABS V31.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V3.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V26.2D, V27.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
ORR V25.16B, V21.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMLA V0.2D, V7.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
FDIV V7.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMINNM V2.2D, V31.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
BSL V25.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FCMGT V1.2D, V3.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FSUB V4.2D, V29.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V24.2D, V0.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMINNM V23.2D, V24.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V27.2D, V23.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMLA V28.2D, V27.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
BSL V1.16B, V28.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V17.2D, V17.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q17, [X21, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
TBZ W1, #0, 42dfcc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W1, W1, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W7, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X19, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W11, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D16, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42e008 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X8, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W2, W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X26, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FABS D18, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X21, X6, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X16, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X12, X6, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X6, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D1, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D22, [X9, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D19, [X16, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [X4, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FDIV D30, D18, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D21, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D3, [X4, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FDIV D26, D19, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D31, D21, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D7, D0, S3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D2, D7, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D25, D30, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D4, D1, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCSEL D24, D8, D9, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D17, D26, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
B.LS 42df38 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x8ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FABS D28, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FABS D27, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FSUB D18, D9, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMINNM D23, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D20, D28, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D22, D27, D17, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMUL D30, D22, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMINNM D21, D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D3, D21, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D0, D24, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
ADD X18, X3, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D16, D16, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
ADD X7, X3, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X3, X22, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X20, X22, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D16, [X3, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X5, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D26, [X5, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D7, [X5, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FSUB D31, D26, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D2, D0, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D25, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCSEL D1, D8, D9, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMPE D25, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42dfbc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D24, [X4, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FABS D18, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FABS D23, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FABS D27, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMINNM D22, D27, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D20, [X9, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D4, D23, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D19, D24, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D17, D27, D17, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FDIV D30, D18, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D3, D17, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMINNM D26, D3, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D7, D9, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D31, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D0, D1, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMUL D16, D0, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
ADD X5, X23, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X23, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D16, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR W4, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W9, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W9, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 42e02c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #316]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W26, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W19, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W7, W8, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42d780 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [SP, #348]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X20, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W17, W22, W0, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X24, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42dea4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W7, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42dc28 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:67-110
Module	exec

The loop is defined in:

/usr/include/c++/14/bits/stl_algobase.h:238
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:67-110
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 36 paths individually, rerun with max-paths=36
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

35% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
11% of VPU stores are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
48% of VPU multiply instructions are used in vector version.
50% of VPU fused multiply-add instructions are used in vector version.
50% of VPU divide and square root instructions are used in vector version.
43% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 93 FP arithmetical operations:

36: addition or subtraction (12 inside FMA instructions)
48: multiply (12 inside FMA instructions)
9: divide

The binary loop is loading 64 bytes. The binary loop is storing 25 bytes.

Arithmetic intensity

Arithmetic intensity is 1.04 FP operations per loaded or stored byte.

General properties

nb instructions	325
nb uops	325
loop length	1300
used w registers	17
used x registers	31
used b registers	0
used h registers	0
used s registers	6
used d registers	23
used q registers	3
used v registers	25
used z registers	0
nb stack references	36
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	40.63 cycles
front end	40.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	24.00	24.00	24.00	24.00	34.75	34.75	34.75	34.75	29.83	29.50	29.67	6.00	6.00
cycles	6.00	6.00	24.00	24.00	24.00	24.00	34.75	34.75	34.75	34.75	29.83	29.50	29.67	6.00	6.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.74-31.47

Cycles summary

Front-end	40.63
Dispatch	34.75
DIV/SQRT	15.74-31.47
Overall L1	40.63

Vectorization ratios

INT

all	28%
load	7%
store	11%
mul	0%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
other	51%

all	44%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	36%

INT+FP

all	35%
load	7%
store	11%
mul	48%
add-sub	52%
fma	50%
div/sqrt	50%
other	43%

Vector efficiency ratios

INT

all	30%
load	26%
store	36%
mul	25%
add-sub	26%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	37%
add-sub	37%
fma	37%
div/sqrt	37%
other	33%

INT+FP

all	32%
load	26%
store	36%
mul	37%
add-sub	34%
fma	37%
div/sqrt	37%
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.63 cycles. At this rate:

1% of peak load performance is reached (1.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.62 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 42d780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP W7, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W7, W19, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W4, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W4, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42dfd0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x984>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W21, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X23, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X24, X25, X19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X7, [X28, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X3, X25, X23	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X8, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X23, X25, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X11, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X30, X25, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X16, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X18, X25, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X6, X25, X20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X5, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X24, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LS 42e058 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0xa0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X12, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X24, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V2.4S, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
ADD X0, X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X8, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X8, <462814>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X23, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X22, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM W24, W1, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR Q0, [X8, #576]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X17, X7, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X24, X24, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X9, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD X0, X4, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X15, X22, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X5, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X16, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X10, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD V2.4S, V2.4S, V0.4S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP X14, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X28, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X6, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X22, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
AND W8, W1, #0xfffffffc	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X14, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X18, X28, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X6, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X9, X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W7, W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X1, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 42dfcc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W1, W1, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42de78 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x82c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV S2, W7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
SBFM X2, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W24, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X18, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MVNI V20.2S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
LDR D23, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V26.2S, #1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MVNI V24.2S, #1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
UBFM X26, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X9, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X4, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X5, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q17, [X22, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR Q18, [X16, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MOV V2.S[1], W24	1	0	0	0	0	1	0	0.25	0.25	0.25	0.25	0	0	0	0	0	5	1	scal (12.5%)
FCMGT V16.2D, V17.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FABS V19.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V21.2S, V2.2S, V20.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
SSHLL V25.2D, V2.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (25.0%)
ORR V1.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V7.2S, V2.2S, V26.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
ADD V3.2S, V2.2S, V24.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
SSHLL V0.2D, V21.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (25.0%)
SMIN V22.2S, V7.2S, V23.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
SSHLL V27.2D, V3.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (25.0%)
BSL V1.16B, V0.16B, V25.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
BIF V25.16B, V0.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
SSHLL V30.2D, V22.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (25.0%)
FMOV X20, D1	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOV D4, V1.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOV D28, V25.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV X0, D25	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
BIF V27.16B, V30.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
BSL V16.16B, V0.16B, V30.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMOV X24, D28	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOV D20, V27.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UBFM X11, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X17, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X17, D4	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X2, X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X21, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D2, [X11, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
UBFM X26, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X20, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X8, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X17, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X0, D27	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X2, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, SP, #200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X12, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ST1 {V16.D[1]}, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	4	0.50	scal (25.0%)
ADD X2, X21, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X24, D20	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
LD1 {V31.D[1]}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
UBFM X0, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X2, D16	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR D26, [X12, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X2, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDIV V25.2D, V19.2D, V31.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LD1 {V2.D[1]}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
ADD X2, X12, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V21.D[1]}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
FADD V16.2D, V25.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X2, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FSUB V0.2D, V15.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FSUB V27.2D, V29.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR D24, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X2, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V26.D[1]}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
FSUB V3.2D, V21.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOV V7.D[1], V24.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FABS V1.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FDIV V18.2D, V18.2D, V7.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FSUB V28.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FCMLE V4.2D, V3.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V23.2D, V0.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V7.2D, V18.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FABS V22.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ORR V30.16B, V4.16B, V4.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V19.2D, V28.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
ORR V3.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMLA V23.2D, V7.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
FMINNM V20.2D, V22.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
BSL V30.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FCMGT V26.2D, V19.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V21.2D, V27.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V31.2D, V23.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMINNM V25.2D, V31.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMLA V3.2D, V21.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
BSL V26.16B, V3.16B, V2.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V17.2D, V17.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q17, [X2, X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FABS V2.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR D16, [X11, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X26, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X26, X17, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X8, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LD1 {V16.D[1]}, [X26]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (25.0%)
LDR D24, [X24, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D4, [X0, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
MOV V23.D[1], V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D28, [X17, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D27, [X11, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FSUB V18.2D, V23.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
MOV V4.D[1], V24.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D20, [X21, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D22, [X21, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X21, X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FSUB V30.2D, V16.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FABS V19.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
MOV V27.D[1], V28.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMLE V21.2D, V18.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ORR V28.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
MOV V20.D[1], V22.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL V0.2D, V0.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FABS V31.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V3.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V26.2D, V27.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
ORR V25.16B, V21.16B, V21.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMLA V0.2D, V7.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
FDIV V7.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMINNM V2.2D, V31.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
BSL V25.16B, V5.16B, V29.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FCMGT V1.2D, V3.2D, #0.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FSUB V4.2D, V29.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V24.2D, V0.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMINNM V23.2D, V24.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V27.2D, V23.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMLA V28.2D, V27.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (50.0%)
BSL V1.16B, V28.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
FMUL V17.2D, V17.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q17, [X21, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
TBZ W1, #0, 42dfcc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W1, W1, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W7, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X19, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W11, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D16, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42e008 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X8, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W2, W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X26, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FABS D18, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X21, X6, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X16, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X12, X6, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X6, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D1, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D22, [X9, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D19, [X16, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [X4, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FDIV D30, D18, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D21, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D3, [X4, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FDIV D26, D19, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D31, D21, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D7, D0, S3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D2, D7, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D25, D30, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D4, D1, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCSEL D24, D8, D9, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D17, D26, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
B.LS 42df38 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x8ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FABS D28, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FABS D27, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FSUB D18, D9, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMINNM D23, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D20, D28, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D22, D27, D17, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMUL D30, D22, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMINNM D21, D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D3, D21, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D0, D24, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
ADD X18, X3, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D16, D16, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
ADD X7, X3, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X3, X22, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X20, X22, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D16, [X3, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X5, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D26, [X5, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D7, [X5, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FSUB D31, D26, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D2, D0, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D25, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCSEL D1, D8, D9, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMPE D25, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 42dfbc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D24, [X4, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FABS D18, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FABS D23, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FABS D27, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMINNM D22, D27, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D20, [X9, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D4, D23, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D19, D24, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D17, D27, D17, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FDIV D30, D18, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D3, D17, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMINNM D26, D3, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D7, D9, S30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D31, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D0, D1, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMUL D16, D0, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
ADD X5, X23, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X23, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D16, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR W4, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W9, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W9, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 42e02c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #316]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W26, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W19, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W7, W8, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42d780 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [SP, #348]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X20, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W17, W22, W0, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X24, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42dea4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W7, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42dc28 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
		1	0			1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1
1x2	1	1	1	2	0.079999998211861	0.0053509101271629
1x4
1x8	4	1	1	8	0.03999999910593	0.0076044392772019
1x16	3	1	1	16	0.025000000372529	0.0027311709709466
1x24	1	1	1	24	0.02000000141561	0.0005486358422786
1x32	5	1	1	32	0.015000000596046	0.0016729029593989
1x40	19	1	1	40	0.030000001192093	0.0071455859579146
1x48	32	1	1	48	0.040000002831221	0.010922556743026
1x56	42	1	1	56	0.059999998658895	0.013826658949256
1x64	47	1	1	64	0.040000002831221	0.013313830830157

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency