OV - exec - Loop 205

	Loop Id: 205	Module: exec	Source: advec_mom.cpp:182-211 [...]	Coverage: NA%

0x4310cc LDR	X2, [X25]

0x4310d0 SBFM	X0, X15, #0, #31

0x4310d4 SUB	W13, W12, #1

0x4310d8 ADD	X6, X0, #1

0x4310dc LDR	X15, [X23]

0x4310e0 ADD	X13, X6, X13

0x4310e4 LDR	X19, [X3, #8]

0x4310e8 MUL	X20, X9, X2

0x4310ec LDR	X16, [X23, #16]

0x4310f0 MUL	X18, X9, X15

0x4310f4 LDR	X28, [X25, #16]

0x4310f8 ADD	X22, X19, X9,LSL #3

0x4310fc LDR	X12, [X26]

0x431100 ADD	X15, X16, X18,LSL #3

0x431104 LDR	X18, [X24]

0x431108 ADD	X16, X28, X20,LSL #3

0x43110c LDR	X21, [X24, #16]

0x431110 LDR	X8, [X26, #16]

0x431114 B	43111c

  (204) 0x431118 ADD	X6, X6, #1

  (204) 0x43111c LDR	D30, [X16, X0,LSL #3]

  (204) 0x431120 SBFM	X2, X7, #0, #31

  (204) 0x431124 ORR	X5, XZR, X11

  (204) 0x431128 ORR	X4, XZR, X9

  (204) 0x43112c ORR	W20, WZR, W7

  (204) 0x431130 FCMPE	D30, #0

  (204) 0x431134 B.GE	431148

  (204) 0x431138 SBFM	X2, X30, #0, #31

  (204) 0x43113c ORR	X5, XZR, X9

  (204) 0x431140 ORR	X4, XZR, X11

  (204) 0x431144 ORR	W20, WZR, W27

  (204) 0x431148 MADD	X28, X18, X4, X0

  (204) 0x43114c FABS	D27, D30

  (204) 0x431150 MADD	X5, X12, X5, X0

  (204) 0x431154 MADD	X2, X2, X12, X0

  (204) 0x431158 MADD	X4, X12, X4, X0

  (204) 0x43115c LDR	D29, [X8, X5,LSL #3]

  (204) 0x431160 LDR	D28, [X8, X4,LSL #3]

  (204) 0x431164 LDR	D31, [X8, X2,LSL #3]

  (204) 0x431168 FSUB	D1, D29, S28

  (204) 0x43116c FSUB	D0, D28, S31

  (204) 0x431170 FABS	D26, D1

  (204) 0x431174 FMUL	D2, D0, D1

  (204) 0x431178 FABS	D25, D0

  (204) 0x43117c FMINNM	D22, D25, D26

  (204) 0x431180 FCMPE	D2, #0

  (204) 0x431184 B.LS	4311d4

  (204) 0x431188 LDR	D3, [X21, X28,LSL #3]

  (204) 0x43118c FCMPE	D1, #0

  (204) 0x431190 LDR	D23, [X22]

  (204) 0x431194 LDR	D19, [X19, W20,SXTW #3]

  (204) 0x431198 FDIV	D4, D27, D3

  (204) 0x43119c FCSEL	D21, D16, D24, #9

  (204) 0x4311a0 FMUL	D0, D23, D18

  (204) 0x4311a4 FADD	D5, D4, D24

  (204) 0x4311a8 FSUB	D6, D17, S4

  (204) 0x4311ac FSUB	D7, D24, S4

  (204) 0x4311b0 FMUL	D20, D5, D25

  (204) 0x4311b4 FMUL	D27, D6, D26

  (204) 0x4311b8 FDIV	D29, D20, D19

  (204) 0x4311bc FDIV	D31, D27, D23

  (204) 0x4311c0 FADD	D1, D29, D31

  (204) 0x4311c4 FMUL	D25, D1, D0

  (204) 0x4311c8 FMINNM	D26, D25, D22

  (204) 0x4311cc FMUL	D22, D26, D7

  (204) 0x4311d0 FMADD	D28, D21, D22, D28

  (204) 0x4311d4 FMUL	D30, D30, D28

  (204) 0x4311d8 STR	D30, [X15, X0,LSL #3]

  (204) 0x4311dc ORR	X0, XZR, X6

  (204) 0x4311e0 CMP	X6, X13

  (204) 0x4311e4 B.NE	431118

0x4311e8 LDR	W6, [SP, #104]

0x4311ec ADD	W30, W30, #1

0x4311f0 ADD	W7, W7, #1

0x4311f4 ADD	X11, X11, #1

0x4311f8 ORR	X9, XZR, X10

0x4311fc CMP	W6, W10

0x431200 B.LE	431250

0x431204 SUB	W5, W1, W14

0x431208 ORR	W13, WZR, W14

0x43120c LDR	W15, [SP, #108]

0x431210 ORR	W14, WZR, W17

0x431214 ADD	X10, X10, #1

0x431218 CMP	W5, W14

0x43121c CSEL	W12, W5, W14, #9

0x431220 ADD	W14, W13, W12

0x431224 ADD	W27, W9, #1

0x431228 CMP	W13, W14

0x43122c B.CC	4310cc

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 182 - 211

--------------------------------------------------------------------------------

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	context.h:46-46,context.h:69-69,advec_mom.cpp:182-182,advec_mom.cpp:198-198,advec_mom.cpp:211-211
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.75
CQA cycles if no scalar integer	5.75
CQA cycles if FP arith vectorized	5.75
CQA cycles if fully vectorized	2.53
Front-end cycles	4.63
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	5.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.67
P11 cycles	3.67
P12 cycles	3.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.04
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.66
Vector-efficiency ratio load	22.73
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	20.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	context.h:46-46,context.h:69-69,advec_mom.cpp:182-182,advec_mom.cpp:198-198,advec_mom.cpp:211-211
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.75
CQA cycles if no scalar integer	5.75
CQA cycles if FP arith vectorized	5.75
CQA cycles if fully vectorized	2.53
Front-end cycles	4.63
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	5.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.67
P11 cycles	3.67
P12 cycles	3.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.04
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.66
Vector-efficiency ratio load	22.73
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	20.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	advec_mom.cpp:182-211
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:182-211

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.75 to 2.53 cycles (2.27x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 6 bytes.

General properties

nb instructions	37
nb uops	37
loop length	148
used w registers	14
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00
cycles	1.50	1.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Dispatch	5.75
Overall L1	5.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	23%
load	22%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.75 cycles. At this rate:

1% of peak load performance is reached (1.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 431204

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X2, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
SBFM X0, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (100.0%)
SUB W13, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X6, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR X15, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X13, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X19, [X3, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
MUL X20, X9, X2	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X16, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
MUL X18, X9, X15	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X28, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X22, X19, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR X12, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X15, X16, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR X18, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X16, X28, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR X21, [X24, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 43111c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR W6, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
ADD W30, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W6, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.LE 431250 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W1, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ORR W13, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR W15, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
ORR W14, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W5, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
CSEL W12, W5, W14, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W14, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD W27, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
CMP W13, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.CC 4310cc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	advec_mom.cpp:182-211
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:182-211

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 6 bytes.

General properties

nb instructions	37
nb uops	37
loop length	148
used w registers	14
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00
cycles	1.50	1.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Dispatch	5.75
Overall L1	5.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	23%
load	22%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.75 cycles. At this rate:

1% of peak load performance is reached (1.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 431204

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X2, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
SBFM X0, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (100.0%)
SUB W13, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X6, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR X15, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X13, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X19, [X3, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
MUL X20, X9, X2	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X16, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
MUL X18, X9, X15	1	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X28, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X22, X19, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR X12, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X15, X16, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR X18, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X16, X28, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR X21, [X24, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 43111c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR W6, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
ADD W30, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W6, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.LE 431250 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W1, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ORR W13, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR W15, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
ORR W14, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W5, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
CSEL W12, W5, W14, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W14, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD W27, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
CMP W13, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.CC 4310cc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
						1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1
1x2
1x4
1x8	2	1	1	8	0.025000000372529	0.0029247845523059
1x16	5	1	1	16	0.029999997466803	0.0044869240373373
1x24	18	1	1	24	0.050000000745058	0.012207148596644
1x32	25	1	1	32	0.044999998062849	0.012602535076439
1x40	26	1	1	40	0.044999998062849	0.012504775077105
1x48	26	1	1	48	0.03999999538064	0.0086104823276401
1x56	38	1	1	56	0.034999996423721	0.010198871605098
1x64	32	1	1	64	0.045000001788139	0.0087166773155332

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency