OV - exec - Loop 241

	Loop Id: 241	Module: exec	Source: generate_chunk.cpp:91-98 [...]	Coverage: 0.03%

0x4363cc ADD	X1, X0, #8

0x4363d0 LDR	D23, [X2]    [39]

0x4363d4 LDR	D22, [X6, X1]    [1]

0x4363d8 FCMPE	D23, D22

0x4363dc B.GT	436424

0x4363e0 LDR	D21, [X6, X0]    [1]

0x4363e4 LDR	X0, [X16, #8]    [38]

0x4363e8 LDR	D20, [X0, X5]    [36]

0x4363ec FCMPE	D21, D20

0x4363f0 B.GE	436424

0x4363f4 LDR	X23, [X9, #632]    [3]

0x4363f8 LDR	D19, [X8]    [2]

0x4363fc ADD	X22, X23, X11

0x436400 LDR	D18, [X22, #8]    [25]

0x436404 FCMPE	D19, D18

0x436408 B.GT	436424

0x43640c LDR	X18, [X19, #56]    [41]

0x436410 LDR	D31, [X23, X11]    [32]

0x436414 LDR	X17, [X18, #8]    [40]

0x436418 LDR	D30, [X17, X5]    [17]

0x43641c FCMPE	D31, D30

0x436420 B.MI	436804

0x436424 CMP	X4, X12

0x436428 B.EQ	436258

0x43642c ADD	X0, X1, #8

0x436430 LDR	D5, [X2]    [39]

0x436434 ADD	X17, X4, #1

0x436438 ORR	X10, XZR, X17

0x43643c LDR	D4, [X6, X0]    [1]

0x436440 FCMPE	D5, D4

0x436444 B.GT	436568

0x436448 LDR	D6, [X6, X1]    [1]

0x43644c LDR	X1, [X16, #8]    [38]

0x436450 LDR	D7, [X1, X5]    [37]

0x436454 FCMPE	D6, D7

0x436458 B.GE	436568

0x43645c LDR	X23, [X9, #632]    [3]

0x436460 LDR	D16, [X8]    [2]

0x436464 ADD	X22, X23, X11

0x436468 LDR	D17, [X22, #8]    [7]

0x43646c FCMPE	D16, D17

0x436470 B.GT	436568

0x436474 LDR	X18, [X19, #56]    [41]

0x436478 LDR	D22, [X23, X11]    [29]

0x43647c LDR	X25, [X18, #8]    [20]

0x436480 LDR	D23, [X25, X5]    [12]

0x436484 FCMPE	D22, D23

0x436488 B.GE	436568

0x43648c LDP	X23, X22, [X19]    [41]

0x436490 LDR	X1, [X9, #48]    [3]

0x436494 LDR	X25, [X22, #8]    [6]

0x436498 LDR	X24, [X9, #64]    [3]

0x43649c MADD	X18, X3, X1, X4

0x4364a0 LDR	X23, [X23, #8]    [28]

0x4364a4 LDR	D21, [X25, X5]    [11]

0x4364a8 LDR	X1, [X9]    [3]

0x4364ac LDR	X30, [X9, #168]    [3]

0x4364b0 STR	D21, [X24, X18,LSL #3]    [10]

0x4364b4 LDP	X24, X18, [X19, #16]    [41]

0x4364b8 MADD	X25, X3, X1, X4

0x4364bc LDR	D20, [X23, X5]    [27]

0x4364c0 LDR	X22, [X9, #16]    [3]

0x4364c4 LDR	X24, [X24, #8]    [9]

0x4364c8 LDR	X1, [X9, #216]    [3]

0x4364cc LDR	X23, [X9, #184]    [3]

0x4364d0 STR	D20, [X22, X25,LSL #3]    [5]

0x4364d4 LDR	X22, [X18, #8]    [19]

0x4364d8 MUL	X18, X30, X3

0x4364dc STR	X1, [SP, #96]    [15]

0x4364e0 LDR	D19, [X24, X5]    [8]

0x4364e4 ADD	X1, X18, X17

0x4364e8 ADD	X25, X18, X4

0x4364ec ADD	X30, X30, X18

0x4364f0 LDR	X18, [X9, #232]    [3]

0x4364f4 STR	X1, [SP, #104]    [15]

0x4364f8 LDR	X1, [SP, #96]    [15]

0x4364fc STR	D19, [X23, X25,LSL #3]    [26]

0x436500 ADD	X25, X30, X4

0x436504 ADD	X30, X30, X17

0x436508 LDR	D18, [X22, X5]    [4]

0x43650c STP	X25, X30, [SP, #112]    [15]

0x436510 MUL	X25, X1, X3

0x436514 ADD	X30, X25, X4

0x436518 ADD	X1, X1, X25

0x43651c ADD	X25, X25, X17

0x436520 ADD	X4, X1, X4

0x436524 STR	D18, [X18, X30,LSL #3]    [18]

0x436528 ADD	X1, X1, X17

0x43652c LDR	D31, [X24, X5]    [8]

0x436530 LDR	X30, [SP, #104]    [15]

0x436534 STR	D31, [X23, X30,LSL #3]    [26]

0x436538 LDR	D30, [X22, X5]    [4]

0x43653c STR	D30, [X18, X25,LSL #3]    [18]

0x436540 LDR	D29, [X24, X5]    [8]

0x436544 LDR	X25, [SP, #112]    [15]

0x436548 STR	D29, [X23, X25,LSL #3]    [26]

0x43654c LDR	D28, [X22, X5]    [4]

0x436550 STR	D28, [X18, X4,LSL #3]    [18]

0x436554 LDR	D27, [X24, X5]    [8]

0x436558 LDR	X24, [SP, #120]    [15]

0x43655c STR	D27, [X23, X24,LSL #3]    [26]

0x436560 LDR	D26, [X22, X5]    [4]

0x436564 STR	D26, [X18, X1,LSL #3]    [18]

0x436568 ADD	X4, X17, #1

0x43656c B	4363cc

0x436804 LDP	X23, X0, [X19]    [41]

0x436808 LDR	X30, [X9, #48]    [3]

0x43680c LDR	X22, [X0, #8]    [35]

0x436810 LDR	X25, [X9, #64]    [3]

0x436814 MADD	X24, X3, X30, X10

0x436818 LDR	X17, [X23, #8]    [31]

0x43681c LDR	D29, [X22, X5]    [24]

0x436820 LDR	X18, [X9]    [3]

0x436824 LDR	X22, [X19, #24]    [41]

0x436828 STR	D29, [X25, X24,LSL #3]    [14]

0x43682c LDR	X24, [X19, #16]    [41]

0x436830 MADD	X30, X3, X18, X10

0x436834 LDR	D28, [X17, X5]    [16]

0x436838 LDR	X25, [X9, #16]    [3]

0x43683c LDR	X24, [X24, #8]    [34]

0x436840 LDR	X17, [X9, #168]    [3]

0x436844 LDR	X23, [X9, #184]    [3]

0x436848 STR	D28, [X25, X30,LSL #3]    [13]

0x43684c LDR	D27, [X24, X5]    [33]

0x436850 MUL	X18, X17, X3

0x436854 LDR	X22, [X22, #8]    [23]

0x436858 LDR	X0, [X9, #216]    [3]

0x43685c ADD	X30, X18, X10

0x436860 ADD	X25, X18, X4

0x436864 ADD	X17, X17, X18

0x436868 LDR	X18, [X9, #232]    [3]

0x43686c STR	D27, [X23, X30,LSL #3]    [30]

0x436870 ADD	X30, X17, X4

0x436874 LDR	D26, [X22, X5]    [22]

0x436878 STR	X25, [SP, #96]    [15]

0x43687c ADD	X25, X17, X10

0x436880 MUL	X17, X0, X3

0x436884 STR	X30, [SP, #104]    [15]

0x436888 ADD	X30, X17, X10

0x43688c ADD	X0, X0, X17

0x436890 ADD	X17, X17, X4

0x436894 ADD	X10, X0, X10

0x436898 STR	D26, [X18, X30,LSL #3]    [21]

0x43689c ADD	X0, X0, X4

0x4368a0 LDR	D25, [X24, X5]    [33]

0x4368a4 LDR	X30, [SP, #96]    [15]

0x4368a8 STR	D25, [X23, X30,LSL #3]    [30]

0x4368ac LDR	D24, [X22, X5]    [22]

0x4368b0 STR	D24, [X18, X17,LSL #3]    [21]

0x4368b4 LDR	D0, [X24, X5]    [33]

0x4368b8 STR	D0, [X23, X25,LSL #3]    [30]

0x4368bc LDR	D1, [X22, X5]    [22]

0x4368c0 STR	D1, [X18, X10,LSL #3]    [21]

0x4368c4 LDR	D2, [X24, X5]    [33]

0x4368c8 LDR	X24, [SP, #104]    [15]

0x4368cc STR	D2, [X23, X24,LSL #3]    [30]

0x4368d0 LDR	D3, [X22, X5]    [22]

0x4368d4 STR	D3, [X18, X0,LSL #3]    [21]

0x4368d8 B	436424

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 91 - 98

--------------------------------------------------------------------------------

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►67.42+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec
►32.58+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

Coverage (%)	Name	Source Location	Module
►50.56+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec
►49.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

Coverage (%)	Name	Source Location	Module
►71.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►28.57+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►80.88+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►19.12+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►83.33+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►16.67+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►85.00+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►15.00+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►85.37+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►14.63+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►88.89+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.11+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►90.91+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►9.09+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

Coverage (%)	Name	Source Location	Module
►90.24+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►9.76+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.77
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.98
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P10,
Function	generate_chunk(int, global_variables&) [clone ._omp_fn.1]
Source	context.h:46-46,context.h:69-69,generate_chunk.cpp:91-98
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	34.83
CQA cycles if no scalar integer	19.67
CQA cycles if FP arith vectorized	34.83
CQA cycles if fully vectorized	8.75
Front-end cycles	19.88
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	9.00
P5 cycles	9.00
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	34.83
P11 cycles	34.50
P12 cycles	34.67
P13 cycles	2.50
P14 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	159.00
Nb uops	159.00
Nb loads	NA
Nb stores	25.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.36
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	26.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.77
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.98
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P10,
Function	generate_chunk(int, global_variables&) [clone ._omp_fn.1]
Source	context.h:46-46,context.h:69-69,generate_chunk.cpp:91-98
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	34.83
CQA cycles if no scalar integer	19.67
CQA cycles if FP arith vectorized	34.83
CQA cycles if fully vectorized	8.75
Front-end cycles	19.88
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	9.00
P5 cycles	9.00
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	34.83
P11 cycles	34.50
P12 cycles	34.67
P13 cycles	2.50
P14 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	159.00
Nb uops	159.00
Nb loads	NA
Nb stores	25.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.36
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	26.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	generate_chunk(int, global_variables&) [clone ._omp_fn.1]
Source file and lines	generate_chunk.cpp:91-98
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:91-98

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=25
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 25 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.83 to 19.67 cycles (1.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 34.83 to 8.75 cycles (3.98x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	159
nb uops	159
loop length	636
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	24
used q registers	0
used v registers	0
used z registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.88 cycles
front end	19.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	9.00	9.00	9.00	9.00	14.00	14.00	0.00	0.00	34.83	34.50	34.67	2.50	2.50
cycles	5.50	5.50	9.00	9.00	9.00	9.00	14.00	14.00	0.00	0.00	34.83	34.50	34.67	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.88
Dispatch	34.83
Overall L1	34.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 34.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4363cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D22, [X6, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D23, D22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 436424 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X6, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X0, [X16, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D20, [X0, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D21, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 436424 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X9, #632]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D19, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X22, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D19, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 436424 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X19, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D31, [X23, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X17, [X18, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D30, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D31, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 436804 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 436258 <_Z14generate_chunkiR16global_variables._omp_fn.1+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X17, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X10, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X6, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D5, D4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 436568 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X6, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X1, [X16, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D7, [X1, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D6, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 436568 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X9, #632]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D16, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X22, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D16, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 436568 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X19, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X23, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [X18, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D23, [X25, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D22, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 436568 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X22, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X1, [X9, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X9, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X18, X3, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X23, [X23, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D21, [X25, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X1, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X9, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D21, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X24, X18, [X19, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MADD X25, X3, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D20, [X23, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X22, [X9, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X9, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X9, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D20, [X22, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X22, [X18, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X18, X30, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D19, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X1, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X9, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D19, [X23, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X25, X30, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STP X25, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL X25, X1, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X30, X25, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X25, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR D18, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X30, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D31, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D30, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [X18, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D29, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D29, [X23, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D28, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D28, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D27, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X24, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D27, [X23, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D26, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D26, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X4, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 4363cc <_Z14generate_chunkiR16global_variables._omp_fn.1+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X0, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X30, [X9, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X9, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X24, X3, X30, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D29, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X19, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D29, [X25, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X24, [X19, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X30, X3, X18, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D28, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [X9, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X9, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X9, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D28, [X25, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D27, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
MUL X18, X17, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X22, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X9, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X9, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D27, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X30, X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X25, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X17, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
STR X30, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X30, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR D26, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X0, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D25, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D24, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D24, [X18, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X23, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D1, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D1, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D2, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X24, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D2, [X23, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D3, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 436424 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	generate_chunk(int, global_variables&) [clone ._omp_fn.1]
Source file and lines	generate_chunk.cpp:91-98
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:91-98

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=25
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	159
nb uops	159
loop length	636
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	24
used q registers	0
used v registers	0
used z registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.88 cycles
front end	19.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	9.00	9.00	9.00	9.00	14.00	14.00	0.00	0.00	34.83	34.50	34.67	2.50	2.50
cycles	5.50	5.50	9.00	9.00	9.00	9.00	14.00	14.00	0.00	0.00	34.83	34.50	34.67	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.88
Dispatch	34.83
Overall L1	34.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	25%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 34.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4363cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D22, [X6, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D23, D22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 436424 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X6, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X0, [X16, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D20, [X0, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D21, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 436424 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X9, #632]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D19, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X22, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D19, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 436424 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X19, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D31, [X23, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X17, [X18, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D30, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D31, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 436804 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 436258 <_Z14generate_chunkiR16global_variables._omp_fn.1+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X17, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X10, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X6, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D5, D4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 436568 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X6, X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X1, [X16, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D7, [X1, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D6, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 436568 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X9, #632]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D16, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X22, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D16, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 436568 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X19, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X23, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [X18, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D23, [X25, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D22, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 436568 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X22, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X1, [X9, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X9, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X18, X3, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X23, [X23, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D21, [X25, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X1, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X9, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D21, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X24, X18, [X19, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MADD X25, X3, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D20, [X23, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X22, [X9, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X9, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X9, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D20, [X22, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X22, [X18, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X18, X30, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D19, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X1, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X9, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D19, [X23, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X25, X30, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STP X25, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MUL X25, X1, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X30, X25, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X25, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR D18, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X30, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D31, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D30, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [X18, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D29, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D29, [X23, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D28, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D28, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D27, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X24, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D27, [X23, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D26, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D26, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X4, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 4363cc <_Z14generate_chunkiR16global_variables._omp_fn.1+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X0, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X30, [X9, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X9, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X24, X3, X30, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X17, [X23, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D29, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X19, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D29, [X25, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X24, [X19, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X30, X3, X18, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D28, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [X9, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X9, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X9, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D28, [X25, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D27, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
MUL X18, X17, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X22, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X9, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [X9, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D27, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X30, X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X25, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X17, X0, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
STR X30, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X30, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR D26, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X0, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D25, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D24, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D24, [X18, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X23, X25,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D1, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D1, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D2, [X24, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X24, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D2, [X23, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X22, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D3, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 436424 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_4/oneview_run_1782227431OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	1	0	0.99	0	0.96	0	1.25	0	1.8	0	2.16	0	2.11	0	1.92	0	1.96	0	2.11	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.44499999284744	0.029939919710159
1x2	2	1	1.99	2	0.29999998211861	0.029764438048005
1x4	4	0.99	3.96	4	0.22499999403954	0.029286691918969
1x8	8	0.96	7.7	8	0.13000001013279	0.026615537703037
1x16	10	1.25	19.94	16	0.065000005066395	0.013265687972307
1x24	7	1.8	43.09	24	0.045000001788139	0.0065836305730045
1x32	7	2.16	69.07	32	0.035000000149012	0.0044610742479563
1x40	8	2.11	84.32	40	0.029999999329448	0.0038548556622118
1x48	10	1.92	92.16	48	0.025000000372529	0.0035877008922398
1x56	11	1.96	109.99	56	0.019999999552965	0.0030117474962026
1x64	13	2.11	135.12	64	0.02000000141561	0.00244783423841

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency