OV - exec - Function _QMviscosity_kernel_modulePviscosity_kernel..omp

	Function: _QMviscosity_kernel_modulePviscosity_kernel..omp_par	Module: exec	Source: viscosity_kernel.f90:28-98 [...]	Coverage (incl. loops): 2.49% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 28 - 98

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28:   SUBROUTINE viscosity_kernel(x_min,x_max,y_min,y_max,    &

[...]

52:     !$OMP DO PRIVATE(ugrad,vgrad,div,strain2,pgradx,pgrady,pgradx2,pgrady2,limiter,pgrad,xgrad,ygrad,grad,grad2,dirx,diry)

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

[...]

98:   END SUBROUTINE viscosity_kernel

0x44ef30 SUB	SP, SP, #160

0x44ef34 STP	X29, X30, [SP, #64]

0x44ef38 STP	X28, X27, [SP, #80]

0x44ef3c STP	X26, X25, [SP, #96]

0x44ef40 STP	X24, X23, [SP, #112]

0x44ef44 STP	X22, X21, [SP, #128]

0x44ef48 STP	X20, X19, [SP, #144]

0x44ef4c ADD	X29, SP, #64

0x44ef50 LDP	X8, X9, [X2]

0x44ef54 LDP	X12, X13, [X2, #48]

0x44ef58 ADRP	X0,

0x44ef5c ADD	X0, X0, #984

0x44ef60 LDR	X10, [X2, #16]

0x44ef64 LDR	X11, [X2, #32]

0x44ef68 LDR	X27, [X2, #128]

0x44ef6c LDR	X28, [X8]

0x44ef70 LDP	X15, X14, [X2, #64]

0x44ef74 LDR	X19, [X9]

0x44ef78 LDR	W9, [X12]

0x44ef7c LDR	W8, [X13]

0x44ef80 LDR	X20, [X10]

0x44ef84 STP	X14, X15, [SP, #16]

0x44ef88 SUBS	W8, W8, W9

0x44ef8c LDP	X23, X14, [X2, #96]

0x44ef90 LDP	X21, X22, [X2, #80]

0x44ef94 LDR	X24, [X11]

0x44ef98 LDP	X25, X26, [X2, #112]

0x44ef9c STUR	X14, [X29, #488]

0x44efa0 STR	W9, [SP, #8]

0x44efa4 CSINV	W8, W8, WZR, #10

0x44efa8 STP	W8, WZR, [X29, #500]

0x44efac MOVZ	W8, #1

0x44efb0 STUR	W8, [X29, #496]

0x44efb4 BL	410140

0x44efb8 ORR	W1, WZR, W0

0x44efbc SUB	X3, X29, #4

0x44efc0 SUB	X4, X29, #8

0x44efc4 SUB	X5, X29, #12

0x44efc8 SUB	X6, X29, #16

0x44efcc STR	WZR, [SP]

0x44efd0 ADRP	X0,

0x44efd4 ADD	X0, X0, #984

0x44efd8 MOVZ	W2, #34

0x44efdc MOVZ	W7, #1

0x44efe0 STR	W1, [SP, #12]

0x44efe4 BL	4101b0

0x44efe8 LDP	W8, W12, [X29, #500]

0x44efec SUB	W8, W8, W12

0x44eff0 CMN	W8, #1

0x44eff4 STUR	W8, [X29, #484]

0x44eff8 B.EQ	44f474

0x44effc LDP	X8, X10, [SP, #16]

0x44f000 LDR	W9, [X10]

0x44f004 LDR	W13, [X8]

0x44f008 SUBS	W10, W13, W9

0x44f00c B.LT	44f474

0x44f010 ADD	W10, W10, #1

0x44f014 CBZ	W10, 44f474

0x44f018 ADD	W14, W9, #1

0x44f01c ADD	W15, W13, #1

0x44f020 LDR	W8, [SP, #8]

0x44f024 SUB	W13, W13, #1

0x44f028 FMOV	D1, #0.5000000

0x44f02c PTRUE	P1.D, ALL

0x44f030 MOVI	V3.2D, #0

0x44f034 ORR	W11, WZR, WZR

0x44f038 CMP	W15, W14

0x44f03c ADRP	X15,

0x44f040 SUB	W14, W9, #1

0x44f044 LDR	D0, [X15, #120]

0x44f048 CCMP	W13, W14, #8, #10

0x44f04c CNTD	X14, ALL

0x44f050 ADD	W8, W12, W8

0x44f054 DUP	Z2.D, Z0.D[0]

0x44f058 STR	W8, [SP, #24]

0x44f05c CSINC	W8, WZR, WZR, #10

0x44f060 SUBS	W15, W10, W14

0x44f064 CSEL	W15, WZR, W15, #3

0x44f068 WHILELO	P0.D, WZR, W10

0x44f06c STR	W8, [SP, #16]

0x44f070 B	44f090

0x44f074 HINT	#0

0x44f078 HINT	#0

0x44f07c HINT	#0

  (1240) 0x44f080 LDUR	W8, [X29, #484]

  (1240) 0x44f084 CMP	W11, W8

  (1240) 0x44f088 ADD	W11, W11, #1

  (1240) 0x44f08c B.EQ	44f474

  (1240) 0x44f090 LDR	W8, [SP, #24]

  (1240) 0x44f094 ADD	W2, W8, W11

  (1240) 0x44f098 LDUR	X8, [X29, #488]

  (1240) 0x44f09c ADD	W17, W2, #1

  (1240) 0x44f0a0 SBFM	X16, X2, #0, #31

  (1240) 0x44f0a4 SUB	W2, W2, #1

  (1240) 0x44f0a8 SBFM	X17, X17, #0, #31

  (1240) 0x44f0ac SUB	X18, X16, X20

  (1240) 0x44f0b0 SBFM	X2, X2, #0, #31

  (1240) 0x44f0b4 SUB	X3, X17, X20

  (1240) 0x44f0b8 SUB	X2, X2, X20

  (1240) 0x44f0bc MUL	X16, X18, X19

  (1240) 0x44f0c0 LDR	D4, [X8, X18,LSL #3]

  (1240) 0x44f0c4 LDR	D5, [X8, X3,LSL #3]

  (1240) 0x44f0c8 LDR	W8, [SP, #16]

  (1240) 0x44f0cc MUL	X18, X18, X24

  (1240) 0x44f0d0 MUL	X1, X3, X24

  (1240) 0x44f0d4 MUL	X2, X2, X24

  (1240) 0x44f0d8 MUL	X17, X3, X19

  (1240) 0x44f0dc ADD	X0, X25, X18,LSL #3

  (1240) 0x44f0e0 ADD	X1, X25, X1,LSL #3

  (1240) 0x44f0e4 ADD	X2, X25, X2,LSL #3

  (1240) 0x44f0e8 ADD	X3, X27, X18,LSL #3

  (1240) 0x44f0ec FADD	D5, D4, D5

  (1240) 0x44f0f0 CBZ	W8, 44f2ac

(1241) 0x44f0f4 ORR	W4, WZR, WZR

(1241) 0x44f0f8 B	44f110

0x44f0fc HINT	#0

(1241) 0x44f100 STR	XZR, [X3, X5,LSL #3]

(1241) 0x44f104 ADD	W4, W4, #1

(1241) 0x44f108 CMP	W10, W4

(1241) 0x44f10c B.LS	44f080

  (1242) 0x44f110 ADD	W7, W9, W4

  (1242) 0x44f114 ADD	W12, W7, #1

  (1242) 0x44f118 SBFM	X5, X7, #0, #31

  (1242) 0x44f11c SBFM	X12, X12, #0, #31

  (1242) 0x44f120 SUB	X5, X5, X28

  (1242) 0x44f124 SUB	X6, X12, X28

  (1242) 0x44f128 ADD	X30, X5, X16

  (1242) 0x44f12c ADD	X8, X5, X17

  (1242) 0x44f130 ADD	X12, X6, X16

  (1242) 0x44f134 ADD	X13, X6, X17

  (1242) 0x44f138 LDR	D20, [X21, X30,LSL #3]

  (1242) 0x44f13c LDR	D22, [X21, X8,LSL #3]

  (1242) 0x44f140 LDR	D19, [X22, X8,LSL #3]

  (1242) 0x44f144 LDR	D23, [X22, X30,LSL #3]

  (1242) 0x44f148 LDR	D17, [X21, X12,LSL #3]

  (1242) 0x44f14c LDR	D18, [X21, X13,LSL #3]

  (1242) 0x44f150 LDR	D21, [X22, X13,LSL #3]

  (1242) 0x44f154 LDR	D24, [X22, X12,LSL #3]

  (1242) 0x44f158 FADD	D7, D20, D22

  (1242) 0x44f15c FADD	D6, D17, D18

  (1242) 0x44f160 FADD	D16, D23, D24

  (1242) 0x44f164 FSUB	D7, D6, S7

  (1242) 0x44f168 FADD	D6, D19, D21

  (1242) 0x44f16c FSUB	D16, D6, S16

  (1242) 0x44f170 LDR	D6, [X23, X5,LSL #3]

  (1242) 0x44f174 FMUL	D25, D4, D16

  (1242) 0x44f178 FMADD	D25, D7, D6, D25

  (1242) 0x44f17c FCMP	D25, #0

  (1242) 0x44f180 B.GE	44f100

  (1242) 0x44f184 FADD	D18, D18, D22

  (1242) 0x44f188 SUB	W8, W7, #1

  (1242) 0x44f18c FMUL	D16, D16, D1

  (1242) 0x44f190 FMUL	D7, D7, D1

  (1242) 0x44f194 SBFM	X8, X8, #0, #31

  (1242) 0x44f198 FSUB	D18, D18, S20

  (1242) 0x44f19c SUB	X8, X8, X28

  (1242) 0x44f1a0 LDR	D20, [X2, X5,LSL #3]

  (1242) 0x44f1a4 FDIV	D16, D16, D4

  (1242) 0x44f1a8 FDIV	D7, D7, D6

  (1242) 0x44f1ac FSUB	D17, D18, S17

  (1242) 0x44f1b0 FADD	D18, D21, D24

  (1242) 0x44f1b4 FSUB	D18, D18, S23

  (1242) 0x44f1b8 FMUL	D17, D17, D1

  (1242) 0x44f1bc FSUB	D18, D18, S19

  (1242) 0x44f1c0 FDIV	D17, D17, D4

  (1242) 0x44f1c4 FMUL	D18, D18, D1

  (1242) 0x44f1c8 FDIV	D18, D18, D6

  (1242) 0x44f1cc FADD	D19, D17, D18

  (1242) 0x44f1d0 LDR	D17, [X0, X6,LSL #3]

  (1242) 0x44f1d4 LDR	D18, [X0, X8,LSL #3]

  (1242) 0x44f1d8 FSUB	D17, D17, S18

  (1242) 0x44f1dc LDR	D18, [X23, X6,LSL #3]

  (1242) 0x44f1e0 FADD	D18, D6, D18

  (1242) 0x44f1e4 FDIV	D17, D17, D18

  (1242) 0x44f1e8 LDR	D18, [X1, X5,LSL #3]

  (1242) 0x44f1ec FSUB	D18, D18, S20

  (1242) 0x44f1f0 FDIV	D18, D18, D5

  (1242) 0x44f1f4 FMUL	D20, D17, D17

  (1242) 0x44f1f8 FMUL	D21, D18, D18

  (1242) 0x44f1fc FMUL	D16, D16, D21

  (1242) 0x44f200 FMADD	D7, D7, D20, D16

  (1242) 0x44f204 FMUL	D16, D19, D17

  (1242) 0x44f208 FMADD	D7, D16, D18, D7

  (1242) 0x44f20c FADD	D16, D20, D21

  (1242) 0x44f210 FMAXNM	D16, D16, D0

  (1242) 0x44f214 FDIV	D7, D7, D16

  (1242) 0x44f218 FCMP	D7, #0

  (1242) 0x44f21c B.GT	44f100

  (1242) 0x44f220 FABS	D16, D17

  (1242) 0x44f224 ADD	X8, X5, X18

  (1242) 0x44f228 FCMP	D16, D0

  (1242) 0x44f22c FCSEL	D16, D0, D16, #4

  (1242) 0x44f230 FCMP	D17, #0

  (1242) 0x44f234 FABS	D17, D18

  (1242) 0x44f238 FNEG	D19, D16

  (1242) 0x44f23c FCSEL	D16, D19, D16, #4

  (1242) 0x44f240 FCMP	D17, D0

  (1242) 0x44f244 FCSEL	D17, D0, D17, #4

  (1242) 0x44f248 FCMP	D16, #0

  (1242) 0x44f24c FNEG	D18, D17

  (1242) 0x44f250 FCSEL	D17, D18, D17, #4

  (1242) 0x44f254 FMUL	D18, D17, D17

  (1242) 0x44f258 FMADD	D18, D16, D16, D18

  (1242) 0x44f25c FSQRT	D18, D18

  (1242) 0x44f260 FMUL	D6, D6, D18

  (1242) 0x44f264 FDIV	D6, D6, D16

  (1242) 0x44f268 FMUL	D16, D4, D18

  (1242) 0x44f26c FDIV	D16, D16, D17

  (1242) 0x44f270 FABS	D6, D6

  (1242) 0x44f274 FABS	D16, D16

  (1242) 0x44f278 FCMP	D6, D16

  (1242) 0x44f27c FCSEL	D6, D6, D16, #4

  (1242) 0x44f280 LDR	D16, [X26, X8,LSL #3]

  (1242) 0x44f284 FMUL	D6, D6, D6

  (1242) 0x44f288 FADD	D16, D16, D16

  (1242) 0x44f28c FMUL	D6, D6, D16

  (1242) 0x44f290 FMUL	D6, D7, D6

  (1242) 0x44f294 FMUL	D6, D7, D6

  (1242) 0x44f298 STR	D6, [X27, X8,LSL #3]

  (1242) 0x44f29c ADD	W4, W4, #1

  (1242) 0x44f2a0 CMP	W10, W4

  (1242) 0x44f2a4 B.HI	44f110

  (1240) 0x44f2a8 B	44f080

  (1240) 0x44f2ac DUP	Z4.D, Z4.D[0]

  (1240) 0x44f2b0 DUP	Z5.D, Z5.D[0]

  (1240) 0x44f2b4 SUB	X5, XZR, X14

  (1240) 0x44f2b8 ORR	P2.B, P0/Z, P0.B, P0.B

  (1240) 0x44f2bc ORR	W4, WZR, W9

    (1239) 0x44f2c0 ADD	W6, W4, #1

    (1239) 0x44f2c4 SUB	W7, W4, #1

    (1239) 0x44f2c8 SBFM	X30, X4, #0, #31

    (1239) 0x44f2cc ADD	W5, W5, W14

    (1239) 0x44f2d0 ADD	W4, W4, W14

    (1239) 0x44f2d4 SBFM	X12, X6, #0, #31

    (1239) 0x44f2d8 SBFM	X7, X7, #0, #31

    (1239) 0x44f2dc SUB	X6, X30, X28

    (1239) 0x44f2e0 LD1D	{Z6.D}, P2/Z, [X23, X6,LSL #3]

    (1239) 0x44f2e4 SUB	X12, X12, X28

    (1239) 0x44f2e8 SUB	X7, X7, X28

    (1239) 0x44f2ec LD1D	{Z18.D}, P2/Z, [X1, X6,LSL #3]

    (1239) 0x44f2f0 LD1D	{Z19.D}, P2/Z, [X2, X6,LSL #3]

    (1239) 0x44f2f4 ADD	X30, X6, X17

    (1239) 0x44f2f8 LD1D	{Z7.D}, P2/Z, [X0, X12,LSL #3]

    (1239) 0x44f2fc LD1D	{Z16.D}, P2/Z, [X0, X7,LSL #3]

    (1239) 0x44f300 LD1D	{Z17.D}, P2/Z, [X23, X12,LSL #3]

    (1239) 0x44f304 ADD	X7, X6, X16

    (1239) 0x44f308 ADD	X13, X12, X16

    (1239) 0x44f30c ADD	X12, X12, X17

    (1239) 0x44f310 LD1D	{Z20.D}, P2/Z, [X22, X7,LSL #3]

    (1239) 0x44f314 LD1D	{Z21.D}, P2/Z, [X21, X12,LSL #3]

    (1239) 0x44f318 LD1D	{Z22.D}, P2/Z, [X22, X13,LSL #3]

    (1239) 0x44f31c LD1D	{Z23.D}, P2/Z, [X21, X7,LSL #3]

    (1239) 0x44f320 FSUB	Z7.D, Z7.D, Z16.D

    (1239) 0x44f324 FADD	Z16.D, Z6.D, Z17.D

    (1239) 0x44f328 LD1D	{Z17.D}, P2/Z, [X22, X12,LSL #3]

    (1239) 0x44f32c LD1D	{Z24.D}, P2/Z, [X21, X13,LSL #3]

    (1239) 0x44f330 ADD	X12, X6, X18

    (1239) 0x44f334 FADD	Z26.D, Z20.D, Z22.D

    (1239) 0x44f338 FDIVR	Z16.D, P1/M, Z16.D, Z7.D

    (1239) 0x44f33c FSUB	Z7.D, Z18.D, Z19.D

    (1239) 0x44f340 LD1D	{Z18.D}, P2/Z, [X21, X30,LSL #3]

    (1239) 0x44f344 LD1D	{Z19.D}, P2/Z, [X22, X30,LSL #3]

    (1239) 0x44f348 FDIV	Z7.D, P1/M, Z7.D, Z5.D

    (1239) 0x44f34c FADD	Z22.D, Z17.D, Z22.D

    (1239) 0x44f350 FADD	Z25.D, Z19.D, Z17.D

    (1239) 0x44f354 FADD	Z27.D, Z21.D, Z18.D

    (1239) 0x44f358 FSUB	Z20.D, Z22.D, Z20.D

    (1239) 0x44f35c FADD	Z18.D, Z23.D, Z18.D

    (1239) 0x44f360 FADD	Z21.D, Z24.D, Z21.D

    (1239) 0x44f364 FSUB	Z17.D, Z25.D, Z26.D

    (1239) 0x44f368 FSUB	Z26.D, Z27.D, Z23.D

    (1239) 0x44f36c FSUB	Z19.D, Z20.D, Z19.D

    (1239) 0x44f370 FSUB	Z18.D, Z21.D, Z18.D

    (1239) 0x44f374 FSUB	Z22.D, Z26.D, Z24.D

    (1239) 0x44f378 MOVPRFX	Z20, Z17

    (1239) 0x44f37c FMUL	Z20.D, P1/M, Z20.D, #0.0000000

    (1239) 0x44f380 FMUL	Z19.D, P1/M, Z19.D, #0.0000000

    (1239) 0x44f384 MOVPRFX	Z21, Z18

    (1239) 0x44f388 FMUL	Z21.D, P1/M, Z21.D, #0.0000000

    (1239) 0x44f38c FMUL	Z17.D, Z4.D, Z17.D

    (1239) 0x44f390 FMUL	Z22.D, P1/M, Z22.D, #0.0000000

    (1239) 0x44f394 FDIV	Z20.D, P1/M, Z20.D, Z4.D

    (1239) 0x44f398 FDIV	Z19.D, P1/M, Z19.D, Z6.D

    (1239) 0x44f39c MOVPRFX	Z25, Z16

    (1239) 0x44f3a0 FABS	Z25.D, P1/M, Z16.D

    (1239) 0x44f3a4 MOVPRFX	Z23, Z7

    (1239) 0x44f3a8 FABS	Z23.D, P1/M, Z7.D

    (1239) 0x44f3ac FCMGT	P3.D, P1/Z, Z2.D, Z25.D

    (1239) 0x44f3b0 SEL	Z24.D, P3, Z2.D, Z25.D

    (1239) 0x44f3b4 FCMLT	P4.D, P1/Z, Z16.D, #0.0000000

    (1239) 0x44f3b8 FCMGT	P3.D, P1/Z, Z2.D, Z23.D

    (1239) 0x44f3bc FNEG	Z24.D, P4/M, Z24.D

    (1239) 0x44f3c0 FDIV	Z22.D, P1/M, Z22.D, Z4.D

    (1239) 0x44f3c4 SEL	Z23.D, P3, Z2.D, Z23.D

    (1239) 0x44f3c8 FMUL	Z25.D, Z24.D, Z24.D

    (1239) 0x44f3cc FADD	Z19.D, Z22.D, Z19.D

    (1239) 0x44f3d0 FCMLT	P3.D, P1/Z, Z24.D, #0.0000000

    (1239) 0x44f3d4 FDIV	Z21.D, P1/M, Z21.D, Z6.D

    (1239) 0x44f3d8 FNEG	Z23.D, P3/M, Z23.D

    (1239) 0x44f3dc FMUL	Z26.D, Z23.D, Z23.D

    (1239) 0x44f3e0 FADD	Z25.D, Z25.D, Z26.D

    (1239) 0x44f3e4 FMUL	Z26.D, Z7.D, Z7.D

    (1239) 0x44f3e8 FMUL	Z22.D, Z16.D, Z16.D

    (1239) 0x44f3ec FMUL	Z16.D, Z19.D, Z16.D

    (1239) 0x44f3f0 FMUL	Z20.D, Z20.D, Z26.D

    (1239) 0x44f3f4 FADD	Z19.D, Z22.D, Z26.D

    (1239) 0x44f3f8 FMLA	Z20.D, P1/M, Z21.D, Z22.D

    (1239) 0x44f3fc FSQRT	Z25.D, P1/M, Z25.D

    (1239) 0x44f400 FMAD	Z7.D, P1/M, Z16.D, Z20.D

    (1239) 0x44f404 FCMGT	P3.D, P1/Z, Z19.D, Z2.D

    (1239) 0x44f408 SEL	Z16.D, P3, Z19.D, Z2.D

    (1239) 0x44f40c FMUL	Z19.D, Z4.D, Z25.D

    (1239) 0x44f410 FDIV	Z7.D, P1/M, Z7.D, Z16.D

    (1239) 0x44f414 FMUL	Z16.D, Z6.D, Z25.D

    (1239) 0x44f418 FMAD	Z6.D, P1/M, Z18.D, Z17.D

    (1239) 0x44f41c FCMGE	P3.D, P1/Z, Z6.D, #0.0000000

    (1239) 0x44f420 FDIV	Z16.D, P1/M, Z16.D, Z24.D

    (1239) 0x44f424 FABS	Z16.D, P1/M, Z16.D

    (1239) 0x44f428 FDIV	Z19.D, P1/M, Z19.D, Z23.D

    (1239) 0x44f42c FCMGT	P4.D, P1/Z, Z7.D, #0.0000000

    (1239) 0x44f430 SEL	P3.B, P3, P3.B, P4.B

    (1239) 0x44f434 BIC	P4.B, P2/Z, P2.B, P3.B

    (1239) 0x44f438 FABS	Z19.D, P1/M, Z19.D

    (1239) 0x44f43c LD1D	{Z6.D}, P4/Z, [X26, X12,LSL #3]

    (1239) 0x44f440 AND	P2.B, P2/Z, P2.B, P3.B

    (1239) 0x44f444 FCMGT	P5.D, P1/Z, Z19.D, Z16.D

    (1239) 0x44f448 FADD	Z6.D, Z6.D, Z6.D

    (1239) 0x44f44c SEL	Z16.D, P5, Z16.D, Z19.D

    (1239) 0x44f450 FMUL	Z16.D, Z16.D, Z16.D

    (1239) 0x44f454 FMUL	Z6.D, Z16.D, Z6.D

    (1239) 0x44f458 FMUL	Z6.D, Z7.D, Z6.D

    (1239) 0x44f45c FMUL	Z6.D, Z7.D, Z6.D

    (1239) 0x44f460 ST1D	{Z6.D}, P4, [X27, X12,LSL #3]

    (1239) 0x44f464 ST1D	{Z3.D}, P2, [X3, X6,LSL #3]

    (1239) 0x44f468 WHILELO	P2.D, W5, W15

    (1239) 0x44f46c B.MI	44f2c0

  (1240) 0x44f470 B	44f080

0x44f474 LDR	W19, [SP, #12]

0x44f478 ADRP	X0,

0x44f47c ADD	X0, X0, #984

0x44f480 ORR	W1, WZR, W19

0x44f484 BL	410040

0x44f488 ADRP	X0,

0x44f48c ADD	X0, X0, #1008

0x44f490 ORR	W1, WZR, W19

0x44f494 BL	410330

0x44f498 LDP	X20, X19, [SP, #144]

0x44f49c LDP	X22, X21, [SP, #128]

0x44f4a0 LDP	X24, X23, [SP, #112]

0x44f4a4 LDP	X26, X25, [SP, #96]

0x44f4a8 LDP	X28, X27, [SP, #80]

0x44f4ac LDP	X29, X30, [SP, #64]

0x44f4b0 ADD	SP, SP, #160

0x44f4b4 RET

0x44f4b8 HINT	#0

0x44f4bc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.39+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.61+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	viscosity_kernel	viscosity_kernel.f90:98	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	viscosity_kernel.f90:28-98
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:28,52-89,98.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 1.00 cycles (14.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 14.67 to 7.86 cycles (1.87x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 18 bytes. The binary function is storing 21 bytes.

General properties

nb instructions	104
nb uops	98
loop length	416
used w registers	14
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	1
used z registers	2
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	11.50	11.50	11.50	11.50	0.75	0.75	0.75	0.75	14.67	14.67	14.67	8.00	8.00
cycles	4.50	4.50	11.50	11.50	11.50	11.50	0.75	0.75	0.75	0.75	14.67	14.67	14.67	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	14.67
Overall L1	14.67

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	30%
load	37%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	37%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

1% of peak load performance is reached (1.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.43 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 44ef30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X13, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48ff58>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #984	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X28, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X14, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X14, X15, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDP X23, X14, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X25, X26, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X14, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X3, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADRP X0, <48ffd0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #984	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STUR W8, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 44f474 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W10, W13, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 44f474 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 44f474 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W15, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D1, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V3.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W15, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADRP X15, <47003c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W14, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D0, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CCMP W13, W14, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W8, W12, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z2.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CSINC W8, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W15, W10, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W15, WZR, W15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, WZR, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
STR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 44f090 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48f478>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #984	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48f488>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1008	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	viscosity_kernel.f90:28-98
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 18 bytes. The binary function is storing 21 bytes.

General properties

nb instructions	104
nb uops	98
loop length	416
used w registers	14
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	1
used z registers	2
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	11.50	11.50	11.50	11.50	0.75	0.75	0.75	0.75	14.67	14.67	14.67	8.00	8.00
cycles	4.50	4.50	11.50	11.50	11.50	11.50	0.75	0.75	0.75	0.75	14.67	14.67	14.67	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	14.67
Overall L1	14.67

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	30%
load	37%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	37%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

1% of peak load performance is reached (1.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.43 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 44ef30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X13, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48ff58>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #984	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X28, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X14, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X14, X15, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDP X23, X14, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X25, X26, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X14, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X3, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADRP X0, <48ffd0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #984	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STUR W8, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 44f474 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W10, W13, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 44f474 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 44f474 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W15, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D1, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V3.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W15, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADRP X15, <47003c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W14, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D0, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CCMP W13, W14, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W8, W12, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z2.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CSINC W8, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W15, W10, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W15, WZR, W15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, WZR, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
STR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 44f090 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48f478>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #984	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48f488>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1008	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼_QMviscosity_kernel_modulePviscosity_kernel..omp_par–	2.49	3.40
▼Loop 1241 - viscosity_kernel.f90:52-89 - exec–	0.00	0.00
▼Loop 1240 - viscosity_kernel.f90:52-89 - exec–	0.00	0.02
○Loop 1239 - viscosity_kernel.f90:54-89 - exec	2.48	3.39
○Loop 1242 - viscosity_kernel.f90:54-89 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

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Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code