| Function: _QMpdv_kernel_modulePpdv_kernel..omp_par | Module: exec | Source: PdV_kernel.f90:69-145 [...] | Coverage (incl. loops): 14.30% | (excl. loops): 0.01% |
|---|
| Function: _QMpdv_kernel_modulePpdv_kernel..omp_par | Module: exec | Source: PdV_kernel.f90:69-145 [...] | Coverage (incl. loops): 14.30% | (excl. loops): 0.01% |
|---|
/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 69 - 145 |
-------------------------------------------------------------------------------- |
69: IF(predict)THEN |
70: |
71: !$OMP DO PRIVATE(right_flux,left_flux,top_flux,bottom_flux,total_flux,min_cell_volume, & |
72: !$OMP energy_change,recip_volume,volume_change_s) |
73: DO k=y_min,y_max |
74: !$OMP SIMD |
75: DO j=x_min,x_max |
76: |
77: left_flux= (xarea(j ,k )*(xvel0(j ,k )+xvel0(j ,k+1) & |
78: +xvel0(j ,k )+xvel0(j ,k+1)))*0.25_8*dt*0.5 |
79: right_flux= (xarea(j+1,k )*(xvel0(j+1,k )+xvel0(j+1,k+1) & |
80: +xvel0(j+1,k )+xvel0(j+1,k+1)))*0.25_8*dt*0.5 |
81: bottom_flux=(yarea(j ,k )*(yvel0(j ,k )+yvel0(j+1,k ) & |
82: +yvel0(j ,k )+yvel0(j+1,k )))*0.25_8*dt*0.5 |
83: top_flux= (yarea(j ,k+1)*(yvel0(j ,k+1)+yvel0(j+1,k+1) & |
84: +yvel0(j ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5 |
85: total_flux=right_flux-left_flux+top_flux-bottom_flux |
86: |
87: volume_change_s=volume(j,k)/(volume(j,k)+total_flux) |
[...] |
93: recip_volume=1.0/volume(j,k) |
94: |
95: energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume |
96: |
97: energy1(j,k)=energy0(j,k)-energy_change |
98: |
99: density1(j,k)=density0(j,k)*volume_change_s |
[...] |
107: !$OMP DO PRIVATE(right_flux,left_flux,top_flux,bottom_flux,total_flux,min_cell_volume, & |
108: !$OMP energy_change,recip_volume,volume_change_s) |
109: DO k=y_min,y_max |
110: !$OMP SIMD |
111: DO j=x_min,x_max |
112: |
113: left_flux= (xarea(j ,k )*(xvel0(j ,k )+xvel0(j ,k+1) & |
114: +xvel1(j ,k )+xvel1(j ,k+1)))*0.25_8*dt |
115: right_flux= (xarea(j+1,k )*(xvel0(j+1,k )+xvel0(j+1,k+1) & |
116: +xvel1(j+1,k )+xvel1(j+1,k+1)))*0.25_8*dt |
117: bottom_flux=(yarea(j ,k )*(yvel0(j ,k )+yvel0(j+1,k ) & |
118: +yvel1(j ,k )+yvel1(j+1,k )))*0.25_8*dt |
119: top_flux= (yarea(j ,k+1)*(yvel0(j ,k+1)+yvel0(j+1,k+1) & |
120: +yvel1(j ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt |
121: total_flux=right_flux-left_flux+top_flux-bottom_flux |
122: |
123: volume_change_s=volume(j,k)/(volume(j,k)+total_flux) |
[...] |
129: recip_volume=1.0/volume(j,k) |
130: |
131: energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume |
132: |
133: energy1(j,k)=energy0(j,k)-energy_change |
134: |
135: density1(j,k)=density0(j,k)*volume_change_s |
[...] |
145: END SUBROUTINE PdV_kernel |
0x416a10 SUB SP, SP, #240 |
0x416a14 STP X29, X30, [SP, #144] |
0x416a18 STP X28, X27, [SP, #160] |
0x416a1c STP X26, X25, [SP, #176] |
0x416a20 STP X24, X23, [SP, #192] |
0x416a24 STP X22, X21, [SP, #208] |
0x416a28 STP X20, X19, [SP, #224] |
0x416a2c ADD X29, SP, #144 |
0x416a30 LDP X14, X13, [X2, #56] |
0x416a34 LDP X8, X9, [X2] |
0x416a38 ADRP X0, |
0x416a3c ADD X0, X0, #3416 |
0x416a40 LDR X10, [X2, #16] |
0x416a44 LDR X25, [X8] |
0x416a48 STP X13, X14, [SP, #40] |
0x416a4c LDP X14, X13, [X2, #72] |
0x416a50 LDP X11, X12, [X2, #40] |
0x416a54 LDR X8, [X9] |
0x416a58 LDR X9, [X10] |
0x416a5c LDP X20, X21, [X2, #88] |
0x416a60 STP X13, X14, [SP, #16] |
0x416a64 LDP X26, X13, [X2, #104] |
0x416a68 STR X8, [SP, #72] |
0x416a6c LDR X8, [X11] |
0x416a70 LDP X27, X14, [X2, #136] |
0x416a74 LDP X22, X23, [X2, #120] |
0x416a78 LDP X19, X24, [X2, #184] |
0x416a7c STR X13, [SP, #8] |
0x416a80 LDP X15, X13, [X2, #152] |
0x416a84 STP X8, X9, [SP, #56] |
0x416a88 LDR W8, [X12] |
0x416a8c STUR X13, [X29, #456] |
0x416a90 LDP X13, X28, [X2, #168] |
0x416a94 STP X15, X14, [X29, #976] |
0x416a98 STR W8, [SP, #36] |
0x416a9c STUR X13, [X29, #448] |
0x416aa0 BL 410140 |
0x416aa4 LDP X8, X10, [SP, #40] |
0x416aa8 ORR W1, WZR, W0 |
0x416aac STR W0, [SP, #32] |
0x416ab0 LDR W9, [X10] |
0x416ab4 LDR W8, [X8] |
0x416ab8 SUBS W8, W8, W9 |
0x416abc STR W9, [SP, #40] |
0x416ac0 LDR W9, [SP, #36] |
0x416ac4 CSINV W8, W8, WZR, #10 |
0x416ac8 CBZ W9, 416e80 |
0x416acc STP W8, WZR, [X29, #500] |
0x416ad0 MOVZ W8, #1 |
0x416ad4 ADRP X0, |
0x416ad8 ADD X0, X0, #3368 |
0x416adc SUB X3, X29, #4 |
0x416ae0 STR WZR, [SP] |
0x416ae4 SUB X4, X29, #8 |
0x416ae8 SUB X5, X29, #12 |
0x416aec SUB X6, X29, #16 |
0x416af0 MOVZ W2, #34 |
0x416af4 STUR W8, [X29, #496] |
0x416af8 MOVZ W7, #1 |
0x416afc BL 4101b0 |
0x416b00 LDP W8, W11, [X29, #500] |
0x416b04 LDUR X30, [X29, #472] |
0x416b08 SUB W8, W8, W11 |
0x416b0c CMN W8, #1 |
0x416b10 B.EQ 416e60 |
0x416b14 LDP X10, X9, [SP, #16] |
0x416b18 LDR W9, [X9] |
0x416b1c LDR W14, [X10] |
0x416b20 SUBS W10, W14, W9 |
0x416b24 B.LT 416e60 |
0x416b28 ADD W10, W10, #1 |
0x416b2c CBZ W10, 416e60 |
0x416b30 LDR W13, [SP, #40] |
0x416b34 CNTD X15, ALL |
0x416b38 FMOV D2, #0.2500000 |
0x416b3c FMOV D3, #0.5000000 |
0x416b40 FMOV V4.2D, #0.2500000 |
0x416b44 FMOV V5.2D, #0.5000000 |
0x416b48 FMOV D6, #-1.0000000 |
0x416b4c PTRUE P1.D, ALL |
0x416b50 FDUP Z7.D, #80 |
0x416b54 FDUP Z16.D, #96 |
0x416b58 FDUP Z17.D, #112 |
0x416b5c ORR W12, WZR, WZR |
0x416b60 SUBS W16, W10, W15 |
0x416b64 CSEL W16, WZR, W16, #3 |
0x416b68 WHILELO P0.D, WZR, W10 |
0x416b6c ADD W11, W11, W13 |
0x416b70 STR W11, [SP, #48] |
0x416b74 LDR X11, [SP, #8] |
0x416b78 LDR D0, [X11] |
0x416b7c ADD W11, W14, #1 |
0x416b80 LDUR X14, [X29, #448] |
0x416b84 DUP Z1.D, Z0.D[0] |
0x416b88 STR W11, [SP, #40] |
0x416b8c B 416bac |
0x416b90 HINT #0 |
0x416b94 HINT #0 |
0x416b98 HINT #0 |
0x416b9c HINT #0 |
(46) 0x416ba0 CMP W12, W8 |
(46) 0x416ba4 ADD W12, W12, #1 |
(46) 0x416ba8 B.EQ 416e60 |
(46) 0x416bac LDR W11, [SP, #48] |
(46) 0x416bb0 SUB X3, XZR, X15 |
(46) 0x416bb4 ORR P2.B, P0/Z, P0.B, P0.B |
(46) 0x416bb8 ORR W2, WZR, W9 |
(46) 0x416bbc ADD W18, W11, W12 |
(46) 0x416bc0 LDP X13, X11, [SP, #64] |
(46) 0x416bc4 SBFM X17, X18, #0, #31 |
(46) 0x416bc8 ADD W18, W18, #1 |
(46) 0x416bcc SBFM X18, X18, #0, #31 |
(46) 0x416bd0 SUB X0, X17, X13 |
(46) 0x416bd4 SUB X1, X18, X13 |
(46) 0x416bd8 LDR W13, [SP, #40] |
(46) 0x416bdc MUL X17, X0, X11 |
(46) 0x416be0 MUL X18, X1, X11 |
(46) 0x416be4 LDR X11, [SP, #56] |
(46) 0x416be8 MUL X0, X0, X11 |
(46) 0x416bec MUL X1, X1, X11 |
(46) 0x416bf0 ADD W11, W9, #1 |
(46) 0x416bf4 CMP W13, W11 |
(46) 0x416bf8 LDP X11, X13, [X29, #968] |
(46) 0x416bfc ADD X1, X22, X1,LSL #3 |
(46) 0x416c00 B.GE 416d40 |
(46) 0x416c04 ORR W2, WZR, WZR |
(45) 0x416c08 ADD W3, W9, W2 |
(45) 0x416c0c ADD W2, W2, #1 |
(45) 0x416c10 SBFM X4, X3, #0, #31 |
(45) 0x416c14 ADD W3, W3, #1 |
(45) 0x416c18 CMP W10, W2 |
(45) 0x416c1c SUB X4, X4, X25 |
(45) 0x416c20 SBFM X3, X3, #0, #31 |
(45) 0x416c24 ADD X5, X4, X17 |
(45) 0x416c28 ADD X6, X4, X18 |
(45) 0x416c2c SUB X3, X3, X25 |
(45) 0x416c30 ADD X26, X4, X0 |
(45) 0x416c34 LDR D19, [X21, X5,LSL #3] |
(45) 0x416c38 LDR D20, [X21, X6,LSL #3] |
(45) 0x416c3c ADD X7, X3, X17 |
(45) 0x416c40 ADD X3, X3, X18 |
(45) 0x416c44 LDR D18, [X20, X5,LSL #3] |
(45) 0x416c48 ADD X30, X22, X26,LSL #3 |
(45) 0x416c4c UBFM X27, X26, #61, #60 |
(45) 0x416c50 LDR D23, [X23, X3,LSL #3] |
(45) 0x416c54 FADD D21, D19, D20 |
(45) 0x416c58 FADD D19, D19, D21 |
(45) 0x416c5c LDR D21, [X21, X3,LSL #3] |
(45) 0x416c60 FADD D19, D20, D19 |
(45) 0x416c64 LDR D20, [X21, X7,LSL #3] |
(45) 0x416c68 FMUL D18, D18, D19 |
(45) 0x416c6c LDR D19, [X20, X7,LSL #3] |
(45) 0x416c70 FMUL D18, D18, D2 |
(45) 0x416c74 FADD D22, D20, D21 |
(45) 0x416c78 FADD D20, D20, D22 |
(45) 0x416c7c LDR D22, [X23, X6,LSL #3] |
(45) 0x416c80 FMUL D18, D0, D18 |
(45) 0x416c84 FADD D20, D21, D20 |
(45) 0x416c88 LDR D21, [X23, X7,LSL #3] |
(45) 0x416c8c FMUL D18, D18, D3 |
(45) 0x416c90 FMUL D19, D19, D20 |
(45) 0x416c94 LDR D20, [X23, X5,LSL #3] |
(45) 0x416c98 FADD D25, D22, D23 |
(45) 0x416c9c FMUL D19, D19, D2 |
(45) 0x416ca0 FADD D22, D22, D25 |
(45) 0x416ca4 FADD D24, D20, D21 |
(45) 0x416ca8 FMUL D19, D0, D19 |
(45) 0x416cac FADD D20, D20, D24 |
(45) 0x416cb0 FNMSUB D18, D19, D3, D18 |
(45) 0x416cb4 FADD D20, D21, D20 |
(45) 0x416cb8 FADD D21, D23, D22 |
(45) 0x416cbc LDR D22, [X1, X4,LSL #3] |
(45) 0x416cc0 LDR D23, [X14, X27] |
(45) 0x416cc4 MOV V21.D[1], V20.D[0] |
(45) 0x416cc8 LD1 {V22.D[1]}, [X30] |
(45) 0x416ccc LDUR X30, [X29, #472] |
(45) 0x416cd0 FMUL V20.2D, V22.2D, V21.2D |
(45) 0x416cd4 LDR D22, [X11, X27] |
(45) 0x416cd8 FMUL V20.2D, V20.2D, V4.2D |
(45) 0x416cdc FMUL V20.2D, V20.2D, V0.D[0] |
(45) 0x416ce0 FDIV D23, D23, D22 |
(45) 0x416ce4 FMUL V20.2D, V20.2D, V5.2D |
(45) 0x416ce8 FADD D18, D18, D20 |
(45) 0x416cec MOV D19, V20.D[1] |
(45) 0x416cf0 FSUB D18, D18, S19 |
(45) 0x416cf4 LDR D19, [X30, X27] |
(45) 0x416cf8 FADD D20, D19, D18 |
(45) 0x416cfc FDIV D21, D6, D19 |
(45) 0x416d00 FDIV D19, D19, D20 |
(45) 0x416d04 LDR D20, [X13, X27] |
(45) 0x416d08 FDIV D20, D20, D22 |
(45) 0x416d0c FADD D20, D20, D23 |
(45) 0x416d10 LDR D23, [X28, X27] |
(45) 0x416d14 FMUL D18, D20, D18 |
(45) 0x416d18 FMADD D18, D21, D18, D23 |
(45) 0x416d1c STR D18, [X19, X26,LSL #3] |
(45) 0x416d20 FMUL D18, D22, D19 |
(45) 0x416d24 STR D18, [X24, X26,LSL #3] |
(45) 0x416d28 B.HI 416c08 |
(46) 0x416d2c B 416ba0 |
0x416d30 HINT #0 |
0x416d34 HINT #0 |
0x416d38 HINT #0 |
0x416d3c HINT #0 |
(44) 0x416d40 SBFM X4, X2, #0, #31 |
(44) 0x416d44 ADD W7, W2, #1 |
(44) 0x416d48 ADD W3, W3, W15 |
(44) 0x416d4c ADD W2, W2, W15 |
(44) 0x416d50 SUB X4, X4, X25 |
(44) 0x416d54 SBFM X7, X7, #0, #31 |
(44) 0x416d58 ADD X5, X4, X17 |
(44) 0x416d5c ADD X6, X4, X18 |
(44) 0x416d60 SUB X7, X7, X25 |
(44) 0x416d64 ADD X27, X4, X0 |
(44) 0x416d68 LD1D {Z19.D}, P2/Z, [X21, X5,LSL #3] |
(44) 0x416d6c LD1D {Z20.D}, P2/Z, [X21, X6,LSL #3] |
(44) 0x416d70 ADD X26, X7, X17 |
(44) 0x416d74 ADD X7, X7, X18 |
(44) 0x416d78 LD1D {Z18.D}, P2/Z, [X20, X5,LSL #3] |
(44) 0x416d7c FADD Z21.D, Z19.D, Z20.D |
(44) 0x416d80 FADD Z19.D, Z19.D, Z21.D |
(44) 0x416d84 LD1D {Z21.D}, P2/Z, [X21, X7,LSL #3] |
(44) 0x416d88 FADD Z19.D, Z20.D, Z19.D |
(44) 0x416d8c LD1D {Z20.D}, P2/Z, [X21, X26,LSL #3] |
(44) 0x416d90 FMUL Z18.D, Z18.D, Z19.D |
(44) 0x416d94 LD1D {Z19.D}, P2/Z, [X20, X26,LSL #3] |
(44) 0x416d98 FMUL Z18.D, Z18.D, Z7.D |
(44) 0x416d9c FADD Z22.D, Z20.D, Z21.D |
(44) 0x416da0 FADD Z20.D, Z20.D, Z22.D |
(44) 0x416da4 LD1D {Z22.D}, P2/Z, [X23, X26,LSL #3] |
(44) 0x416da8 FMUL Z18.D, Z1.D, Z18.D |
(44) 0x416dac FADD Z20.D, Z21.D, Z20.D |
(44) 0x416db0 LD1D {Z21.D}, P2/Z, [X23, X5,LSL #3] |
(44) 0x416db4 FMUL Z18.D, P1/M, Z18.D, #0.0000000 |
(44) 0x416db8 FMUL Z19.D, Z19.D, Z20.D |
(44) 0x416dbc LD1D {Z20.D}, P2/Z, [X22, X27,LSL #3] |
(44) 0x416dc0 FMUL Z19.D, Z19.D, Z7.D |
(44) 0x416dc4 FADD Z23.D, Z21.D, Z22.D |
(44) 0x416dc8 FADD Z21.D, Z21.D, Z23.D |
(44) 0x416dcc LD1D {Z23.D}, P2/Z, [X23, X7,LSL #3] |
(44) 0x416dd0 FMUL Z19.D, Z1.D, Z19.D |
(44) 0x416dd4 FADD Z21.D, Z22.D, Z21.D |
(44) 0x416dd8 LD1D {Z22.D}, P2/Z, [X23, X6,LSL #3] |
(44) 0x416ddc FNMLS Z18.D, P1/M, Z19.D, Z16.D |
(44) 0x416de0 LD1D {Z19.D}, P2/Z, [X30, X27,LSL #3] |
(44) 0x416de4 FMUL Z20.D, Z20.D, Z21.D |
(44) 0x416de8 LD1D {Z21.D}, P2/Z, [X1, X4,LSL #3] |
(44) 0x416dec FMUL Z20.D, Z20.D, Z7.D |
(44) 0x416df0 FADD Z24.D, Z22.D, Z23.D |
(44) 0x416df4 FADD Z22.D, Z22.D, Z24.D |
(44) 0x416df8 LD1D {Z24.D}, P2/Z, [X14, X27,LSL #3] |
(44) 0x416dfc FMUL Z20.D, Z1.D, Z20.D |
(44) 0x416e00 FADD Z22.D, Z23.D, Z22.D |
(44) 0x416e04 LD1D {Z23.D}, P2/Z, [X11, X27,LSL #3] |
(44) 0x416e08 FMUL Z21.D, Z21.D, Z22.D |
(44) 0x416e0c LD1D {Z22.D}, P2/Z, [X13, X27,LSL #3] |
(44) 0x416e10 FMUL Z21.D, Z21.D, Z7.D |
(44) 0x416e14 FDIV Z24.D, P1/M, Z24.D, Z23.D |
(44) 0x416e18 FDIV Z22.D, P1/M, Z22.D, Z23.D |
(44) 0x416e1c FMUL Z21.D, Z1.D, Z21.D |
(44) 0x416e20 FMLA Z18.D, P1/M, Z21.D, Z16.D |
(44) 0x416e24 MOVPRFX Z21, Z17 |
(44) 0x416e28 FDIV Z21.D, P1/M, Z21.D, Z19.D |
(44) 0x416e2c FMLS Z18.D, P1/M, Z20.D, Z16.D |
(44) 0x416e30 FADD Z20.D, Z19.D, Z18.D |
(44) 0x416e34 FDIV Z19.D, P1/M, Z19.D, Z20.D |
(44) 0x416e38 FADD Z22.D, Z22.D, Z24.D |
(44) 0x416e3c FMUL Z18.D, Z22.D, Z18.D |
(44) 0x416e40 LD1D {Z22.D}, P2/Z, [X28, X27,LSL #3] |
(44) 0x416e44 FMSB Z18.D, P1/M, Z21.D, Z22.D |
(44) 0x416e48 ST1D {Z18.D}, P2, [X19, X27,LSL #3] |
(44) 0x416e4c FMUL Z18.D, Z23.D, Z19.D |
(44) 0x416e50 ST1D {Z18.D}, P2, [X24, X27,LSL #3] |
(44) 0x416e54 WHILELO P2.D, W3, W16 |
(44) 0x416e58 B.MI 416d40 |
(44) 0x416e5c B 416ba0 |
0x416e60 LDR W19, [SP, #32] |
0x416e64 ADRP X0, |
0x416e68 ADD X0, X0, #3368 |
0x416e6c ORR W1, WZR, W19 |
0x416e70 BL 410040 |
0x416e74 ADRP X0, |
0x416e78 ADD X0, X0, #3392 |
0x416e7c B 41723c |
0x416e80 STP W8, WZR, [X29, #484] |
0x416e84 MOVZ W8, #1 |
0x416e88 ADRP X0, |
0x416e8c ADD X0, X0, #3320 |
0x416e90 SUB X3, X29, #20 |
0x416e94 STR WZR, [SP] |
0x416e98 SUB X4, X29, #24 |
0x416e9c SUB X5, X29, #28 |
0x416ea0 SUB X6, X29, #32 |
0x416ea4 MOVZ W2, #34 |
0x416ea8 STUR W8, [X29, #480] |
0x416eac MOVZ W7, #1 |
0x416eb0 BL 4101b0 |
0x416eb4 LDP W8, W12, [X29, #484] |
0x416eb8 LDUR X30, [X29, #472] |
0x416ebc SUB W8, W8, W12 |
0x416ec0 CMN W8, #1 |
0x416ec4 STR W8, [SP, #48] |
0x416ec8 B.EQ 417220 |
0x416ecc LDP X8, X10, [SP, #16] |
0x416ed0 LDR W9, [X10] |
0x416ed4 LDR W14, [X8] |
0x416ed8 SUBS W10, W14, W9 |
0x416edc B.LT 417220 |
0x416ee0 ADD W10, W10, #1 |
0x416ee4 CBZ W10, 417220 |
0x416ee8 LDR W8, [SP, #40] |
0x416eec CNTD X15, ALL |
0x416ef0 FMOV D2, #0.2500000 |
0x416ef4 FMOV D3, #-1.0000000 |
0x416ef8 FDUP Z4.D, #80 |
0x416efc FDUP Z5.D, #112 |
0x416f00 ORR W11, WZR, WZR |
0x416f04 SUBS W16, W10, W15 |
0x416f08 PTRUE P1.D, ALL |
0x416f0c CSEL W16, WZR, W16, #3 |
0x416f10 WHILELO P0.D, WZR, W10 |
0x416f14 ADD W8, W12, W8 |
0x416f18 STR W8, [SP, #40] |
0x416f1c LDR X8, [SP, #8] |
0x416f20 LDR D0, [X8] |
0x416f24 ADD W8, W14, #1 |
0x416f28 LDUR X14, [X29, #456] |
0x416f2c STR W8, [SP, #36] |
0x416f30 DUP Z1.D, Z0.D[0] |
0x416f34 B 416f50 |
0x416f38 HINT #0 |
0x416f3c HINT #0 |
(42) 0x416f40 LDR W8, [SP, #48] |
(42) 0x416f44 CMP W11, W8 |
(42) 0x416f48 ADD W11, W11, #1 |
(42) 0x416f4c B.EQ 417220 |
(42) 0x416f50 LDR W8, [SP, #40] |
(42) 0x416f54 SUB X3, XZR, X15 |
(42) 0x416f58 ORR P2.B, P0/Z, P0.B, P0.B |
(42) 0x416f5c ORR W2, WZR, W9 |
(42) 0x416f60 ADD W18, W8, W11 |
(42) 0x416f64 LDP X12, X8, [SP, #64] |
(42) 0x416f68 SBFM X17, X18, #0, #31 |
(42) 0x416f6c ADD W18, W18, #1 |
(42) 0x416f70 SBFM X18, X18, #0, #31 |
(42) 0x416f74 SUB X0, X17, X12 |
(42) 0x416f78 SUB X1, X18, X12 |
(42) 0x416f7c LDR W12, [SP, #36] |
(42) 0x416f80 MUL X17, X0, X8 |
(42) 0x416f84 MUL X18, X1, X8 |
(42) 0x416f88 LDR X8, [SP, #56] |
(42) 0x416f8c MUL X0, X0, X8 |
(42) 0x416f90 MUL X1, X1, X8 |
(42) 0x416f94 ADD W8, W9, #1 |
(42) 0x416f98 CMP W12, W8 |
(42) 0x416f9c LDUR X12, [X29, #464] |
(42) 0x416fa0 LDUR X8, [X29, #448] |
(42) 0x416fa4 ADD X1, X22, X1,LSL #3 |
(42) 0x416fa8 B.GE 4170ec |
(42) 0x416fac ORR W2, WZR, WZR |
(42) 0x416fb0 HINT #0 |
(42) 0x416fb4 HINT #0 |
(42) 0x416fb8 HINT #0 |
(42) 0x416fbc HINT #0 |
(43) 0x416fc0 ADD W13, W9, W2 |
(43) 0x416fc4 ADD W2, W2, #1 |
(43) 0x416fc8 SBFM X3, X13, #0, #31 |
(43) 0x416fcc ADD W13, W13, #1 |
(43) 0x416fd0 CMP W10, W2 |
(43) 0x416fd4 SUB X3, X3, X25 |
(43) 0x416fd8 SBFM X13, X13, #0, #31 |
(43) 0x416fdc ADD X4, X3, X17 |
(43) 0x416fe0 ADD X5, X3, X18 |
(43) 0x416fe4 SUB X13, X13, X25 |
(43) 0x416fe8 ADD X7, X3, X0 |
(43) 0x416fec LDR D7, [X21, X4,LSL #3] |
(43) 0x416ff0 LDR D16, [X21, X5,LSL #3] |
(43) 0x416ff4 LDR D6, [X20, X4,LSL #3] |
(43) 0x416ff8 ADD X6, X13, X17 |
(43) 0x416ffc ADD X13, X13, X18 |
(43) 0x417000 LDR D17, [X21, X13,LSL #3] |
(43) 0x417004 LDR D18, [X23, X6,LSL #3] |
(43) 0x417008 LDR D19, [X23, X13,LSL #3] |
(43) 0x41700c FADD D7, D7, D16 |
(43) 0x417010 LDR D16, [X26, X4,LSL #3] |
(43) 0x417014 FADD D7, D7, D16 |
(43) 0x417018 LDR D16, [X26, X5,LSL #3] |
(43) 0x41701c FADD D7, D7, D16 |
(43) 0x417020 LDR D16, [X20, X6,LSL #3] |
(43) 0x417024 FMUL D6, D6, D7 |
(43) 0x417028 LDR D7, [X21, X6,LSL #3] |
(43) 0x41702c FMUL D6, D6, D2 |
(43) 0x417030 FADD D7, D7, D17 |
(43) 0x417034 LDR D17, [X26, X6,LSL #3] |
(43) 0x417038 FMUL D6, D0, D6 |
(43) 0x41703c FADD D7, D7, D17 |
(43) 0x417040 LDR D17, [X26, X13,LSL #3] |
(43) 0x417044 FADD D7, D7, D17 |
(43) 0x417048 LDR D17, [X23, X4,LSL #3] |
(43) 0x41704c FMUL D7, D16, D7 |
(43) 0x417050 LDR D16, [X22, X7,LSL #3] |
(43) 0x417054 FMUL D7, D7, D2 |
(43) 0x417058 FADD D17, D17, D18 |
(43) 0x41705c LDR D18, [X27, X4,LSL #3] |
(43) 0x417060 FNMSUB D6, D0, D7, D6 |
(43) 0x417064 LDR D7, [X30, X7,LSL #3] |
(43) 0x417068 FADD D17, D17, D18 |
(43) 0x41706c LDR D18, [X27, X6,LSL #3] |
(43) 0x417070 FADD D17, D17, D18 |
(43) 0x417074 LDR D18, [X23, X5,LSL #3] |
(43) 0x417078 FMUL D16, D16, D17 |
(43) 0x41707c LDR D17, [X1, X3,LSL #3] |
(43) 0x417080 FMUL D16, D16, D2 |
(43) 0x417084 FADD D18, D18, D19 |
(43) 0x417088 LDR D19, [X27, X5,LSL #3] |
(43) 0x41708c FADD D18, D18, D19 |
(43) 0x417090 LDR D19, [X27, X13,LSL #3] |
(43) 0x417094 FADD D18, D18, D19 |
(43) 0x417098 LDR D19, [X8, X7,LSL #3] |
(43) 0x41709c FMUL D17, D17, D18 |
(43) 0x4170a0 LDR D18, [X14, X7,LSL #3] |
(43) 0x4170a4 FMUL D17, D17, D2 |
(43) 0x4170a8 FMADD D6, D0, D17, D6 |
(43) 0x4170ac FDIV D17, D3, D7 |
(43) 0x4170b0 FDIV D19, D19, D18 |
(43) 0x4170b4 FMSUB D6, D0, D16, D6 |
(43) 0x4170b8 FADD D16, D7, D6 |
(43) 0x4170bc FDIV D7, D7, D16 |
(43) 0x4170c0 LDR D16, [X12, X7,LSL #3] |
(43) 0x4170c4 FDIV D16, D16, D18 |
(43) 0x4170c8 FADD D16, D16, D19 |
(43) 0x4170cc LDR D19, [X28, X7,LSL #3] |
(43) 0x4170d0 FMUL D6, D16, D6 |
(43) 0x4170d4 FMADD D6, D17, D6, D19 |
(43) 0x4170d8 STR D6, [X19, X7,LSL #3] |
(43) 0x4170dc FMUL D6, D18, D7 |
(43) 0x4170e0 STR D6, [X24, X7,LSL #3] |
(43) 0x4170e4 B.HI 416fc0 |
(42) 0x4170e8 B 416f40 |
(41) 0x4170ec SBFM X4, X2, #0, #31 |
(41) 0x4170f0 ADD W7, W2, #1 |
(41) 0x4170f4 ADD W3, W3, W15 |
(41) 0x4170f8 ADD W2, W2, W15 |
(41) 0x4170fc SUB X4, X4, X25 |
(41) 0x417100 SBFM X7, X7, #0, #31 |
(41) 0x417104 ADD X5, X4, X17 |
(41) 0x417108 ADD X6, X4, X18 |
(41) 0x41710c SUB X7, X7, X25 |
(41) 0x417110 ADD X13, X4, X0 |
(41) 0x417114 LD1D {Z7.D}, P2/Z, [X21, X5,LSL #3] |
(41) 0x417118 LD1D {Z16.D}, P2/Z, [X21, X6,LSL #3] |
(41) 0x41711c ADD X30, X7, X17 |
(41) 0x417120 ADD X7, X7, X18 |
(41) 0x417124 LD1D {Z6.D}, P2/Z, [X20, X5,LSL #3] |
(41) 0x417128 LD1D {Z17.D}, P2/Z, [X21, X7,LSL #3] |
(41) 0x41712c LD1D {Z18.D}, P2/Z, [X23, X30,LSL #3] |
(41) 0x417130 LD1D {Z19.D}, P2/Z, [X23, X7,LSL #3] |
(41) 0x417134 FADD Z7.D, Z7.D, Z16.D |
(41) 0x417138 LD1D {Z16.D}, P2/Z, [X26, X5,LSL #3] |
(41) 0x41713c FADD Z7.D, Z7.D, Z16.D |
(41) 0x417140 LD1D {Z16.D}, P2/Z, [X26, X6,LSL #3] |
(41) 0x417144 FADD Z7.D, Z7.D, Z16.D |
(41) 0x417148 LD1D {Z16.D}, P2/Z, [X21, X30,LSL #3] |
(41) 0x41714c FMUL Z6.D, Z6.D, Z7.D |
(41) 0x417150 LD1D {Z7.D}, P2/Z, [X20, X30,LSL #3] |
(41) 0x417154 FMUL Z6.D, Z6.D, Z4.D |
(41) 0x417158 FADD Z16.D, Z16.D, Z17.D |
(41) 0x41715c LD1D {Z17.D}, P2/Z, [X26, X30,LSL #3] |
(41) 0x417160 FMUL Z6.D, Z1.D, Z6.D |
(41) 0x417164 FADD Z16.D, Z16.D, Z17.D |
(41) 0x417168 LD1D {Z17.D}, P2/Z, [X26, X7,LSL #3] |
(41) 0x41716c FADD Z16.D, Z16.D, Z17.D |
(41) 0x417170 LD1D {Z17.D}, P2/Z, [X23, X5,LSL #3] |
(41) 0x417174 FMUL Z7.D, Z7.D, Z16.D |
(41) 0x417178 LD1D {Z16.D}, P2/Z, [X22, X13,LSL #3] |
(41) 0x41717c FMUL Z7.D, Z7.D, Z4.D |
(41) 0x417180 FADD Z17.D, Z17.D, Z18.D |
(41) 0x417184 LD1D {Z18.D}, P2/Z, [X27, X5,LSL #3] |
(41) 0x417188 FNMLS Z6.D, P1/M, Z1.D, Z7.D |
(41) 0x41718c FADD Z17.D, Z17.D, Z18.D |
(41) 0x417190 LD1D {Z18.D}, P2/Z, [X27, X30,LSL #3] |
(41) 0x417194 LDUR X30, [X29, #472] |
(41) 0x417198 LD1D {Z7.D}, P2/Z, [X30, X13,LSL #3] |
(41) 0x41719c FADD Z17.D, Z17.D, Z18.D |
(41) 0x4171a0 LD1D {Z18.D}, P2/Z, [X23, X6,LSL #3] |
(41) 0x4171a4 FMUL Z16.D, Z16.D, Z17.D |
(41) 0x4171a8 LD1D {Z17.D}, P2/Z, [X1, X4,LSL #3] |
(41) 0x4171ac FMUL Z16.D, Z16.D, Z4.D |
(41) 0x4171b0 FADD Z18.D, Z18.D, Z19.D |
(41) 0x4171b4 LD1D {Z19.D}, P2/Z, [X27, X6,LSL #3] |
(41) 0x4171b8 FADD Z18.D, Z18.D, Z19.D |
(41) 0x4171bc LD1D {Z19.D}, P2/Z, [X27, X7,LSL #3] |
(41) 0x4171c0 FADD Z18.D, Z18.D, Z19.D |
(41) 0x4171c4 LD1D {Z19.D}, P2/Z, [X8, X13,LSL #3] |
(41) 0x4171c8 FMUL Z17.D, Z17.D, Z18.D |
(41) 0x4171cc LD1D {Z18.D}, P2/Z, [X14, X13,LSL #3] |
(41) 0x4171d0 FMUL Z17.D, Z17.D, Z4.D |
(41) 0x4171d4 FMLA Z6.D, P1/M, Z1.D, Z17.D |
(41) 0x4171d8 LD1D {Z17.D}, P2/Z, [X12, X13,LSL #3] |
(41) 0x4171dc FDIV Z19.D, P1/M, Z19.D, Z18.D |
(41) 0x4171e0 FMLS Z6.D, P1/M, Z1.D, Z16.D |
(41) 0x4171e4 FDIV Z17.D, P1/M, Z17.D, Z18.D |
(41) 0x4171e8 FADD Z16.D, Z7.D, Z6.D |
(41) 0x4171ec FADD Z17.D, Z17.D, Z19.D |
(41) 0x4171f0 MOVPRFX Z19, Z5 |
(41) 0x4171f4 FDIV Z19.D, P1/M, Z19.D, Z7.D |
(41) 0x4171f8 FDIV Z7.D, P1/M, Z7.D, Z16.D |
(41) 0x4171fc FMUL Z6.D, Z17.D, Z6.D |
(41) 0x417200 LD1D {Z17.D}, P2/Z, [X28, X13,LSL #3] |
(41) 0x417204 FMSB Z6.D, P1/M, Z19.D, Z17.D |
(41) 0x417208 ST1D {Z6.D}, P2, [X19, X13,LSL #3] |
(41) 0x41720c FMUL Z6.D, Z18.D, Z7.D |
(41) 0x417210 ST1D {Z6.D}, P2, [X24, X13,LSL #3] |
(41) 0x417214 WHILELO P2.D, W3, W16 |
(41) 0x417218 B.MI 4170ec |
(42) 0x41721c B 416f40 |
0x417220 LDR W19, [SP, #32] |
0x417224 ADRP X0, |
0x417228 ADD X0, X0, #3320 |
0x41722c ORR W1, WZR, W19 |
0x417230 BL 410040 |
0x417234 ADRP X0, |
0x417238 ADD X0, X0, #3344 |
0x41723c ORR W1, WZR, W19 |
0x417240 BL 410330 |
0x417244 LDP X20, X19, [SP, #224] |
0x417248 LDP X22, X21, [SP, #208] |
0x41724c LDP X24, X23, [SP, #192] |
0x417250 LDP X26, X25, [SP, #176] |
0x417254 LDP X28, X27, [SP, #160] |
0x417258 LDP X29, X30, [SP, #144] |
0x41725c ADD SP, SP, #240 |
0x417260 RET |
0x417264 HINT #0 |
0x417268 HINT #0 |
0x41726c HINT #0 |
0x417270 HINT #0 |
0x417274 HINT #0 |
0x417278 HINT #0 |
0x41727c HINT #0 |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.42+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0
| Source file and lines | PdV_kernel.f90:69-145 |
| Module | exec |
| nb instructions | 184 |
| nb uops | 167 |
| loop length | 736 |
| used w registers | 15 |
| used x registers | 26 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 1 |
| used d registers | 4 |
| used q registers | 0 |
| used v registers | 2 |
| used z registers | 7 |
| nb stack references | 37 |
| micro-operation queue | 20.88 cycles |
| front end | 20.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.50 | 8.50 | 16.75 | 16.75 | 16.75 | 16.75 | 3.50 | 3.50 | 3.50 | 3.50 | 25.00 | 25.00 | 25.00 | 14.00 | 14.00 |
| cycles | 8.50 | 8.50 | 16.75 | 16.75 | 16.75 | 16.75 | 3.50 | 3.50 | 3.50 | 3.50 | 25.00 | 25.00 | 25.00 | 14.00 | 14.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 20.88 |
| Dispatch | 25.00 |
| Overall L1 | 25.00 |
| all | 2% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 16% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| all | 3% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| all | 30% |
| load | 36% |
| store | 28% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 23% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 35% |
| all | 20% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| all | 29% |
| load | 36% |
| store | 28% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 23% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 29% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB SP, SP, #240 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STP X29, X30, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X28, X27, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X26, X25, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X24, X23, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X22, X21, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X20, X19, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ADD X29, SP, #144 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDP X14, X13, [X2, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X8, X9, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADRP X0, <48aa38> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3416 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X10, [X2, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X25, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STP X13, X14, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDP X14, X13, [X2, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X11, X12, [X2, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR X8, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X20, X21, [X2, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STP X13, X14, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDP X26, X13, [X2, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STR X8, [SP, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X8, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X27, X14, [X2, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X22, X23, [X2, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X19, X24, [X2, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STR X13, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDP X15, X13, [X2, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STP X8, X9, [SP, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDR W8, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STUR X13, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDP X13, X28, [X2, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STP X15, X14, [X29, #976] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STR W8, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| STUR X13, [X29, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| BL 410140 <@plt_start@+0x120> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X8, X10, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ORR W1, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| STR W0, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR W9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| SUBS W8, W8, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| STR W9, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR W9, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CSINV W8, W8, WZR, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBZ W9, 416e80 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STP W8, WZR, [X29, #500] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADRP X0, <48aad4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3368 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X3, X29, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR WZR, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| SUB X4, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X5, X29, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X6, X29, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STUR W8, [X29, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 4101b0 <@plt_start@+0x190> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP W8, W11, [X29, #500] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDUR X30, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| SUB W8, W8, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMN W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.EQ 416e60 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X10, X9, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W14, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUBS W10, W14, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LT 416e60 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W10, W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBZ W10, 416e60 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR W13, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| CNTD X15, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| FMOV D2, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMOV D3, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMOV V4.2D, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (50.0%) |
| FMOV V5.2D, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (50.0%) |
| FMOV D6, #-1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| PTRUE P1.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| FDUP Z7.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| FDUP Z16.D, #96 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| FDUP Z17.D, #112 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| ORR W12, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUBS W16, W10, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSEL W16, WZR, W16, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| WHILELO P0.D, WZR, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| ADD W11, W11, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR W11, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR X11, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D0, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD W11, W14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDUR X14, [X29, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| DUP Z1.D, Z0.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| STR W11, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 416bac <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x19c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| LDR W19, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| ADRP X0, <48ae64> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3368 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ORR W1, WZR, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 410040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADRP X0, <48ae74> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3392 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| B 41723c <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x82c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STP W8, WZR, [X29, #484] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADRP X0, <48ae88> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3320 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X3, X29, #20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR WZR, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| SUB X4, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X5, X29, #28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X6, X29, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STUR W8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 4101b0 <@plt_start@+0x190> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP W8, W12, [X29, #484] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDUR X30, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| SUB W8, W8, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMN W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| STR W8, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B.EQ 417220 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x810> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X8, X10, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W14, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUBS W10, W14, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LT 417220 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x810> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W10, W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBZ W10, 417220 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x810> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR W8, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CNTD X15, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| FMOV D2, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMOV D3, #-1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FDUP Z4.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| FDUP Z5.D, #112 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| ORR W11, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUBS W16, W10, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| PTRUE P1.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| CSEL W16, WZR, W16, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| WHILELO P0.D, WZR, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| ADD W8, W12, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR W8, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR X8, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D0, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD W8, W14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDUR X14, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR W8, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| DUP Z1.D, Z0.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| B 416f50 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x540> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| LDR W19, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| ADRP X0, <48a224> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3320 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ORR W1, WZR, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 410040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADRP X0, <48a234> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3344 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ORR W1, WZR, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 410330 <@plt_start@+0x310> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X20, X19, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X22, X21, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X24, X23, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X26, X25, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X28, X27, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X29, X30, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADD SP, SP, #240 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A |
The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0
| Source file and lines | PdV_kernel.f90:69-145 |
| Module | exec |
| nb instructions | 184 |
| nb uops | 167 |
| loop length | 736 |
| used w registers | 15 |
| used x registers | 26 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 1 |
| used d registers | 4 |
| used q registers | 0 |
| used v registers | 2 |
| used z registers | 7 |
| nb stack references | 37 |
| micro-operation queue | 20.88 cycles |
| front end | 20.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.50 | 8.50 | 16.75 | 16.75 | 16.75 | 16.75 | 3.50 | 3.50 | 3.50 | 3.50 | 25.00 | 25.00 | 25.00 | 14.00 | 14.00 |
| cycles | 8.50 | 8.50 | 16.75 | 16.75 | 16.75 | 16.75 | 3.50 | 3.50 | 3.50 | 3.50 | 25.00 | 25.00 | 25.00 | 14.00 | 14.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 20.88 |
| Dispatch | 25.00 |
| Overall L1 | 25.00 |
| all | 2% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 16% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| all | 3% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| all | 30% |
| load | 36% |
| store | 28% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 23% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 35% |
| all | 20% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| all | 29% |
| load | 36% |
| store | 28% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 23% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 29% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB SP, SP, #240 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STP X29, X30, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X28, X27, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X26, X25, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X24, X23, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X22, X21, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X20, X19, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ADD X29, SP, #144 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDP X14, X13, [X2, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X8, X9, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADRP X0, <48aa38> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3416 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X10, [X2, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X25, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STP X13, X14, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDP X14, X13, [X2, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X11, X12, [X2, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR X8, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X20, X21, [X2, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STP X13, X14, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDP X26, X13, [X2, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STR X8, [SP, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X8, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X27, X14, [X2, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X22, X23, [X2, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X19, X24, [X2, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STR X13, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDP X15, X13, [X2, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STP X8, X9, [SP, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDR W8, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STUR X13, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDP X13, X28, [X2, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| STP X15, X14, [X29, #976] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STR W8, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| STUR X13, [X29, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| BL 410140 <@plt_start@+0x120> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X8, X10, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ORR W1, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| STR W0, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR W9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| SUBS W8, W8, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| STR W9, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR W9, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CSINV W8, W8, WZR, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBZ W9, 416e80 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x470> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STP W8, WZR, [X29, #500] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADRP X0, <48aad4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3368 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X3, X29, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR WZR, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| SUB X4, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X5, X29, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X6, X29, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STUR W8, [X29, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 4101b0 <@plt_start@+0x190> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP W8, W11, [X29, #500] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDUR X30, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| SUB W8, W8, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMN W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.EQ 416e60 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X10, X9, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W9, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W14, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUBS W10, W14, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LT 416e60 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W10, W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBZ W10, 416e60 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR W13, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| CNTD X15, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| FMOV D2, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMOV D3, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMOV V4.2D, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (50.0%) |
| FMOV V5.2D, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (50.0%) |
| FMOV D6, #-1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| PTRUE P1.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| FDUP Z7.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| FDUP Z16.D, #96 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| FDUP Z17.D, #112 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| ORR W12, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUBS W16, W10, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSEL W16, WZR, W16, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| WHILELO P0.D, WZR, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| ADD W11, W11, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR W11, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR X11, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D0, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD W11, W14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDUR X14, [X29, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| DUP Z1.D, Z0.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| STR W11, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 416bac <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x19c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| LDR W19, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| ADRP X0, <48ae64> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3368 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ORR W1, WZR, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 410040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADRP X0, <48ae74> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3392 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| B 41723c <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x82c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STP W8, WZR, [X29, #484] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADRP X0, <48ae88> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3320 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X3, X29, #20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR WZR, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| SUB X4, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X5, X29, #28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X6, X29, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STUR W8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 4101b0 <@plt_start@+0x190> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP W8, W12, [X29, #484] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDUR X30, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| SUB W8, W8, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMN W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| STR W8, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B.EQ 417220 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x810> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X8, X10, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W14, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUBS W10, W14, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| B.LT 417220 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x810> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W10, W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBZ W10, 417220 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x810> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR W8, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| CNTD X15, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| FMOV D2, #0.2500000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMOV D3, #-1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FDUP Z4.D, #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| FDUP Z5.D, #112 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (3.1%) |
| ORR W11, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUBS W16, W10, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| PTRUE P1.D, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| CSEL W16, WZR, W16, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| WHILELO P0.D, WZR, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| ADD W8, W12, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR W8, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR X8, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR D0, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| ADD W8, W14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDUR X14, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR W8, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| DUP Z1.D, Z0.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| B 416f50 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x540> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| LDR W19, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| ADRP X0, <48a224> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3320 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ORR W1, WZR, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 410040 <@plt_start@+0x20> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADRP X0, <48a234> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X0, X0, #3344 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ORR W1, WZR, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 410330 <@plt_start@+0x310> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X20, X19, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X22, X21, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X24, X23, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X26, X25, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X28, X27, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X29, X30, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADD SP, SP, #240 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A | ||||||||||||||||||
| HINT #0 | N/A |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼_QMpdv_kernel_modulePpdv_kernel..omp_par– | 14.30 | 19.53 |
| ▼Loop 44 - PdV_kernel.f90:71-99 - exec– | 6.38 | 8.71 |
| ▼Loop 46 - PdV_kernel.f90:71-99 - exec– | 0.00 | 0.02 |
| ○Loop 45 - PdV_kernel.f90:74-99 - exec | 0.00 | 0.00 |
| ▼Loop 42 - PdV_kernel.f90:107-135 - exec– | 0.00 | 0.02 |
| ○Loop 41 - PdV_kernel.f90:110-135 - exec | 7.91 | 10.80 |
| ○Loop 43 - PdV_kernel.f90:110-135 - exec | 0.00 | 0.00 |