OV - exec - Function _QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp

	Function: _QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par	Module: exec	Source: :0-0 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.02%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 30 - 167

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30:   SUBROUTINE generate_chunk_kernel(x_min,x_max,y_min,y_max, &

[...]

86:     !$OMP DO

87:     DO k=y_min-2,y_max+2

88:     !$OMP SIMD

89:       DO j=x_min-2,x_max+2

90:         energy0(j,k)=state_energy(1)

91:       ENDDO

92:     ENDDO

93:     !$OMP END DO

94:     !$OMP DO

95:     DO k=y_min-2,y_max+2

96:     !$OMP SIMD

97:       DO j=x_min-2,x_max+2

98:         density0(j,k)=state_density(1)

99:       ENDDO

100:     ENDDO

101:     !$OMP END DO

102:     !$OMP DO

103:     DO k=y_min-2,y_max+2

104:     !$OMP SIMD

105:       DO j=x_min-2,x_max+2

106:         xvel0(j,k)=state_xvel(1)

107:       ENDDO

108:     ENDDO

109:     !$OMP END DO

110:     !$OMP DO

111:     DO k=y_min-2,y_max+2

112:     !$OMP SIMD

113:       DO j=x_min-2,x_max+2

114:         yvel0(j,k)=state_yvel(1)

115:       ENDDO

116:     ENDDO

117:     !$OMP END DO

118:

119:     DO state=2,number_of_states

120:

121:       ! Could the velocity setting be thread unsafe?

122:       x_cent=state_xmin(state)

123:       y_cent=state_ymin(state)

124:

125:       !$OMP DO PRIVATE(radius,jt,kt)

126:       DO k=y_min-2,y_max+2

127:       !$OMP SIMD

128:         DO j=x_min-2,x_max+2

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

[...]

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

145:               energy0(j,k)=state_energy(state)

146:               density0(j,k)=state_density(state)

147:               DO kt=k,k+1

148:                 DO jt=j,j+1

149:                   xvel0(jt,kt)=state_xvel(state)

150:                   yvel0(jt,kt)=state_yvel(state)

151:                 ENDDO

152:               ENDDO

153:             ENDIF

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

156:               energy0(j,k)=state_energy(state)

157:               density0(j,k)=state_density(state)

158:               DO kt=k,k+1

159:                 DO jt=j,j+1

160:                   xvel0(jt,kt)=state_xvel(state)

161:                   yvel0(jt,kt)=state_yvel(state)

[...]

167:       ENDDO

0x423dd0 SUB	SP, SP, #432

0x423dd4 STP	X29, X30, [SP, #336]

0x423dd8 STP	X28, X27, [SP, #352]

0x423ddc STP	X26, X25, [SP, #368]

0x423de0 STP	X24, X23, [SP, #384]

0x423de4 STP	X22, X21, [SP, #400]

0x423de8 STP	X20, X19, [SP, #416]

0x423dec ADD	X29, SP, #336

0x423df0 LDP	X23, X15, [X2, #72]

0x423df4 LDR	X14, [X2, #88]

0x423df8 MOVZ	W21, #1

0x423dfc ADRP	X0,

0x423e00 ADD	X0, X0, #3424

0x423e04 LDR	X10, [X2, #24]

0x423e08 LDR	X11, [X2, #40]

0x423e0c LDP	X12, X13, [X2, #56]

0x423e10 STP	X14, X15, [SP, #144]

0x423e14 LDP	X15, X14, [X2, #96]

0x423e18 LDP	X8, X9, [X2, #8]

0x423e1c STP	X13, X12, [SP, #160]

0x423e20 LDR	W12, [X12]

0x423e24 LDR	W13, [X13]

0x423e28 SUB	W25, W12, #2

0x423e2c STP	X15, X14, [SP, #128]

0x423e30 LDR	X20, [X8]

0x423e34 LDP	X15, X14, [X2, #112]

0x423e38 LDR	X8, [X9]

0x423e3c ADD	W12, W13, #2

0x423e40 STUR	X8, [X29, #400]

0x423e44 LDR	X8, [X10]

0x423e48 SUBS	W12, W12, W25

0x423e4c STUR	W21, [X29, #424]

0x423e50 CSINV	W12, W12, WZR, #10

0x423e54 STP	W12, WZR, [X29, #428]

0x423e58 LDP	X22, X12, [X2, #240]

0x423e5c STP	X14, X15, [SP, #96]

0x423e60 LDP	X15, X14, [X2, #128]

0x423e64 STUR	X8, [X29, #416]

0x423e68 LDR	X8, [X11]

0x423e6c STUR	X12, [X29, #360]

0x423e70 LDR	X12, [X2, #272]

0x423e74 STP	X14, X15, [SP, #48]

0x423e78 LDP	X15, X14, [X2, #144]

0x423e7c STUR	X8, [X29, #392]

0x423e80 STR	X14, [SP, #16]

0x423e84 LDP	X28, X14, [X2, #160]

0x423e88 STR	X15, [SP, #40]

0x423e8c STUR	X14, [X29, #368]

0x423e90 LDP	X15, X14, [X2, #176]

0x423e94 STR	X15, [SP, #88]

0x423e98 STUR	X14, [X29, #384]

0x423e9c LDP	X15, X14, [X2, #192]

0x423ea0 STR	X15, [SP, #80]

0x423ea4 STUR	X14, [X29, #376]

0x423ea8 LDP	X15, X27, [X2, #208]

0x423eac LDP	X14, X24, [X2, #224]

0x423eb0 STP	X14, X15, [SP, #64]

0x423eb4 LDP	X13, X14, [X2, #256]

0x423eb8 STR	X13, [SP, #8]

0x423ebc STP	X12, X14, [SP, #24]

0x423ec0 BL	410140

0x423ec4 ORR	W19, WZR, W0

0x423ec8 ADRP	X0,

0x423ecc ADD	X0, X0, #3184

0x423ed0 SUB	X3, X29, #76

0x423ed4 SUB	X4, X29, #80

0x423ed8 STR	WZR, [SP]

0x423edc ORR	W1, WZR, W19

0x423ee0 SUB	X5, X29, #84

0x423ee4 SUB	X6, X29, #88

0x423ee8 MOVZ	W2, #34

0x423eec MOVZ	W7, #1

0x423ef0 BL	4101b0

0x423ef4 LDP	W8, W12, [X29, #428]

0x423ef8 SUB	W8, W8, W12

0x423efc CMN	W8, #1

0x423f00 B.EQ	42401c

0x423f04 LDP	X10, X9, [SP, #96]

0x423f08 LDR	W17, [X9]

0x423f0c LDR	W18, [X10]

0x423f10 SUB	W9, W17, #2

0x423f14 ADD	W10, W18, #2

0x423f18 CMP	W10, W9

0x423f1c B.LT	42401c

0x423f20 SUB	W10, W18, W17

0x423f24 ADD	W10, W10, #5

0x423f28 CBZ	W10, 42401c

0x423f2c LDR	X13, [SP, #88]

0x423f30 ADD	W14, W18, #2

0x423f34 CNTD	X15, ALL

0x423f38 SUB	W17, W17, W18

0x423f3c ADD	W12, W12, W25

0x423f40 ORR	W11, WZR, WZR

0x423f44 SUB	W17, W17, #5

0x423f48 PTRUE	P0.D, ALL

0x423f4c LDR	D0, [X13]

0x423f50 CNTW	X13, ALL

0x423f54 CMP	W10, W13

0x423f58 SUB	W16, WZR, W13

0x423f5c CCMP	W14, W9, #8, #2

0x423f60 AND	W16, W10, W16

0x423f64 CSINC	W14, WZR, WZR, #10

0x423f68 DUP	Z1.D, Z0.D[0]

0x423f6c B	423f8c

0x423f70 HINT	#0

0x423f74 HINT	#0

0x423f78 HINT	#0

0x423f7c HINT	#0

  (312) 0x423f80 CMP	W11, W8

  (312) 0x423f84 ADD	W11, W11, #1

  (312) 0x423f88 B.EQ	42401c

  (312) 0x423f8c LDUR	X0, [X29, #416]

  (312) 0x423f90 ADD	W18, W12, W11

  (312) 0x423f94 SBFM	X18, X18, #0, #31

  (312) 0x423f98 SUB	X18, X18, X0

  (312) 0x423f9c LDP	X0, X1, [X29, #896]

  (312) 0x423fa0 MUL	X18, X18, X1

  (312) 0x423fa4 ADD	X18, X0, X18,LSL #3

  (312) 0x423fa8 TBZ	W14, #0, 423fc0

  (312) 0x423fac ORR	W1, WZR, WZR

  (312) 0x423fb0 B	423ff4

0x423fb4 HINT	#0

0x423fb8 HINT	#0

0x423fbc HINT	#0

(310) 0x423fc0 ORR	W0, WZR, WZR

  (306) 0x423fc4 ADD	W1, W9, W0

  (306) 0x423fc8 ADD	W0, W0, W13

  (306) 0x423fcc SBFM	X1, X1, #0, #31

  (306) 0x423fd0 CMP	W16, W0

  (306) 0x423fd4 SUB	X1, X1, X20

  (306) 0x423fd8 ADD	X2, X18, X1,LSL #3

  (306) 0x423fdc ST1D	{Z1.D}, P0, [X18, X1,LSL #3]

  (306) 0x423fe0 ST1D	{Z1.D}, P0, [X2, X15,LSL #3]

  (306) 0x423fe4 B.NE	423fc4

(310) 0x423fe8 CMP	W10, W16

(310) 0x423fec ORR	W1, WZR, W16

(310) 0x423ff0 B.EQ	423f80

  (312) 0x423ff4 ADD	W0, W17, W1

  (312) 0x423ff8 ADD	W1, W9, W1

  (312) 0x423ffc HINT	#0

    (311) 0x424000 SBFM	X2, X1, #0, #31

    (311) 0x424004 ADDS	W0, W0, #1

    (311) 0x424008 ADD	W1, W1, #1

    (311) 0x42400c SUB	X2, X2, X20

    (311) 0x424010 STR	D0, [X18, X2,LSL #3]

    (311) 0x424014 B.CC	424000

  (312) 0x424018 B	423f80

0x42401c ADRP	X0,

0x424020 ADD	X0, X0, #3184

0x424024 ORR	W1, WZR, W19

0x424028 BL	410040

0x42402c ADRP	X0,

0x424030 ADD	X0, X0, #3208

0x424034 ORR	W1, WZR, W19

0x424038 BL	410330

0x42403c LDR	X8, [SP, #168]

0x424040 ADRP	X0,

0x424044 ADD	X0, X0, #3232

0x424048 SUB	X3, X29, #60

0x42404c SUB	X4, X29, #64

0x424050 ORR	W1, WZR, W19

0x424054 LDR	W8, [X8]

0x424058 SUB	X5, X29, #68

0x42405c SUB	X6, X29, #72

0x424060 MOVZ	W2, #34

0x424064 MOVZ	W7, #1

0x424068 SUB	W25, W8, #2

0x42406c LDR	X8, [SP, #160]

0x424070 LDR	W8, [X8]

0x424074 STUR	W21, [X29, #440]

0x424078 STR	WZR, [SP]

0x42407c ADD	W8, W8, #2

0x424080 SUBS	W8, W8, W25

0x424084 CSINV	W8, W8, WZR, #10

0x424088 STP	W8, WZR, [X29, #444]

0x42408c BL	4101b0

0x424090 LDP	W8, W12, [X29, #444]

0x424094 SUB	W8, W8, W12

0x424098 CMN	W8, #1

0x42409c B.EQ	42419c

0x4240a0 LDP	X10, X9, [SP, #96]

0x4240a4 LDR	W17, [X9]

0x4240a8 LDR	W18, [X10]

0x4240ac SUB	W9, W17, #2

0x4240b0 ADD	W10, W18, #2

0x4240b4 CMP	W10, W9

0x4240b8 B.LT	42419c

0x4240bc SUB	W10, W18, W17

0x4240c0 ADD	W10, W10, #5

0x4240c4 CBZ	W10, 42419c

0x4240c8 LDR	X13, [SP, #80]

0x4240cc ADD	W14, W18, #2

0x4240d0 CNTD	X15, ALL

0x4240d4 SUB	W17, W17, W18

0x4240d8 ADD	W12, W12, W25

0x4240dc ORR	W11, WZR, WZR

0x4240e0 SUB	W17, W17, #5

0x4240e4 PTRUE	P0.D, ALL

0x4240e8 LDR	D0, [X13]

0x4240ec CNTW	X13, ALL

0x4240f0 CMP	W10, W13

0x4240f4 SUB	W16, WZR, W13

0x4240f8 CCMP	W14, W9, #8, #2

0x4240fc AND	W16, W10, W16

0x424100 CSINC	W14, WZR, WZR, #10

0x424104 DUP	Z1.D, Z0.D[0]

0x424108 B	424118

(308) 0x42410c CMP	W11, W8

(308) 0x424110 ADD	W11, W11, #1

(308) 0x424114 B.EQ	42419c

(308) 0x424118 LDUR	X0, [X29, #416]

(308) 0x42411c ADD	W18, W12, W11

(308) 0x424120 SBFM	X18, X18, #0, #31

(308) 0x424124 SUB	X18, X18, X0

(308) 0x424128 LDUR	X0, [X29, #392]

(308) 0x42412c MUL	X18, X18, X0

(308) 0x424130 LDUR	X0, [X29, #376]

(308) 0x424134 ADD	X18, X0, X18,LSL #3

(308) 0x424138 TBZ	W14, #0, 424144

(308) 0x42413c ORR	W1, WZR, WZR

(308) 0x424140 B	424178

(308) 0x424144 ORR	W0, WZR, WZR

  (307) 0x424148 ADD	W1, W9, W0

  (307) 0x42414c ADD	W0, W0, W13

  (307) 0x424150 SBFM	X1, X1, #0, #31

  (307) 0x424154 CMP	W16, W0

  (307) 0x424158 SUB	X1, X1, X20

  (307) 0x42415c ADD	X2, X18, X1,LSL #3

  (307) 0x424160 ST1D	{Z1.D}, P0, [X18, X1,LSL #3]

  (307) 0x424164 ST1D	{Z1.D}, P0, [X2, X15,LSL #3]

  (307) 0x424168 B.NE	424148

(308) 0x42416c CMP	W10, W16

(308) 0x424170 ORR	W1, WZR, W16

(308) 0x424174 B.EQ	42410c

(308) 0x424178 ADD	W0, W17, W1

(308) 0x42417c ADD	W1, W9, W1

  (309) 0x424180 SBFM	X2, X1, #0, #31

  (309) 0x424184 ADDS	W0, W0, #1

  (309) 0x424188 ADD	W1, W1, #1

  (309) 0x42418c SUB	X2, X2, X20

  (309) 0x424190 STR	D0, [X18, X2,LSL #3]

  (309) 0x424194 B.CC	424180

(308) 0x424198 B	42410c

0x42419c ADRP	X0,

0x4241a0 ADD	X0, X0, #3232

0x4241a4 ORR	W1, WZR, W19

0x4241a8 BL	410040

0x4241ac ADRP	X0,

0x4241b0 ADD	X0, X0, #3256

0x4241b4 ORR	W1, WZR, W19

0x4241b8 BL	410330

0x4241bc LDR	X8, [SP, #168]

0x4241c0 MOVZ	W21, #1

0x4241c4 ADRP	X0,

0x4241c8 ADD	X0, X0, #3280

0x4241cc SUB	X3, X29, #44

0x4241d0 ORR	W1, WZR, W19

0x4241d4 LDR	W8, [X8]

0x4241d8 SUB	X4, X29, #48

0x4241dc SUB	X5, X29, #52

0x4241e0 SUB	X6, X29, #56

0x4241e4 MOVZ	W2, #34

0x4241e8 MOVZ	W7, #1

0x4241ec SUB	W25, W8, #2

0x4241f0 LDR	X8, [SP, #160]

0x4241f4 LDR	W8, [X8]

0x4241f8 ADD	W8, W8, #2

0x4241fc STUR	W21, [X29, #456]

0x424200 STR	WZR, [SP]

0x424204 SUBS	W8, W8, W25

0x424208 CSINV	W8, W8, WZR, #10

0x42420c STP	W8, WZR, [X29, #460]

0x424210 BL	4101b0

0x424214 LDP	W8, W12, [X29, #460]

0x424218 SUB	W8, W8, W12

0x42421c CMN	W8, #1

0x424220 B.EQ	42433c

0x424224 LDP	X10, X9, [SP, #96]

0x424228 LDR	W17, [X9]

0x42422c LDR	W18, [X10]

0x424230 SUB	W9, W17, #2

0x424234 ADD	W10, W18, #2

0x424238 CMP	W10, W9

0x42423c B.LT	42433c

0x424240 SUB	W10, W18, W17

0x424244 ADD	W10, W10, #5

0x424248 CBZ	W10, 42433c

0x42424c LDR	X13, [SP, #72]

0x424250 ADD	W14, W18, #2

0x424254 CNTD	X15, ALL

0x424258 SUB	W17, W17, W18

0x42425c ADD	W12, W12, W25

0x424260 ORR	W11, WZR, WZR

0x424264 SUB	W17, W17, #5

0x424268 PTRUE	P0.D, ALL

0x42426c LDR	D0, [X13]

0x424270 CNTW	X13, ALL

0x424274 CMP	W10, W13

0x424278 SUB	W16, WZR, W13

0x42427c CCMP	W14, W9, #8, #2

0x424280 AND	W16, W10, W16

0x424284 CSINC	W14, WZR, WZR, #10

0x424288 DUP	Z1.D, Z0.D[0]

0x42428c B	4242ac

0x424290 HINT	#0

0x424294 HINT	#0

0x424298 HINT	#0

0x42429c HINT	#0

  (305) 0x4242a0 CMP	W11, W8

  (305) 0x4242a4 ADD	W11, W11, #1

  (305) 0x4242a8 B.EQ	42433c

  (305) 0x4242ac LDUR	X0, [X29, #416]

  (305) 0x4242b0 ADD	W18, W12, W11

  (305) 0x4242b4 SBFM	X18, X18, #0, #31

  (305) 0x4242b8 SUB	X18, X18, X0

  (305) 0x4242bc LDUR	X0, [X29, #400]

  (305) 0x4242c0 MUL	X18, X18, X0

  (305) 0x4242c4 ADD	X18, X27, X18,LSL #3

  (305) 0x4242c8 TBZ	W14, #0, 4242e0

  (305) 0x4242cc ORR	W1, WZR, WZR

  (305) 0x4242d0 B	424314

0x4242d4 HINT	#0

0x4242d8 HINT	#0

0x4242dc HINT	#0

(303) 0x4242e0 ORR	W0, WZR, WZR

  (299) 0x4242e4 ADD	W1, W9, W0

  (299) 0x4242e8 ADD	W0, W0, W13

  (299) 0x4242ec SBFM	X1, X1, #0, #31

  (299) 0x4242f0 CMP	W16, W0

  (299) 0x4242f4 SUB	X1, X1, X20

  (299) 0x4242f8 ADD	X2, X18, X1,LSL #3

  (299) 0x4242fc ST1D	{Z1.D}, P0, [X18, X1,LSL #3]

  (299) 0x424300 ST1D	{Z1.D}, P0, [X2, X15,LSL #3]

  (299) 0x424304 B.NE	4242e4

(303) 0x424308 CMP	W10, W16

(303) 0x42430c ORR	W1, WZR, W16

(303) 0x424310 B.EQ	4242a0

  (305) 0x424314 ADD	W0, W17, W1

  (305) 0x424318 ADD	W1, W9, W1

  (305) 0x42431c HINT	#0

    (304) 0x424320 SBFM	X2, X1, #0, #31

    (304) 0x424324 ADDS	W0, W0, #1

    (304) 0x424328 ADD	W1, W1, #1

    (304) 0x42432c SUB	X2, X2, X20

    (304) 0x424330 STR	D0, [X18, X2,LSL #3]

    (304) 0x424334 B.CC	424320

  (305) 0x424338 B	4242a0

0x42433c ADRP	X0,

0x424340 ADD	X0, X0, #3280

0x424344 ORR	W1, WZR, W19

0x424348 BL	410040

0x42434c ADRP	X0,

0x424350 ADD	X0, X0, #3304

0x424354 ORR	W1, WZR, W19

0x424358 BL	410330

0x42435c LDR	X8, [SP, #168]

0x424360 ADRP	X0,

0x424364 ADD	X0, X0, #3328

0x424368 SUB	X3, X29, #28

0x42436c SUB	X4, X29, #32

0x424370 ORR	W1, WZR, W19

0x424374 LDR	W8, [X8]

0x424378 SUB	X5, X29, #36

0x42437c SUB	X6, X29, #40

0x424380 MOVZ	W2, #34

0x424384 MOVZ	W7, #1

0x424388 SUB	W25, W8, #2

0x42438c LDR	X8, [SP, #160]

0x424390 LDR	W8, [X8]

0x424394 STUR	W21, [X29, #472]

0x424398 STR	WZR, [SP]

0x42439c ADD	W8, W8, #2

0x4243a0 SUBS	W8, W8, W25

0x4243a4 CSINV	W8, W8, WZR, #10

0x4243a8 STP	W8, WZR, [X29, #476]

0x4243ac BL	4101b0

0x4243b0 LDP	W8, W12, [X29, #476]

0x4243b4 SUB	W8, W8, W12

0x4243b8 CMN	W8, #1

0x4243bc B.EQ	4244bc

0x4243c0 LDP	X10, X9, [SP, #96]

0x4243c4 LDR	W17, [X9]

0x4243c8 LDR	W18, [X10]

0x4243cc SUB	W9, W17, #2

0x4243d0 ADD	W10, W18, #2

0x4243d4 CMP	W10, W9

0x4243d8 B.LT	4244bc

0x4243dc SUB	W10, W18, W17

0x4243e0 ADD	W10, W10, #5

0x4243e4 CBZ	W10, 4244bc

0x4243e8 LDR	X13, [SP, #64]

0x4243ec ADD	W14, W18, #2

0x4243f0 CNTD	X15, ALL

0x4243f4 SUB	W17, W17, W18

0x4243f8 ADD	W12, W12, W25

0x4243fc ORR	W11, WZR, WZR

0x424400 SUB	W17, W17, #5

0x424404 PTRUE	P0.D, ALL

0x424408 LDR	D0, [X13]

0x42440c CNTW	X13, ALL

0x424410 CMP	W10, W13

0x424414 SUB	W16, WZR, W13

0x424418 CCMP	W14, W9, #8, #2

0x42441c AND	W16, W10, W16

0x424420 CSINC	W14, WZR, WZR, #10

0x424424 DUP	Z1.D, Z0.D[0]

0x424428 B	424438

(301) 0x42442c CMP	W11, W8

(301) 0x424430 ADD	W11, W11, #1

(301) 0x424434 B.EQ	4244bc

(301) 0x424438 LDUR	X0, [X29, #416]

(301) 0x42443c ADD	W18, W12, W11

(301) 0x424440 SBFM	X18, X18, #0, #31

(301) 0x424444 SUB	X18, X18, X0

(301) 0x424448 LDUR	X0, [X29, #400]

(301) 0x42444c MUL	X18, X18, X0

(301) 0x424450 ADD	X18, X24, X18,LSL #3

(301) 0x424454 TBZ	W14, #0, 424460

(301) 0x424458 ORR	W1, WZR, WZR

(301) 0x42445c B	424494

(301) 0x424460 ORR	W0, WZR, WZR

  (300) 0x424464 ADD	W1, W9, W0

  (300) 0x424468 ADD	W0, W0, W13

  (300) 0x42446c SBFM	X1, X1, #0, #31

  (300) 0x424470 CMP	W16, W0

  (300) 0x424474 SUB	X1, X1, X20

  (300) 0x424478 ADD	X2, X18, X1,LSL #3

  (300) 0x42447c ST1D	{Z1.D}, P0, [X18, X1,LSL #3]

  (300) 0x424480 ST1D	{Z1.D}, P0, [X2, X15,LSL #3]

  (300) 0x424484 B.NE	424464

(301) 0x424488 CMP	W10, W16

(301) 0x42448c ORR	W1, WZR, W16

(301) 0x424490 B.EQ	42442c

(301) 0x424494 ADD	W0, W17, W1

(301) 0x424498 ADD	W1, W9, W1

(301) 0x42449c HINT	#0

  (302) 0x4244a0 SBFM	X2, X1, #0, #31

  (302) 0x4244a4 ADDS	W0, W0, #1

  (302) 0x4244a8 ADD	W1, W1, #1

  (302) 0x4244ac SUB	X2, X2, X20

  (302) 0x4244b0 STR	D0, [X18, X2,LSL #3]

  (302) 0x4244b4 B.CC	4244a0

(301) 0x4244b8 B	42442c

0x4244bc ADRP	X0,

0x4244c0 ADD	X0, X0, #3328

0x4244c4 ORR	W1, WZR, W19

0x4244c8 BL	410040

0x4244cc ADRP	X0,

0x4244d0 ADD	X0, X0, #3352

0x4244d4 ORR	W1, WZR, W19

0x4244d8 BL	410330

0x4244dc LDR	W8, [X23]

0x4244e0 CMP	W8, #2

0x4244e4 STR	X8, [SP, #120]

0x4244e8 B.LT	424be0

0x4244ec CNTD	X25, ALL

0x4244f0 MOVZ	W8, #2

0x4244f4 ADRP	X0,

0x4244f8 ADD	X0, X0, #3376

0x4244fc STR	W19, [SP, #116]

0x424500 B	424544

    (289) 0x424504 LDR	W19, [SP, #116]

    (289) 0x424508 ADRP	X21,

    (289) 0x42450c ADD	X21, X21, #3376

    (289) 0x424510 ORR	X0, XZR, X21

    (289) 0x424514 ORR	W1, WZR, W19

    (289) 0x424518 BL	410040

    (289) 0x42451c ADRP	X0,

    (289) 0x424520 ADD	X0, X0, #3400

    (289) 0x424524 ORR	W1, WZR, W19

    (289) 0x424528 BL	410330

    (289) 0x42452c LDR	X8, [SP, #120]

    (289) 0x424530 LDUR	X9, [X29, #352]

    (289) 0x424534 ORR	X0, XZR, X21

    (289) 0x424538 CMP	X9, X8

    (289) 0x42453c ADD	X8, X9, #1

    (289) 0x424540 B.EQ	424be0

    (289) 0x424544 LDR	X11, [SP, #152]

    (289) 0x424548 SUB	X21, X8, #1

    (289) 0x42454c STUR	X8, [X29, #352]

    (289) 0x424550 LDP	X9, X8, [SP, #160]

    (289) 0x424554 SUB	X3, X29, #12

    (289) 0x424558 SUB	X4, X29, #16

    (289) 0x42455c UBFM	X10, X21, #61, #60

    (289) 0x424560 SUB	X5, X29, #20

    (289) 0x424564 SUB	X6, X29, #24

    (289) 0x424568 MOVZ	W2, #34

    (289) 0x42456c MOVZ	W7, #1

    (289) 0x424570 ORR	W1, WZR, W19

    (289) 0x424574 LDR	D0, [X11, X10]

    (289) 0x424578 LDR	X10, [SP, #128]

    (289) 0x42457c LDR	W8, [X8]

    (289) 0x424580 LDR	W9, [X9]

    (289) 0x424584 ADD	X26, X10, X21,LSL #3

    (289) 0x424588 SUB	W23, W8, #2

    (289) 0x42458c ADD	W8, W9, #2

    (289) 0x424590 LDP	X9, X10, [SP, #136]

    (289) 0x424594 SUBS	W8, W8, W23

    (289) 0x424598 CSINV	W8, W8, WZR, #10

    (289) 0x42459c STP	W8, WZR, [X29, #492]

    (289) 0x4245a0 MOVZ	W8, #1

    (289) 0x4245a4 STR	D0, [X10]

    (289) 0x4245a8 LDR	D0, [X26]

    (289) 0x4245ac STUR	W8, [X29, #488]

    (289) 0x4245b0 STR	D0, [X9]

    (289) 0x4245b4 STR	WZR, [SP]

    (289) 0x4245b8 BL	4101b0

    (289) 0x4245bc LDP	W8, W10, [X29, #492]

    (289) 0x4245c0 MOVI	V16.2D, #0

    (289) 0x4245c4 PTRUE	P3.D, ALL

    (289) 0x4245c8 SUB	W8, W8, W10

    (289) 0x4245cc CMN	W8, #1

    (289) 0x4245d0 STUR	W8, [X29, #412]

    (289) 0x4245d4 B.EQ	424504

    (289) 0x4245d8 LDP	X11, X9, [SP, #96]

    (289) 0x4245dc LDR	W17, [X9]

    (289) 0x4245e0 LDR	W0, [X11]

    (289) 0x4245e4 SUB	W9, W17, #2

    (289) 0x4245e8 ADD	W11, W0, #2

    (289) 0x4245ec CMP	W11, W9

    (289) 0x4245f0 B.LT	424504

    (289) 0x4245f4 SUB	W11, W0, W17

    (289) 0x4245f8 ADD	W1, W11, #5

    (289) 0x4245fc CBZ	W1, 424504

    (289) 0x424600 ADD	W23, W10, W23

    (289) 0x424604 LDP	X10, X8, [SP, #80]

    (289) 0x424608 ADD	X11, X8, X21,LSL #3

    (289) 0x42460c ADD	X12, X10, X21,LSL #3

    (289) 0x424610 LDP	X10, X8, [SP, #64]

    (289) 0x424614 ADD	X13, X8, X21,LSL #3

    (289) 0x424618 ADD	X14, X10, X21,LSL #3

    (289) 0x42461c LDP	X10, X8, [SP, #48]

    (289) 0x424620 LDR	W15, [X8, X21,LSL #2]

    (289) 0x424624 LDR	W16, [X10]

    (289) 0x424628 CMP	W15, W16

    (289) 0x42462c B.NE	424850

    (289) 0x424630 LDR	X10, [SP, #24]

    (289) 0x424634 SUB	W17, W17, #1

    (289) 0x424638 ADD	W18, W0, #3

    (289) 0x42463c ORR	W16, WZR, WZR

    (289) 0x424640 CMP	W18, W17

    (289) 0x424644 ADD	W17, W0, #2

    (289) 0x424648 SUB	W0, WZR, W0

    (289) 0x42464c CCMP	W17, W9, #8, #10

    (289) 0x424650 CSINC	W17, WZR, WZR, #10

    (289) 0x424654 SUBS	W18, W1, W25

    (289) 0x424658 ADD	X15, X10, X21,LSL #3

    (289) 0x42465c LDR	X10, [SP, #152]

    (289) 0x424660 CSEL	W18, WZR, W18, #3

    (289) 0x424664 WHILELO	P0.D, WZR, W1

    (289) 0x424668 ORR	W1, WZR, W23

    (289) 0x42466c LDR	D0, [X10, X21,LSL #3]

    (289) 0x424670 LDR	X10, [SP, #32]

    (289) 0x424674 LDR	D1, [X10, X21,LSL #3]

    (289) 0x424678 DUP	Z2.D, Z0.D[0]

    (289) 0x42467c DUP	Z3.D, Z1.D[0]

    (289) 0x424680 B	42469c

      (296) 0x424684 LDUR	W10, [X29, #412]

      (296) 0x424688 ADD	W1, W1, #1

      (296) 0x42468c ORR	W23, WZR, W8

      (296) 0x424690 CMP	W16, W10

      (296) 0x424694 ADD	W16, W16, #1

      (296) 0x424698 B.EQ	424504

      (296) 0x42469c LDUR	X7, [X29, #416]

      (296) 0x4246a0 ADD	W3, W23, W16

      (296) 0x4246a4 LDUR	X10, [X29, #368]

      (296) 0x4246a8 SBFM	X6, X1, #0, #31

      (296) 0x4246ac ORR	W8, WZR, W23

      (296) 0x4246b0 ORR	W23, WZR, W9

      (296) 0x4246b4 ADD	W2, W3, #1

      (296) 0x4246b8 SBFM	X3, X3, #0, #31

      (296) 0x4246bc SBFM	X2, X2, #0, #31

      (296) 0x4246c0 SUB	X2, X2, X7

      (296) 0x4246c4 SUB	X4, X3, X7

      (296) 0x4246c8 SUB	X6, X6, X7

      (296) 0x4246cc ADD	X2, X10, X2,LSL #3

      (296) 0x4246d0 ADD	X3, X10, X4,LSL #3

      (296) 0x4246d4 LDUR	X10, [X29, #392]

      (296) 0x4246d8 MUL	X5, X4, X10

      (296) 0x4246dc LDUR	X10, [X29, #384]

      (296) 0x4246e0 ADD	X4, X10, X5,LSL #3

      (296) 0x4246e4 LDUR	X10, [X29, #376]

      (296) 0x4246e8 ADD	X5, X10, X5,LSL #3

      (296) 0x4246ec LDUR	X10, [X29, #400]

      (296) 0x4246f0 MUL	X6, X6, X10

      (296) 0x4246f4 ADD	X7, X10, X6

      (296) 0x4246f8 CBNZ	W17, 4247bc

      (296) 0x4246fc SUB	W30, WZR, W25

      (296) 0x424700 ORR	P2.B, P0/Z, P0.B, P0.B

      (296) 0x424704 ORR	W21, WZR, W9

        (298) 0x424708 ADD	W23, W21, #1

        (298) 0x42470c SBFM	X10, X21, #0, #31

        (298) 0x424710 ADD	W30, W30, W25

        (298) 0x424714 ADD	W21, W21, W25

        (298) 0x424718 SBFM	X23, X23, #0, #31

        (298) 0x42471c SUB	X10, X10, X20

        (298) 0x424720 SUB	X23, X23, X20

        (298) 0x424724 LD1D	{Z4.D}, P2/Z, [X28, X23,LSL #3]

        (298) 0x424728 ADD	X23, X10, X6

        (298) 0x42472c FCMGE	P1.D, P3/Z, Z4.D, Z2.D

        (298) 0x424730 LD1D	{Z4.D}, P2/Z, [X28, X10,LSL #3]

        (298) 0x424734 FCMGT	P1.D, P1/Z, Z3.D, Z4.D

        (298) 0x424738 AND	P1.B, P2/Z, P2.B, P1.B

        (298) 0x42473c LD1D	{Z4.D}, P1/Z, [X2, Z16.D,LSL #3]

        (298) 0x424740 LD1D	{Z5.D}, P1/Z, [X26, Z16.D,LSL #3]

        (298) 0x424744 LD1D	{Z6.D}, P1/Z, [X3, Z16.D,LSL #3]

        (298) 0x424748 LD1D	{Z7.D}, P1/Z, [X15, Z16.D,LSL #3]

        (298) 0x42474c FCMGE	P2.D, P3/Z, Z4.D, Z5.D

        (298) 0x424750 FCMGT	P2.D, P2/Z, Z7.D, Z6.D

        (298) 0x424754 AND	P1.B, P1/Z, P1.B, P2.B

        (298) 0x424758 WHILELO	P2.D, W30, W18

        (298) 0x42475c LD1D	{Z4.D}, P1/Z, [X11, Z16.D,LSL #3]

        (298) 0x424760 ST1D	{Z4.D}, P1, [X4, X10,LSL #3]

        (298) 0x424764 LD1D	{Z4.D}, P1/Z, [X12, Z16.D,LSL #3]

        (298) 0x424768 ST1D	{Z4.D}, P1, [X5, X10,LSL #3]

        (298) 0x42476c LD1D	{Z4.D}, P1/Z, [X13, Z16.D,LSL #3]

        (298) 0x424770 LD1D	{Z5.D}, P1/Z, [X14, Z16.D,LSL #3]

        (298) 0x424774 ST1D	{Z4.D}, P1, [X27, X23,LSL #3]

        (298) 0x424778 ST1D	{Z5.D}, P1, [X24, X23,LSL #3]

        (298) 0x42477c ADD	X23, X10, #1

        (298) 0x424780 ADD	X10, X10, X7

        (298) 0x424784 ADD	X19, X23, X6

        (298) 0x424788 ST1D	{Z4.D}, P1, [X27, X19,LSL #3]

        (298) 0x42478c ST1D	{Z5.D}, P1, [X24, X19,LSL #3]

        (298) 0x424790 ADD	X19, X23, X7

        (298) 0x424794 ST1D	{Z4.D}, P1, [X27, X10,LSL #3]

        (298) 0x424798 ST1D	{Z5.D}, P1, [X24, X10,LSL #3]

        (298) 0x42479c ST1D	{Z4.D}, P1, [X27, X19,LSL #3]

        (298) 0x4247a0 ST1D	{Z5.D}, P1, [X24, X19,LSL #3]

        (298) 0x4247a4 B.MI	424708

      (296) 0x4247a8 B	424684

        (297) 0x4247ac ADD	W23, W21, #1

        (297) 0x4247b0 ADD	W10, W0, W23

        (297) 0x4247b4 CMP	W10, #3

        (297) 0x4247b8 B.EQ	424684

        (297) 0x4247bc ADD	W10, W23, #1

        (297) 0x4247c0 SBFM	X21, X23, #0, #31

        (297) 0x4247c4 SBFM	X10, X10, #0, #31

        (297) 0x4247c8 SUB	X23, X21, X20

        (297) 0x4247cc SUB	X10, X10, X20

        (297) 0x4247d0 LDR	D5, [X28, X23,LSL #3]

        (297) 0x4247d4 LDR	D4, [X28, X10,LSL #3]

        (297) 0x4247d8 FCMP	D4, D0

        (297) 0x4247dc FCCMP	D5, D1, #0, #10

        (297) 0x4247e0 B.PL	4247ac

        (297) 0x4247e4 LDR	D4, [X2]

        (297) 0x4247e8 LDR	D5, [X26]

        (297) 0x4247ec LDR	D6, [X3]

        (297) 0x4247f0 FCMP	D4, D5

        (297) 0x4247f4 LDR	D7, [X15]

        (297) 0x4247f8 FCCMP	D6, D7, #0, #10

        (297) 0x4247fc B.PL	4247ac

        (297) 0x424800 LDR	D4, [X11]

        (297) 0x424804 LDR	D5, [X12]

        (297) 0x424808 ADD	X10, X23, X6

        (297) 0x42480c STR	D4, [X4, X23,LSL #3]

        (297) 0x424810 LDR	D4, [X13]

        (297) 0x424814 STR	D5, [X5, X23,LSL #3]

        (297) 0x424818 LDR	D5, [X14]

        (297) 0x42481c STR	D4, [X27, X10,LSL #3]

        (297) 0x424820 STR	D5, [X24, X10,LSL #3]

        (297) 0x424824 ADD	X10, X23, #1

        (297) 0x424828 ADD	X19, X10, X6

        (297) 0x42482c ADD	X10, X10, X7

        (297) 0x424830 STR	D4, [X27, X19,LSL #3]

        (297) 0x424834 STR	D5, [X24, X19,LSL #3]

        (297) 0x424838 ADD	X19, X23, X7

        (297) 0x42483c STR	D4, [X27, X19,LSL #3]

        (297) 0x424840 STR	D5, [X24, X19,LSL #3]

        (297) 0x424844 STR	D4, [X27, X10,LSL #3]

        (297) 0x424848 STR	D5, [X24, X10,LSL #3]

        (297) 0x42484c B	4247ac

    (289) 0x424850 LDR	X10, [SP, #40]

    (289) 0x424854 LDR	W10, [X10]

    (289) 0x424858 CMP	W15, W10

    (289) 0x42485c B.NE	424a2c

    (289) 0x424860 LDP	X10, X8, [SP, #136]

    (289) 0x424864 ADD	W16, W0, #2

    (289) 0x424868 SUB	W18, WZR, W0

    (289) 0x42486c ORR	W15, WZR, WZR

    (289) 0x424870 ORR	W0, WZR, W23

    (289) 0x424874 LDR	D1, [X10]

    (289) 0x424878 LDR	X10, [SP, #8]

    (289) 0x42487c LDR	D0, [X8]

    (289) 0x424880 LDR	D2, [X10, X21,LSL #3]

    (289) 0x424884 SUBS	W10, W1, W25

    (289) 0x424888 CSEL	W17, WZR, W10, #3

    (289) 0x42488c WHILELO	P0.D, WZR, W1

    (289) 0x424890 DUP	Z3.D, Z0.D[0]

    (289) 0x424894 DUP	Z4.D, Z2.D[0]

    (289) 0x424898 B	4248b4

0x42489c HINT	#0

      (293) 0x4248a0 LDUR	W8, [X29, #412]

      (293) 0x4248a4 ADD	W0, W0, #1

      (293) 0x4248a8 CMP	W15, W8

      (293) 0x4248ac ADD	W15, W15, #1

      (293) 0x4248b0 B.EQ	424504

      (293) 0x4248b4 LDUR	X5, [X29, #416]

      (293) 0x4248b8 ADD	W1, W23, W15

      (293) 0x4248bc SBFM	X10, X0, #0, #31

      (293) 0x4248c0 CMP	W16, W9

      (293) 0x4248c4 SBFM	X1, X1, #0, #31

      (293) 0x4248c8 SUB	X3, X1, X5

      (293) 0x4248cc LDP	X1, X4, [X29, #896]

      (293) 0x4248d0 SUB	X10, X10, X5

      (293) 0x4248d4 ORR	W5, WZR, W9

      (293) 0x4248d8 MUL	X2, X3, X4

      (293) 0x4248dc LDUR	X4, [X29, #376]

      (293) 0x4248e0 ADD	X1, X1, X2,LSL #3

      (293) 0x4248e4 ADD	X2, X4, X2,LSL #3

      (293) 0x4248e8 LDUR	X4, [X29, #360]

      (293) 0x4248ec LDR	D5, [X4, X3,LSL #3]

      (293) 0x4248f0 LDUR	X4, [X29, #400]

      (293) 0x4248f4 MUL	X3, X10, X4

      (293) 0x4248f8 FSUB	D5, D5, S1

      (293) 0x4248fc ADD	X4, X4, X3

      (293) 0x424900 FMUL	D5, D5, D5

      (293) 0x424904 B.LT	4249b0

      (293) 0x424908 DUP	Z5.D, Z5.D[0]

      (293) 0x42490c SUB	W6, WZR, W25

      (293) 0x424910 ORR	P1.B, P0/Z, P0.B, P0.B

      (293) 0x424914 ORR	W5, WZR, W9

      (293) 0x424918 HINT	#0

      (293) 0x42491c HINT	#0

        (295) 0x424920 SBFM	X10, X5, #0, #31

        (295) 0x424924 ADD	W6, W6, W25

        (295) 0x424928 ADD	W5, W5, W25

        (295) 0x42492c SUB	X10, X10, X20

        (295) 0x424930 LD1D	{Z6.D}, P1/Z, [X22, X10,LSL #3]

        (295) 0x424934 ADD	X7, X10, X3

        (295) 0x424938 FSUB	Z6.D, Z6.D, Z3.D

        (295) 0x42493c FMAD	Z6.D, P3/M, Z6.D, Z5.D

        (295) 0x424940 FSQRT	Z6.D, P3/M, Z6.D

        (295) 0x424944 FCMGE	P1.D, P1/Z, Z4.D, Z6.D

        (295) 0x424948 LD1D	{Z6.D}, P1/Z, [X11, Z16.D,LSL #3]

        (295) 0x42494c ST1D	{Z6.D}, P1, [X1, X10,LSL #3]

        (295) 0x424950 LD1D	{Z6.D}, P1/Z, [X12, Z16.D,LSL #3]

        (295) 0x424954 ST1D	{Z6.D}, P1, [X2, X10,LSL #3]

        (295) 0x424958 LD1D	{Z6.D}, P1/Z, [X13, Z16.D,LSL #3]

        (295) 0x42495c LD1D	{Z7.D}, P1/Z, [X14, Z16.D,LSL #3]

        (295) 0x424960 ST1D	{Z6.D}, P1, [X27, X7,LSL #3]

        (295) 0x424964 ST1D	{Z7.D}, P1, [X24, X7,LSL #3]

        (295) 0x424968 ADD	X7, X10, #1

        (295) 0x42496c ADD	X10, X10, X4

        (295) 0x424970 ADD	X19, X7, X3

        (295) 0x424974 ADD	X7, X7, X4

        (295) 0x424978 ST1D	{Z6.D}, P1, [X27, X19,LSL #3]

        (295) 0x42497c ST1D	{Z7.D}, P1, [X24, X19,LSL #3]

        (295) 0x424980 ST1D	{Z6.D}, P1, [X27, X10,LSL #3]

        (295) 0x424984 ST1D	{Z7.D}, P1, [X24, X10,LSL #3]

        (295) 0x424988 ST1D	{Z6.D}, P1, [X27, X7,LSL #3]

        (295) 0x42498c ST1D	{Z7.D}, P1, [X24, X7,LSL #3]

        (295) 0x424990 WHILELO	P1.D, W6, W17

        (295) 0x424994 B.MI	424920

      (293) 0x424998 B	4248a0

0x42499c HINT	#0

        (294) 0x4249a0 ADD	W5, W5, #1

        (294) 0x4249a4 ADD	W10, W18, W5

        (294) 0x4249a8 CMP	W10, #3

        (294) 0x4249ac B.EQ	4248a0

        (294) 0x4249b0 SBFM	X10, X5, #0, #31

        (294) 0x4249b4 SUB	X6, X10, X20

        (294) 0x4249b8 LDR	D6, [X22, X6,LSL #3]

        (294) 0x4249bc FSUB	D6, D6, S0

        (294) 0x4249c0 FMADD	D6, D6, D6, D5

        (294) 0x4249c4 FSQRT	D6, D6

        (294) 0x4249c8 FCMP	D6, D2

        (294) 0x4249cc B.HI	4249a0

        (294) 0x4249d0 LDR	D6, [X11]

        (294) 0x4249d4 LDR	D7, [X12]

        (294) 0x4249d8 ORR	W10, WZR, W5

        (294) 0x4249dc SBFM	X10, X10, #0, #31

        (294) 0x4249e0 SUB	X10, X10, X20

        (294) 0x4249e4 ADD	X7, X10, X3

        (294) 0x4249e8 STR	D6, [X1, X6,LSL #3]

        (294) 0x4249ec LDR	D6, [X13]

        (294) 0x4249f0 STR	D7, [X2, X6,LSL #3]

        (294) 0x4249f4 LDR	D7, [X14]

        (294) 0x4249f8 ADD	X6, X10, #1

        (294) 0x4249fc ADD	X10, X10, X4

        (294) 0x424a00 STR	D6, [X27, X7,LSL #3]

        (294) 0x424a04 STR	D7, [X24, X7,LSL #3]

        (294) 0x424a08 ADD	X7, X6, X3

        (294) 0x424a0c STR	D6, [X27, X7,LSL #3]

        (294) 0x424a10 STR	D7, [X24, X7,LSL #3]

        (294) 0x424a14 STR	D6, [X27, X10,LSL #3]

        (294) 0x424a18 STR	D7, [X24, X10,LSL #3]

        (294) 0x424a1c ADD	X10, X6, X4

        (294) 0x424a20 STR	D6, [X27, X10,LSL #3]

        (294) 0x424a24 STR	D7, [X24, X10,LSL #3]

        (294) 0x424a28 B	4249a0

    (289) 0x424a2c LDR	X10, [SP, #16]

    (289) 0x424a30 LDR	W10, [X10]

    (289) 0x424a34 CMP	W15, W10

    (289) 0x424a38 B.NE	424504

  (290) 0x424a3c LDP	X10, X8, [SP, #136]

  (290) 0x424a40 ADD	W15, W0, #2

  (290) 0x424a44 SUB	W18, WZR, W0

  (290) 0x424a48 ORR	W16, WZR, WZR

  (290) 0x424a4c ORR	W0, WZR, W23

  (290) 0x424a50 LDR	D0, [X8]

  (290) 0x424a54 LDR	D1, [X10]

  (290) 0x424a58 SUBS	W10, W1, W25

  (290) 0x424a5c CSEL	W17, WZR, W10, #3

  (290) 0x424a60 WHILELO	P0.D, WZR, W1

  (290) 0x424a64 DUP	Z2.D, Z0.D[0]

  (290) 0x424a68 B	424a80

  (290) 0x424a6c LDUR	W8, [X29, #412]

  (290) 0x424a70 ADD	W0, W0, #1

  (290) 0x424a74 CMP	W16, W8

  (290) 0x424a78 ADD	W16, W16, #1

  (290) 0x424a7c B.EQ	424504

  (290) 0x424a80 LDUR	X1, [X29, #416]

  (290) 0x424a84 ADD	W10, W23, W16

  (290) 0x424a88 SBFM	X10, X10, #0, #31

  (290) 0x424a8c SUB	X1, X10, X1

  (290) 0x424a90 LDUR	X10, [X29, #368]

  (290) 0x424a94 LDR	D3, [X10, X1,LSL #3]

  (290) 0x424a98 FCMP	D3, D1

  (290) 0x424a9c B.NE	424a6c

  (290) 0x424aa0 LDP	X10, X4, [X29, #904]

  (290) 0x424aa4 LDUR	X3, [X29, #416]

  (290) 0x424aa8 CMP	W15, W9

  (290) 0x424aac SUB	W7, WZR, W25

  (290) 0x424ab0 ORR	P1.B, P0/Z, P0.B, P0.B

  (290) 0x424ab4 ORR	W5, WZR, W9

  (290) 0x424ab8 ORR	W6, WZR, W9

  (290) 0x424abc MUL	X10, X1, X10

  (290) 0x424ac0 LDP	X2, X1, [X29, #888]

  (290) 0x424ac4 ADD	X1, X1, X10,LSL #3

  (290) 0x424ac8 ADD	X2, X2, X10,LSL #3

  (290) 0x424acc SBFM	X10, X0, #0, #31

  (290) 0x424ad0 SUB	X10, X10, X3

  (290) 0x424ad4 MUL	X3, X10, X4

  (290) 0x424ad8 ADD	X4, X4, X3

  (290) 0x424adc B.LT	424b70

    (292) 0x424ae0 SBFM	X10, X6, #0, #31

    (292) 0x424ae4 ADD	W7, W7, W25

    (292) 0x424ae8 ADD	W6, W6, W25

    (292) 0x424aec SUB	X10, X10, X20

    (292) 0x424af0 LD1D	{Z3.D}, P1/Z, [X28, X10,LSL #3]

    (292) 0x424af4 ADD	X5, X10, X3

    (292) 0x424af8 FCMEQ	P1.D, P1/Z, Z3.D, Z2.D

    (292) 0x424afc LD1D	{Z3.D}, P1/Z, [X11, Z16.D,LSL #3]

    (292) 0x424b00 ST1D	{Z3.D}, P1, [X1, X10,LSL #3]

    (292) 0x424b04 LD1D	{Z3.D}, P1/Z, [X12, Z16.D,LSL #3]

    (292) 0x424b08 ST1D	{Z3.D}, P1, [X2, X10,LSL #3]

    (292) 0x424b0c LD1D	{Z3.D}, P1/Z, [X13, Z16.D,LSL #3]

    (292) 0x424b10 LD1D	{Z4.D}, P1/Z, [X14, Z16.D,LSL #3]

    (292) 0x424b14 ST1D	{Z3.D}, P1, [X27, X5,LSL #3]

    (292) 0x424b18 ST1D	{Z4.D}, P1, [X24, X5,LSL #3]

    (292) 0x424b1c ADD	X5, X10, #1

    (292) 0x424b20 ADD	X10, X10, X4

    (292) 0x424b24 ADD	X19, X5, X3

    (292) 0x424b28 ADD	X5, X5, X4

    (292) 0x424b2c ST1D	{Z3.D}, P1, [X27, X19,LSL #3]

    (292) 0x424b30 ST1D	{Z4.D}, P1, [X24, X19,LSL #3]

    (292) 0x424b34 ST1D	{Z3.D}, P1, [X27, X10,LSL #3]

    (292) 0x424b38 ST1D	{Z4.D}, P1, [X24, X10,LSL #3]

    (292) 0x424b3c ST1D	{Z3.D}, P1, [X27, X5,LSL #3]

    (292) 0x424b40 ST1D	{Z4.D}, P1, [X24, X5,LSL #3]

    (292) 0x424b44 WHILELO	P1.D, W7, W17

    (292) 0x424b48 B.MI	424ae0

  (290) 0x424b4c B	424a6c

0x424b50 HINT	#0

0x424b54 HINT	#0

0x424b58 HINT	#0

0x424b5c HINT	#0

(291) 0x424b60 ADD	W5, W5, #1

(291) 0x424b64 ADD	W10, W18, W5

(291) 0x424b68 CMP	W10, #3

(291) 0x424b6c B.EQ	424a6c

(291) 0x424b70 SBFM	X10, X5, #0, #31

(291) 0x424b74 SUB	X6, X10, X20

(291) 0x424b78 LDR	D3, [X28, X6,LSL #3]

(291) 0x424b7c FCMP	D3, D0

(291) 0x424b80 B.NE	424b60

(291) 0x424b84 LDR	D3, [X11]

(291) 0x424b88 LDR	D4, [X12]

(291) 0x424b8c ORR	W10, WZR, W5

(291) 0x424b90 SBFM	X10, X10, #0, #31

(291) 0x424b94 SUB	X10, X10, X20

(291) 0x424b98 ADD	X7, X10, X3

(291) 0x424b9c STR	D3, [X1, X6,LSL #3]

(291) 0x424ba0 LDR	D3, [X13]

(291) 0x424ba4 STR	D4, [X2, X6,LSL #3]

(291) 0x424ba8 LDR	D4, [X14]

(291) 0x424bac ADD	X6, X10, #1

(291) 0x424bb0 ADD	X10, X10, X4

(291) 0x424bb4 STR	D3, [X27, X7,LSL #3]

(291) 0x424bb8 STR	D4, [X24, X7,LSL #3]

(291) 0x424bbc ADD	X7, X6, X3

(291) 0x424bc0 STR	D3, [X27, X7,LSL #3]

(291) 0x424bc4 STR	D4, [X24, X7,LSL #3]

(291) 0x424bc8 STR	D3, [X27, X10,LSL #3]

(291) 0x424bcc STR	D4, [X24, X10,LSL #3]

(291) 0x424bd0 ADD	X10, X6, X4

(291) 0x424bd4 STR	D3, [X27, X10,LSL #3]

(291) 0x424bd8 STR	D4, [X24, X10,LSL #3]

(291) 0x424bdc B	424b60

0x424be0 LDP	X20, X19, [SP, #416]

0x424be4 LDP	X22, X21, [SP, #400]

0x424be8 LDP	X24, X23, [SP, #384]

0x424bec LDP	X26, X25, [SP, #368]

0x424bf0 LDP	X28, X27, [SP, #352]

0x424bf4 LDP	X29, X30, [SP, #336]

0x424bf8 ADD	SP, SP, #432

0x424bfc RET

Coverage (%)	Name	Source Location	Module
►98.40+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.60+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:50	exec
○	start	start.f90:106	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run orig_0

Source file and lines	generate_chunk_kernel.f90:30-30,generate_chunk_kernel.f90:86-137,generate_chunk_kernel.f90:143-161,generate_chunk_kernel.f90:167-167
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:30,86-137,143-161,167.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 45.50 to 4.00 cycles (11.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 45.50 to 23.62 cycles (1.93x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 13 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:125
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 51 bytes. The binary function is storing 27 bytes.

General properties

nb instructions	331
nb uops	311
loop length	1324
used w registers	18
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	2
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.88 cycles
front end	38.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.00	16.00	45.50	45.50	45.50	45.50	2.00	2.00	0.00	0.00	35.50	35.17	35.33	19.50	19.50
cycles	16.00	16.00	45.50	45.50	45.50	45.50	2.00	2.00	0.00	0.00	35.50	35.17	35.33	19.50	19.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.88
Dispatch	45.50
Overall L1	45.50

Vectorization ratios

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	26%
load	33%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 45.50 cycles. At this rate:

1% of peak load performance is reached (1.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.59 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 423dd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X15, [X2, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48bdfc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3424	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X9, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X13, X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X15, X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X14, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W12, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STUR W21, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CSINV W12, W12, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W12, WZR, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X22, X12, [X2, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X12, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X2, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X14, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X28, X14, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X14, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X14, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X14, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X14, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X15, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X14, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X27, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X14, X24, [X2, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X14, X15, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X13, X14, [X2, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X12, X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48bec8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #76	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X5, X29, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42401c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W9, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 42401c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 42401c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W14, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W17, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR D0, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB W16, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, W9, #8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W10, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
B 423f8c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <48b01c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b02c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48b040>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #68	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W25, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR W21, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #444]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #444]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42419c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W9, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 42419c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 42419c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W14, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W17, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR D0, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB W16, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, W9, #8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W10, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
B 424118 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b19c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b1ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b1c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X4, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W25, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W21, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42433c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W9, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 42433c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 42433c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W14, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W17, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR D0, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB W16, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, W9, #8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W10, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
B 4242ac <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <48b33c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b34c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48b360>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W25, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR W21, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4244bc <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W9, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4244bc <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 4244bc <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W14, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W17, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR D0, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB W16, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, W9, #8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W10, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
B 424438 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b4bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b4cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 424be0 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48b4f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W19, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424544 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x774>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run orig_0

Source file and lines	generate_chunk_kernel.f90:30-30,generate_chunk_kernel.f90:86-137,generate_chunk_kernel.f90:143-161,generate_chunk_kernel.f90:167-167
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 13 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:125
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 51 bytes. The binary function is storing 27 bytes.

General properties

nb instructions	331
nb uops	311
loop length	1324
used w registers	18
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	2
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.88 cycles
front end	38.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.00	16.00	45.50	45.50	45.50	45.50	2.00	2.00	0.00	0.00	35.50	35.17	35.33	19.50	19.50
cycles	16.00	16.00	45.50	45.50	45.50	45.50	2.00	2.00	0.00	0.00	35.50	35.17	35.33	19.50	19.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.88
Dispatch	45.50
Overall L1	45.50

Vectorization ratios

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	26%
load	33%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 45.50 cycles. At this rate:

1% of peak load performance is reached (1.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.59 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 423dd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X15, [X2, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48bdfc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3424	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X9, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X13, X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X15, X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X14, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W12, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STUR W21, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CSINV W12, W12, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W12, WZR, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X22, X12, [X2, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X12, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X2, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X14, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X28, X14, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X14, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X14, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X14, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X14, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X15, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X14, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X27, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X14, X24, [X2, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X14, X15, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X13, X14, [X2, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X12, X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48bec8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #76	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X5, X29, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42401c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W9, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 42401c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 42401c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W14, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W17, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR D0, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB W16, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, W9, #8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W10, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
B 423f8c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <48b01c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b02c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48b040>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #68	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W25, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR W21, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #444]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #444]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42419c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W9, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 42419c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 42419c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W14, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W17, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR D0, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB W16, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, W9, #8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W10, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
B 424118 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b19c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b1ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b1c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X4, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W25, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W21, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42433c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W9, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 42433c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 42433c <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W14, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W17, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR D0, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB W16, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, W9, #8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W10, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
B 4242ac <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <48b33c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b34c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48b360>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W25, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR W21, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4244bc <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W9, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4244bc <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W10, 4244bc <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W14, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W12, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W17, W17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR D0, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB W16, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, W9, #8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W10, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
B 424438 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b4bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b4cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 424be0 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48b4f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W19, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424544 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x774>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par–	0.04	0.05
▼Loop 310 - - exec–	0.00	0.00
○Loop 306 - - exec	0.00	0.00
▼Loop 312 - - exec–	0.00	0.00
○Loop 311 - - exec	0.00	0.00
▼Loop 303 - - exec–	0.00	0.00
▼Loop 305 - - exec–	0.00	0.00
○Loop 304 - - exec	0.00	0.00
○Loop 299 - - exec	0.00	0.00
▼Loop 301 - - exec–	0.00	0.00
○Loop 300 - - exec	0.00	0.00
○Loop 302 - - exec	0.00	0.00
▼Loop 308 - - exec–	0.00	0.00
○Loop 307 - - exec	0.00	0.00
○Loop 309 - - exec	0.00	0.00
▼Loop 291 - - exec–	0.00	0.00
▼Loop 290 - - exec–	0.00	0.00
○Loop 292 - - exec	0.00	0.00
▼Loop 289 - - exec–	0.00	0.00
▼Loop 293 - - exec–	0.00	0.00
○Loop 294 - - exec	0.00	0.00
○Loop 295 - - exec	0.00	0.00
▼Loop 296 - - exec–	0.00	0.00
○Loop 298 - - exec	0.01	0.01
○Loop 297 - - exec	0.00	0.00

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