OV - exec - Loop 1239

	Loop Id: 1239	Module: exec	Source: viscosity_kernel.f90:54-89	Coverage: 2.48%

0x44f2c0 ADD	W6, W4, #1

0x44f2c4 SUB	W7, W4, #1

0x44f2c8 SBFM	X30, X4, #0, #31

0x44f2cc ADD	W5, W5, W14

0x44f2d0 ADD	W4, W4, W14

0x44f2d4 SBFM	X12, X6, #0, #31

0x44f2d8 SBFM	X7, X7, #0, #31

0x44f2dc SUB	X6, X30, X28

0x44f2e0 LD1D	{Z6.D}, P2/Z, [X23, X6,LSL #3]    [3]

0x44f2e4 SUB	X12, X12, X28

0x44f2e8 SUB	X7, X7, X28

0x44f2ec LD1D	{Z18.D}, P2/Z, [X1, X6,LSL #3]    [6]

0x44f2f0 LD1D	{Z19.D}, P2/Z, [X2, X6,LSL #3]    [8]

0x44f2f4 ADD	X30, X6, X17

0x44f2f8 LD1D	{Z7.D}, P2/Z, [X0, X12,LSL #3]    [4]

0x44f2fc LD1D	{Z16.D}, P2/Z, [X0, X7,LSL #3]    [4]

0x44f300 LD1D	{Z17.D}, P2/Z, [X23, X12,LSL #3]    [3]

0x44f304 ADD	X7, X6, X16

0x44f308 ADD	X13, X12, X16

0x44f30c ADD	X12, X12, X17

0x44f310 LD1D	{Z20.D}, P2/Z, [X22, X7,LSL #3]    [2]

0x44f314 LD1D	{Z21.D}, P2/Z, [X21, X12,LSL #3]    [1]

0x44f318 LD1D	{Z22.D}, P2/Z, [X22, X13,LSL #3]    [2]

0x44f31c LD1D	{Z23.D}, P2/Z, [X21, X7,LSL #3]    [1]

0x44f320 FSUB	Z7.D, Z7.D, Z16.D

0x44f324 FADD	Z16.D, Z6.D, Z17.D

0x44f328 LD1D	{Z17.D}, P2/Z, [X22, X12,LSL #3]    [2]

0x44f32c LD1D	{Z24.D}, P2/Z, [X21, X13,LSL #3]    [1]

0x44f330 ADD	X12, X6, X18

0x44f334 FADD	Z26.D, Z20.D, Z22.D

0x44f338 FDIVR	Z16.D, P1/M, Z16.D, Z7.D

0x44f33c FSUB	Z7.D, Z18.D, Z19.D

0x44f340 LD1D	{Z18.D}, P2/Z, [X21, X30,LSL #3]    [1]

0x44f344 LD1D	{Z19.D}, P2/Z, [X22, X30,LSL #3]    [2]

0x44f348 FDIV	Z7.D, P1/M, Z7.D, Z5.D

0x44f34c FADD	Z22.D, Z17.D, Z22.D

0x44f350 FADD	Z25.D, Z19.D, Z17.D

0x44f354 FADD	Z27.D, Z21.D, Z18.D

0x44f358 FSUB	Z20.D, Z22.D, Z20.D

0x44f35c FADD	Z18.D, Z23.D, Z18.D

0x44f360 FADD	Z21.D, Z24.D, Z21.D

0x44f364 FSUB	Z17.D, Z25.D, Z26.D

0x44f368 FSUB	Z26.D, Z27.D, Z23.D

0x44f36c FSUB	Z19.D, Z20.D, Z19.D

0x44f370 FSUB	Z18.D, Z21.D, Z18.D

0x44f374 FSUB	Z22.D, Z26.D, Z24.D

0x44f378 MOVPRFX	Z20, Z17

0x44f37c FMUL	Z20.D, P1/M, Z20.D, #0.0000000

0x44f380 FMUL	Z19.D, P1/M, Z19.D, #0.0000000

0x44f384 MOVPRFX	Z21, Z18

0x44f388 FMUL	Z21.D, P1/M, Z21.D, #0.0000000

0x44f38c FMUL	Z17.D, Z4.D, Z17.D

0x44f390 FMUL	Z22.D, P1/M, Z22.D, #0.0000000

0x44f394 FDIV	Z20.D, P1/M, Z20.D, Z4.D

0x44f398 FDIV	Z19.D, P1/M, Z19.D, Z6.D

0x44f39c MOVPRFX	Z25, Z16

0x44f3a0 FABS	Z25.D, P1/M, Z16.D

0x44f3a4 MOVPRFX	Z23, Z7

0x44f3a8 FABS	Z23.D, P1/M, Z7.D

0x44f3ac FCMGT	P3.D, P1/Z, Z2.D, Z25.D

0x44f3b0 SEL	Z24.D, P3, Z2.D, Z25.D

0x44f3b4 FCMLT	P4.D, P1/Z, Z16.D, #0.0000000

0x44f3b8 FCMGT	P3.D, P1/Z, Z2.D, Z23.D

0x44f3bc FNEG	Z24.D, P4/M, Z24.D

0x44f3c0 FDIV	Z22.D, P1/M, Z22.D, Z4.D

0x44f3c4 SEL	Z23.D, P3, Z2.D, Z23.D

0x44f3c8 FMUL	Z25.D, Z24.D, Z24.D

0x44f3cc FADD	Z19.D, Z22.D, Z19.D

0x44f3d0 FCMLT	P3.D, P1/Z, Z24.D, #0.0000000

0x44f3d4 FDIV	Z21.D, P1/M, Z21.D, Z6.D

0x44f3d8 FNEG	Z23.D, P3/M, Z23.D

0x44f3dc FMUL	Z26.D, Z23.D, Z23.D

0x44f3e0 FADD	Z25.D, Z25.D, Z26.D

0x44f3e4 FMUL	Z26.D, Z7.D, Z7.D

0x44f3e8 FMUL	Z22.D, Z16.D, Z16.D

0x44f3ec FMUL	Z16.D, Z19.D, Z16.D

0x44f3f0 FMUL	Z20.D, Z20.D, Z26.D

0x44f3f4 FADD	Z19.D, Z22.D, Z26.D

0x44f3f8 FMLA	Z20.D, P1/M, Z21.D, Z22.D

0x44f3fc FSQRT	Z25.D, P1/M, Z25.D

0x44f400 FMAD	Z7.D, P1/M, Z16.D, Z20.D

0x44f404 FCMGT	P3.D, P1/Z, Z19.D, Z2.D

0x44f408 SEL	Z16.D, P3, Z19.D, Z2.D

0x44f40c FMUL	Z19.D, Z4.D, Z25.D

0x44f410 FDIV	Z7.D, P1/M, Z7.D, Z16.D

0x44f414 FMUL	Z16.D, Z6.D, Z25.D

0x44f418 FMAD	Z6.D, P1/M, Z18.D, Z17.D

0x44f41c FCMGE	P3.D, P1/Z, Z6.D, #0.0000000

0x44f420 FDIV	Z16.D, P1/M, Z16.D, Z24.D

0x44f424 FABS	Z16.D, P1/M, Z16.D

0x44f428 FDIV	Z19.D, P1/M, Z19.D, Z23.D

0x44f42c FCMGT	P4.D, P1/Z, Z7.D, #0.0000000

0x44f430 SEL	P3.B, P3, P3.B, P4.B

0x44f434 BIC	P4.B, P2/Z, P2.B, P3.B

0x44f438 FABS	Z19.D, P1/M, Z19.D

0x44f43c LD1D	{Z6.D}, P4/Z, [X26, X12,LSL #3]    [5]

0x44f440 AND	P2.B, P2/Z, P2.B, P3.B

0x44f444 FCMGT	P5.D, P1/Z, Z19.D, Z16.D

0x44f448 FADD	Z6.D, Z6.D, Z6.D

0x44f44c SEL	Z16.D, P5, Z16.D, Z19.D

0x44f450 FMUL	Z16.D, Z16.D, Z16.D

0x44f454 FMUL	Z6.D, Z16.D, Z6.D

0x44f458 FMUL	Z6.D, Z7.D, Z6.D

0x44f45c FMUL	Z6.D, Z7.D, Z6.D

0x44f460 ST1D	{Z6.D}, P4, [X27, X12,LSL #3]    [7]

0x44f464 ST1D	{Z3.D}, P2, [X3, X6,LSL #3]    [9]

0x44f468 WHILELO	P2.D, W5, W15

0x44f46c B.MI	44f2c0

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 54 - 89

--------------------------------------------------------------------------------

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Coverage (%)	Name	Source Location	Module
►98.39+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.61+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	viscosity_kernel	viscosity_kernel.f90:98	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.97 - 3.97
Bottlenecks	P6, P8,
Function	_QMviscosity_kernel_modulePviscosity_kernel..omp_par
Source	viscosity_kernel.f90:54-89
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	69.93 - 140.85
CQA cycles if no scalar integer	69.93 - 140.85
CQA cycles if FP arith vectorized	69.93 - 140.85
CQA cycles if fully vectorized	69.93 - 140.85
Front-end cycles	13.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	4.75
P6 cycles	35.50
P7 cycles	35.50
P8 cycles	19.50
P9 cycles	19.50
P10 cycles	8.50
P11 cycles	8.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	69.93 - 140.85
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	108.00
Nb uops	108.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.97 - 1.48
Nb FLOP add-sub	76.00
Nb FLOP mul	68.00
Nb FLOP fma	12.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.86 - 7.78
Bytes prefetched	0.00
Bytes loaded	480.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	9.00
Vectorization ratio all	94.57
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	95.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	84.00
Vector-efficiency ratio all	97.15
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.63
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	93.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.97 - 3.97
Bottlenecks	P6, P8,
Function	_QMviscosity_kernel_modulePviscosity_kernel..omp_par
Source	viscosity_kernel.f90:54-89
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	69.93 - 140.85
CQA cycles if no scalar integer	69.93 - 140.85
CQA cycles if FP arith vectorized	69.93 - 140.85
CQA cycles if fully vectorized	69.93 - 140.85
Front-end cycles	13.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	4.75
P6 cycles	35.50
P7 cycles	35.50
P8 cycles	19.50
P9 cycles	19.50
P10 cycles	8.50
P11 cycles	8.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	69.93 - 140.85
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	108.00
Nb uops	108.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.97 - 1.48
Nb FLOP add-sub	76.00
Nb FLOP mul	68.00
Nb FLOP fma	12.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.86 - 7.78
Bytes prefetched	0.00
Bytes loaded	480.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	9.00
Vectorization ratio all	94.57
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	95.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	84.00
Vector-efficiency ratio all	97.15
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.63
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	93.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMviscosity_kernel_modulePviscosity_kernel..omp_par
Source file and lines	viscosity_kernel.f90:54-89
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:54-89.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

95% of VPU addition or subtraction instructions are used in vector version.
84% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 140.85 to 30.50 cycles (4.62x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

88: addition or subtraction (12 inside FMA instructions)
80: multiply (12 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 480 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.38 FP operations per loaded or stored byte.

General properties

nb instructions	108
nb uops	108
loop length	432
used w registers	6
used x registers	19
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	18
nb stack references	0
ADD-SUB / MUL ratio	1.12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.75	4.75	4.75	4.75	35.50	35.50	1.00	1.00	8.50	8.50	0.00	0.00	0.00
cycles	0.50	0.50	4.75	4.75	4.75	4.75	35.50	35.50	19.50	19.50	8.50	8.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	69.93-140.85
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	13.50
Dispatch	35.50
DIV/SQRT	69.93-140.85
Data deps.	0.00
Overall L1	69.93-140.85

Vectorization ratios

INT

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	63%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	84%

Vector efficiency ratios

INT

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	84%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	97%
load	100%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	93%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 140.85 cycles. At this rate:

3% of peak load performance is reached (3.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44f2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD W6, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB W7, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X30, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W5, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W4, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X12, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P2/Z, [X23, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUB X12, X12, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X7, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z18.D}, P2/Z, [X1, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X2, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z7.D}, P2/Z, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X0, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X23, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z20.D}, P2/Z, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X21, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X21, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z16.D, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X12, X6, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z26.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z16.D, P1/M, Z16.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUB Z7.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z7.D, P1/M, Z7.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z22.D, Z17.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z25.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z27.D, Z21.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z20.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z18.D, Z23.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z21.D, Z24.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z17.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z26.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z18.D, Z21.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z22.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z20, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z20.D, P1/M, Z20.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z19.D, P1/M, Z19.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z21, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z21.D, P1/M, Z21.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z17.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, P1/M, Z22.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z20.D, P1/M, Z20.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z25, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z25.D, P1/M, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z23, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z23.D, P1/M, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P3.D, P1/Z, Z2.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SEL Z24.D, P3, Z2.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P4.D, P1/Z, Z16.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P3.D, P1/Z, Z2.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FNEG Z24.D, P4/M, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z22.D, P1/M, Z22.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
SEL Z23.D, P3, Z2.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z25.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z19.D, Z22.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P3.D, P1/Z, Z24.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z21.D, P1/M, Z21.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FNEG Z23.D, P3/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z26.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z25.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z26.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z16.D, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z20.D, Z20.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z19.D, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z20.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z25.D, P1/M, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMAD Z7.D, P1/M, Z16.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCMGT P3.D, P1/Z, Z19.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SEL Z16.D, P3, Z19.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z19.D, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z7.D, P1/M, Z7.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z16.D, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z6.D, P1/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCMGE P3.D, P1/Z, Z6.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z16.D, P1/M, Z16.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FABS Z16.D, P1/M, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCMGT P4.D, P1/Z, Z7.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SEL P3.B, P3, P3.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
BIC P4.B, P2/Z, P2.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FABS Z19.D, P1/M, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P4/Z, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
AND P2.B, P2/Z, P2.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P5.D, P1/Z, Z19.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FADD Z6.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z16.D, P5, Z16.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z6.D}, P4, [X27, X12,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z3.D}, P2, [X3, X6,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W5, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 44f2c0 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMviscosity_kernel_modulePviscosity_kernel..omp_par
Source file and lines	viscosity_kernel.f90:54-89
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

95% of VPU addition or subtraction instructions are used in vector version.
84% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 140.85 to 30.50 cycles (4.62x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

88: addition or subtraction (12 inside FMA instructions)
80: multiply (12 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 480 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.38 FP operations per loaded or stored byte.

General properties

nb instructions	108
nb uops	108
loop length	432
used w registers	6
used x registers	19
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	18
nb stack references	0
ADD-SUB / MUL ratio	1.12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.75	4.75	4.75	4.75	35.50	35.50	1.00	1.00	8.50	8.50	0.00	0.00	0.00
cycles	0.50	0.50	4.75	4.75	4.75	4.75	35.50	35.50	19.50	19.50	8.50	8.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	69.93-140.85
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	13.50
Dispatch	35.50
DIV/SQRT	69.93-140.85
Data deps.	0.00
Overall L1	69.93-140.85

Vectorization ratios

INT

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	63%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	84%

Vector efficiency ratios

INT

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	84%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	97%
load	100%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	93%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 140.85 cycles. At this rate:

3% of peak load performance is reached (3.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44f2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD W6, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB W7, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X30, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W5, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W4, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X12, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P2/Z, [X23, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUB X12, X12, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X7, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z18.D}, P2/Z, [X1, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X2, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z7.D}, P2/Z, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X0, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X23, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z20.D}, P2/Z, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X21, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X21, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z16.D, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X12, X6, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z26.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z16.D, P1/M, Z16.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUB Z7.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z7.D, P1/M, Z7.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z22.D, Z17.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z25.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z27.D, Z21.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z20.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z18.D, Z23.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z21.D, Z24.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z17.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z26.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z18.D, Z21.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z22.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z20, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z20.D, P1/M, Z20.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z19.D, P1/M, Z19.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z21, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z21.D, P1/M, Z21.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z17.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, P1/M, Z22.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z20.D, P1/M, Z20.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z25, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z25.D, P1/M, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z23, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z23.D, P1/M, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P3.D, P1/Z, Z2.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SEL Z24.D, P3, Z2.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P4.D, P1/Z, Z16.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P3.D, P1/Z, Z2.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FNEG Z24.D, P4/M, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z22.D, P1/M, Z22.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
SEL Z23.D, P3, Z2.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z25.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z19.D, Z22.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P3.D, P1/Z, Z24.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z21.D, P1/M, Z21.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FNEG Z23.D, P3/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z26.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z25.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z26.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z16.D, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z20.D, Z20.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z19.D, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z20.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z25.D, P1/M, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMAD Z7.D, P1/M, Z16.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCMGT P3.D, P1/Z, Z19.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SEL Z16.D, P3, Z19.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z19.D, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z7.D, P1/M, Z7.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z16.D, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z6.D, P1/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCMGE P3.D, P1/Z, Z6.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z16.D, P1/M, Z16.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FABS Z16.D, P1/M, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCMGT P4.D, P1/Z, Z7.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SEL P3.B, P3, P3.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
BIC P4.B, P2/Z, P2.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FABS Z19.D, P1/M, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P4/Z, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
AND P2.B, P2/Z, P2.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P5.D, P1/Z, Z19.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FADD Z6.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z16.D, P5, Z16.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z6.D}, P4, [X27, X12,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z3.D}, P2, [X3, X6,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W5, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 44f2c0 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code