OV - exec - Loop 148

	Loop Id: 148	Module: exec	Source: advec_mom_kernel.f90:149-176 [...]	Coverage: 3.56%

  (147) 0x41d9a0 CMP	W10, W8

  (147) 0x41d9a4 ADD	W10, W10, #1

  (147) 0x41d9a8 ADD	W2, W2, #1

  (147) 0x41d9ac B.EQ	41daf8

  (147) 0x41d9b0 TBNZ	X15, #63, 41d9a0

0x41d9b4 SUB	X14, XZR, X26

0x41d9b8 LDR	X6, [SP, #128]

0x41d9bc SUB	X27, X9, #1

0x41d9c0 ORR	X3, XZR, XZR

0x41d9c4 ORR	X25, XZR, X1

0x41d9c8 ADD	X14, X14, W2,SXTW

0x41d9cc MUL	X14, X13, X14

0x41d9d0 ADD	X4, X17, X14

0x41d9d4 ADD	X5, X18, X14

0x41d9d8 ADD	W14, W12, W10

0x41d9dc SBFM	X14, X14, #0, #31

0x41d9e0 SUB	X14, X14, X26

0x41d9e4 MUL	X14, X14, X6

0x41d9e8 ADD	X6, X20, X14,LSL #3

0x41d9ec SUB	X7, X14, X24

0x41d9f0 B	41da24

0x41da00 FSUB	D4, D1, S4

0x41da04 SUB	X25, X25, #1

0x41da08 ADD	X27, X27, #1

0x41da0c CMP	X25, #1

0x41da10 FMADD	D4, D4, D16, D5

0x41da14 FMUL	D3, D3, D4

0x41da18 STR	D3, [X4, X3,LSL #3]

0x41da1c ADD	X3, X3, #1

0x41da20 B.LE	41d9a0

0x41da24 LDR	D3, [X5, X3,LSL #3]

0x41da28 FCMP	D3, #0

0x41da2c B.PL	41da44

0x41da30 ADD	W28, W27, #1

0x41da34 ADD	W30, W27, #2

0x41da38 ORR	X19, XZR, X27

0x41da3c ORR	W14, WZR, W28

0x41da40 B	41da54

0x41da44 ADD	X28, X11, X3

0x41da48 ADD	W30, W0, W3

0x41da4c ADD	X19, X9, X3

0x41da50 ADD	W14, W0, W3

0x41da54 ADD	X28, X7, W28,SXTW

0x41da58 FABS	D4, D3

0x41da5c SBFM	X19, X19, #0, #31

0x41da60 MOVI	D16, #0

0x41da64 SUB	X19, X19, X24

0x41da68 LDR	D5, [X21, X28,LSL #3]

0x41da6c FDIV	D4, D4, D5

0x41da70 LDR	D5, [X20, X28,LSL #3]

0x41da74 SBFM	X28, X30, #0, #31

0x41da78 SUB	X28, X28, X24

0x41da7c LDR	D6, [X6, X28,LSL #3]

0x41da80 FSUB	D7, D5, S6

0x41da84 LDR	D6, [X6, X19,LSL #3]

0x41da88 FSUB	D6, D6, S5

0x41da8c FMUL	D17, D7, D6

0x41da90 FCMP	D17, #0

0x41da94 B.LE	41da00

0x41da98 LDR	X19, [SP, #144]

0x41da9c SBFM	X14, X14, #0, #31

0x41daa0 LDR	D16, [X16, X3,LSL #3]

0x41daa4 FABS	D7, D7

0x41daa8 FABS	D17, D6

0x41daac FSUB	D18, D0, S4

0x41dab0 FADD	D19, D4, D1

0x41dab4 SUB	X14, X14, X24

0x41dab8 FMUL	D18, D18, D17

0x41dabc FMUL	D19, D19, D7

0x41dac0 LDR	D20, [X19, X14,LSL #3]

0x41dac4 FDIV	D18, D18, D16

0x41dac8 FDIV	D19, D19, D20

0x41dacc FADD	D18, D18, D19

0x41dad0 FMUL	D16, D16, D18

0x41dad4 FDIV	D16, D16, D2

0x41dad8 FCMP	D16, D7

0x41dadc FCSEL	D7, D16, D7, #4

0x41dae0 FCMP	D7, D17

0x41dae4 FCSEL	D7, D7, D17, #4

0x41dae8 FCMP	D6, #0

0x41daec FNEG	D16, D7

0x41daf0 FCSEL	D16, D7, D16, #8

0x41daf4 B	41da00

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 149 - 176

--------------------------------------------------------------------------------

149:       !$OMP DO PRIVATE(upwind,downwind,donor,dif,sigma,width,limiter,vdiffuw,vdiffdw,auw,adw,wind,advec_vel_s)

150:       DO k=y_min,y_max+1

151:         DO j=x_min-1,x_max+1

152:           IF(node_flux(j,k).LT.0.0)THEN

153:             upwind=j+2

154:             donor=j+1

[...]

160:             downwind=j+1

161:             dif=upwind

162:           ENDIF

163:           sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k))

164:           width=celldx(j)

165:           vdiffuw=vel1(donor,k)-vel1(upwind,k)

166:           vdiffdw=vel1(downwind,k)-vel1(donor,k)

167:           limiter=0.0

168:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

169:             auw=ABS(vdiffuw)

170:             adw=ABS(vdiffdw)

171:             wind=1.0_8

172:             IF(vdiffdw.LE.0.0) wind=-1.0_8

173:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw)

174:           ENDIF

175:           advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter

176:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

Coverage (%)	Name	Module
►98.42+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.44 - 4.94
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.78 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18 - 1.43
Bottlenecks	P6, P8,
Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source	advec_mom_kernel.f90:149-154,advec_mom_kernel.f90:160-160,advec_mom_kernel.f90:163-170,advec_mom_kernel.f90:173-176
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.75 - 13.99
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	5.06 - 6.99
CQA cycles if fully vectorized	3.50 - 6.99
Front-end cycles	9.75
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.25
P5 cycles	8.25
P6 cycles	7.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	3.50
P11 cycles	3.17
P12 cycles	3.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	7.01 - 13.99
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	78.00
Nb loads	NA
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	1.74 - 1.22
Nb FLOP add-sub	6.00
Nb FLOP mul	5.00
Nb FLOP fma	1.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	3.44 - 4.94
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.78 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18 - 1.43
Bottlenecks	P6, P8,
Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source	advec_mom_kernel.f90:149-154,advec_mom_kernel.f90:160-160,advec_mom_kernel.f90:163-170,advec_mom_kernel.f90:173-176
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.75 - 13.99
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	5.06 - 6.99
CQA cycles if fully vectorized	3.50 - 6.99
Front-end cycles	9.75
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.25
P5 cycles	8.25
P6 cycles	7.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	3.50
P11 cycles	3.17
P12 cycles	3.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	7.01 - 13.99
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	78.00
Nb loads	NA
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	1.74 - 1.22
Nb FLOP add-sub	6.00
Nb FLOP mul	5.00
Nb FLOP fma	1.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source file and lines	advec_mom_kernel.f90:149-176
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:149-154,160-176.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:149-154,160,163-170,173-176.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.99 to 2.83 cycles (4.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.99 to 6.99 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.99 to 9.25 cycles (1.51x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (1 inside FMA instructions)
6: multiply (1 inside FMA instructions)
4: divide

The binary loop does not load or store any data.

General properties

nb instructions	78
nb uops	78
loop length	312
used w registers	10
used x registers	23
used b registers	0
used h registers	0
used s registers	4
used d registers	13
used q registers	0
used v registers	0
used z registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	8.25	8.25	8.25	8.25	7.50	7.50	7.50	7.50	3.50	3.17	3.33	0.00	0.00
cycles	3.00	3.00	8.25	8.25	8.25	8.25	7.50	7.50	7.50	7.50	3.50	3.17	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

7.01-13.99

Cycles summary

Front-end	9.75
Dispatch	8.25
DIV/SQRT	7.01-13.99
Overall L1	9.75-13.99

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	24%
load	25%
store	25%
mul	25%
add-sub	22%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.99 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41da00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SUB X14, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB X27, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X14, W2,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
MUL X14, X13, X14	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X4, X17, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X14, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X14, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X14, X14, X6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X6, X20, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X14, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 41da24 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x16f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FSUB D4, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUB X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FMADD D4, D4, D16, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D3, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.LE 41d9a0 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.PL 41da44 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W28, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X19, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR W14, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 41da54 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X28, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X19, X9, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X28, X7, W28,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
FABS D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SBFM X19, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUB X19, X19, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X21, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D4, D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D5, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X28, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X28, X28, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X6, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D7, D5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D6, [X6, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D6, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D17, D7, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 41da00 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x16d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SBFM X14, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FABS D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D17, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D0, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D19, D4, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUB X14, X14, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D18, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D19, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D20, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D18, D18, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FDIV D19, D19, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D18, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D16, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D16, D16, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCMP D16, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D7, D16, D7, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D7, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D7, D7, D17, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D16, D7, D16, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
B 41da00 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x16d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source file and lines	advec_mom_kernel.f90:149-176
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.99 to 2.83 cycles (4.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.99 to 9.25 cycles (1.51x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (1 inside FMA instructions)
6: multiply (1 inside FMA instructions)
4: divide

The binary loop does not load or store any data.

General properties

nb instructions	78
nb uops	78
loop length	312
used w registers	10
used x registers	23
used b registers	0
used h registers	0
used s registers	4
used d registers	13
used q registers	0
used v registers	0
used z registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	8.25	8.25	8.25	8.25	7.50	7.50	7.50	7.50	3.50	3.17	3.33	0.00	0.00
cycles	3.00	3.00	8.25	8.25	8.25	8.25	7.50	7.50	7.50	7.50	3.50	3.17	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

7.01-13.99

Cycles summary

Front-end	9.75
Dispatch	8.25
DIV/SQRT	7.01-13.99
Overall L1	9.75-13.99

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	24%
load	25%
store	25%
mul	25%
add-sub	22%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.99 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41da00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SUB X14, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB X27, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X14, W2,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
MUL X14, X13, X14	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X4, X17, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X14, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X14, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X14, X14, X6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X6, X20, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X14, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 41da24 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x16f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FSUB D4, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUB X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FMADD D4, D4, D16, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D3, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.LE 41d9a0 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.PL 41da44 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W28, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X19, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR W14, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 41da54 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X28, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X19, X9, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X28, X7, W28,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
FABS D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SBFM X19, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUB X19, X19, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X21, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D4, D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D5, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X28, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X28, X28, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X6, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D7, D5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D6, [X6, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D6, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D17, D7, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 41da00 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x16d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SBFM X14, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FABS D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D17, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D0, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D19, D4, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUB X14, X14, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D18, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D19, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D20, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D18, D18, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FDIV D19, D19, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D18, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D16, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D16, D16, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCMP D16, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D7, D16, D7, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D7, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D7, D7, D17, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D16, D7, D16, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
B 41da00 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x16d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code