| Loop Id: 149 | Module: exec | Source: advec_mom_kernel.f90:135-144 | Coverage: 2.75% |
|---|
| Loop Id: 149 | Module: exec | Source: advec_mom_kernel.f90:135-144 | Coverage: 2.75% |
|---|
(150) 0x41d760 CMP W10, W8 |
(150) 0x41d764 ADD W10, W10, #1 |
(150) 0x41d768 B.EQ 41d8b8 |
(150) 0x41d76c CBZ W12, 41d760 |
(150) 0x41d770 ADD W17, W9, W10 |
(150) 0x41d774 LDR X3, [SP, #128] |
(150) 0x41d778 SUB X6, XZR, X15 |
(150) 0x41d77c ORR P2.B, P0/Z, P0.B, P0.B |
(150) 0x41d780 ORR W5, WZR, W13 |
(150) 0x41d784 ORR W7, WZR, W13 |
(150) 0x41d788 ORR W4, WZR, W11 |
(150) 0x41d78c SUB W18, W17, #1 |
(150) 0x41d790 SBFM X17, X17, #0, #31 |
(150) 0x41d794 SBFM X18, X18, #0, #31 |
(150) 0x41d798 SUB X1, X17, X26 |
(150) 0x41d79c SUB X17, X18, X26 |
(150) 0x41d7a0 MUL X18, X1, X30 |
(150) 0x41d7a4 MUL X0, X17, X30 |
(150) 0x41d7a8 MUL X2, X17, X3 |
(150) 0x41d7ac MUL X1, X1, X3 |
(150) 0x41d7b0 ADD X17, X28, X18,LSL #3 |
(150) 0x41d7b4 ADD X18, X28, X0,LSL #3 |
(150) 0x41d7b8 ADD X0, X19, X2,LSL #3 |
(150) 0x41d7bc ADD X2, X19, X1,LSL #3 |
(150) 0x41d7c0 ADD X3, X25, X1,LSL #3 |
(150) 0x41d7c4 TBZ W14, #0, 41d840 |
(151) 0x41d7c8 SBFM X5, X7, #0, #31 |
(151) 0x41d7cc ADD W7, W7, #1 |
(151) 0x41d7d0 SUBS W4, W4, #1 |
(151) 0x41d7d4 SBFM X6, X7, #0, #31 |
(151) 0x41d7d8 SUB X5, X5, X24 |
(151) 0x41d7dc SUB X6, X6, X24 |
(151) 0x41d7e0 LDR D2, [X18, X6,LSL #3] |
(151) 0x41d7e4 LDR D3, [X0, X6,LSL #3] |
(151) 0x41d7e8 LDR D4, [X17, X6,LSL #3] |
(151) 0x41d7ec ADD X6, X6, X1 |
(151) 0x41d7f0 LDR D5, [X19, X6,LSL #3] |
(151) 0x41d7f4 FMUL D4, D4, D5 |
(151) 0x41d7f8 FMADD D2, D2, D3, D4 |
(151) 0x41d7fc LDR D3, [X18, X5,LSL #3] |
(151) 0x41d800 LDR D4, [X0, X5,LSL #3] |
(151) 0x41d804 FMADD D2, D3, D4, D2 |
(151) 0x41d808 LDR D3, [X17, X5,LSL #3] |
(151) 0x41d80c LDR D4, [X2, X5,LSL #3] |
(151) 0x41d810 FMADD D2, D3, D4, D2 |
(151) 0x41d814 LDR D3, [X3, X5,LSL #3] |
(151) 0x41d818 FMUL D2, D2, D0 |
(151) 0x41d81c STR D2, [X23, X6,LSL #3] |
(151) 0x41d820 FSUB D2, D2, S3 |
(151) 0x41d824 LDR D3, [X25, X6,LSL #3] |
(151) 0x41d828 FADD D2, D3, D2 |
(151) 0x41d82c STR D2, [X21, X6,LSL #3] |
(151) 0x41d830 B.NE 41d7c8 |
(150) 0x41d834 B 41d760 |
0x41d840 ADD W4, W5, #1 |
0x41d844 SBFM X7, X5, #0, #31 |
0x41d848 ADD W6, W6, W15 |
0x41d84c ADD W5, W5, W15 |
0x41d850 SBFM X4, X4, #0, #31 |
0x41d854 SUB X7, X7, X24 |
0x41d858 SUB X4, X4, X24 |
0x41d85c LD1D {Z2.D}, P2/Z, [X18, X4,LSL #3] |
0x41d860 LD1D {Z3.D}, P2/Z, [X0, X4,LSL #3] |
0x41d864 LD1D {Z4.D}, P2/Z, [X17, X4,LSL #3] |
0x41d868 ADD X4, X4, X1 |
0x41d86c LD1D {Z5.D}, P2/Z, [X19, X4,LSL #3] |
0x41d870 FMUL Z4.D, Z4.D, Z5.D |
0x41d874 FMAD Z2.D, P1/M, Z3.D, Z4.D |
0x41d878 LD1D {Z3.D}, P2/Z, [X18, X7,LSL #3] |
0x41d87c LD1D {Z4.D}, P2/Z, [X0, X7,LSL #3] |
0x41d880 FMLA Z2.D, P1/M, Z3.D, Z4.D |
0x41d884 LD1D {Z3.D}, P2/Z, [X17, X7,LSL #3] |
0x41d888 LD1D {Z4.D}, P2/Z, [X2, X7,LSL #3] |
0x41d88c FMLA Z2.D, P1/M, Z3.D, Z4.D |
0x41d890 LD1D {Z3.D}, P2/Z, [X3, X7,LSL #3] |
0x41d894 FMUL Z2.D, Z2.D, Z1.D |
0x41d898 ST1D {Z2.D}, P2, [X23, X4,LSL #3] |
0x41d89c FSUB Z2.D, Z2.D, Z3.D |
0x41d8a0 LD1D {Z3.D}, P2/Z, [X25, X4,LSL #3] |
0x41d8a4 FADD Z2.D, Z3.D, Z2.D |
0x41d8a8 ST1D {Z2.D}, P2, [X21, X4,LSL #3] |
0x41d8ac WHILELO P2.D, W6, W16 |
0x41d8b0 B.MI 41d840 |
0x41d8b4 B 41d760 |
/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 135 - 144 |
-------------------------------------------------------------------------------- |
135: !$OMP DO |
136: DO k=y_min,y_max+1 |
137: !$OMP SIMD |
138: DO j=x_min-1,x_max+2 |
139: ! Staggered cell mass post advection |
140: node_mass_post(j,k)=0.25_8*(density1(j ,k-1)*post_vol(j ,k-1) & |
141: +density1(j ,k )*post_vol(j ,k ) & |
142: +density1(j-1,k-1)*post_vol(j-1,k-1) & |
143: +density1(j-1,k )*post_vol(j-1,k )) |
144: node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j-1,k)+node_flux(j,k) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.43+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.60 |
| Bottlenecks | P10, P11, |
| Function | _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par |
| Source | advec_mom_kernel.f90:137-137,advec_mom_kernel.f90:140-140,advec_mom_kernel.f90:144-144 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.00 |
| CQA cycles if no scalar integer | 6.00 |
| CQA cycles if FP arith vectorized | 6.00 |
| CQA cycles if fully vectorized | 6.00 |
| Front-end cycles | 3.75 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 2.25 |
| P3 cycles | 2.25 |
| P4 cycles | 2.25 |
| P5 cycles | 2.25 |
| P6 cycles | 3.50 |
| P7 cycles | 3.50 |
| P8 cycles | 3.50 |
| P9 cycles | 3.50 |
| P10 cycles | 6.00 |
| P11 cycles | 6.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 30.00 |
| Nb uops | 30.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 6.67 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 12.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 320.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 95.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 66.67 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 95.63 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 70.83 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.60 |
| Bottlenecks | P10, P11, |
| Function | _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par |
| Source | advec_mom_kernel.f90:137-137,advec_mom_kernel.f90:140-140,advec_mom_kernel.f90:144-144 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.00 |
| CQA cycles if no scalar integer | 6.00 |
| CQA cycles if FP arith vectorized | 6.00 |
| CQA cycles if fully vectorized | 6.00 |
| Front-end cycles | 3.75 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 2.25 |
| P3 cycles | 2.25 |
| P4 cycles | 2.25 |
| P5 cycles | 2.25 |
| P6 cycles | 3.50 |
| P7 cycles | 3.50 |
| P8 cycles | 3.50 |
| P9 cycles | 3.50 |
| P10 cycles | 6.00 |
| P11 cycles | 6.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 30.00 |
| Nb uops | 30.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 6.67 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 12.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 320.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 95.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 66.67 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 95.63 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 70.83 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par |
| Source file and lines | advec_mom_kernel.f90:135-144 |
| Module | exec |
| nb instructions | 30 |
| nb uops | 30 |
| loop length | 120 |
| used w registers | 5 |
| used x registers | 14 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 5 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 3.75 cycles |
| front end | 3.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 3.50 | 3.50 | 1.00 | 1.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 3.50 | 3.50 | 3.50 | 3.50 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 3.75 |
| Dispatch | 6.00 |
| Overall L1 | 6.00 |
| all | 92% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 95% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 66% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 93% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 95% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 70% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD W4, W5, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SBFM X7, X5, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W6, W6, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W5, W5, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X4, X4, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X7, X7, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X4, X4, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z2.D}, P2/Z, [X18, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X0, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z4.D}, P2/Z, [X17, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| ADD X4, X4, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z5.D}, P2/Z, [X19, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMUL Z4.D, Z4.D, Z5.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| FMAD Z2.D, P1/M, Z3.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X18, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z4.D}, P2/Z, [X0, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMLA Z2.D, P1/M, Z3.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X17, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z4.D}, P2/Z, [X2, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMLA Z2.D, P1/M, Z3.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X3, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMUL Z2.D, Z2.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| ST1D {Z2.D}, P2, [X23, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FSUB Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X25, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z3.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z2.D}, P2, [X21, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P2.D, W6, W16 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 41d840 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1510> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 41d760 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1430> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Function | _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par |
| Source file and lines | advec_mom_kernel.f90:135-144 |
| Module | exec |
| nb instructions | 30 |
| nb uops | 30 |
| loop length | 120 |
| used w registers | 5 |
| used x registers | 14 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 5 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 3.75 cycles |
| front end | 3.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 3.50 | 3.50 | 1.00 | 1.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 3.50 | 3.50 | 3.50 | 3.50 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 3.75 |
| Dispatch | 6.00 |
| Overall L1 | 6.00 |
| all | 92% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 95% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 66% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 93% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 95% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 70% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD W4, W5, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SBFM X7, X5, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W6, W6, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W5, W5, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X4, X4, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X7, X7, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X4, X4, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z2.D}, P2/Z, [X18, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X0, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z4.D}, P2/Z, [X17, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| ADD X4, X4, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z5.D}, P2/Z, [X19, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMUL Z4.D, Z4.D, Z5.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| FMAD Z2.D, P1/M, Z3.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X18, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z4.D}, P2/Z, [X0, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMLA Z2.D, P1/M, Z3.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X17, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z4.D}, P2/Z, [X2, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMLA Z2.D, P1/M, Z3.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X3, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMUL Z2.D, Z2.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| ST1D {Z2.D}, P2, [X23, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FSUB Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X25, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z3.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z2.D}, P2, [X21, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P2.D, W6, W16 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 41d840 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1510> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 41d760 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1430> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
