| Loop Id: 160 | Module: exec | Source: advec_mom_kernel.f90:127-130 | Coverage: 1.04% |
|---|
| Loop Id: 160 | Module: exec | Source: advec_mom_kernel.f90:127-130 | Coverage: 1.04% |
|---|
0x41cfa8 SUB W3, W1, #1 |
0x41cfac SBFM X4, X1, #0, #31 |
0x41cfb0 ADD W2, W2, W15 |
0x41cfb4 ADD W1, W1, W15 |
0x41cfb8 SBFM X3, X3, #0, #31 |
0x41cfbc SUB X4, X4, X24 |
0x41cfc0 SUB X3, X3, X24 |
0x41cfc4 LD1D {Z2.D}, P1/Z, [X17, X3,LSL #3] [3] |
0x41cfc8 ADD X3, X3, X18 |
0x41cfcc LD1D {Z3.D}, P1/Z, [X6, X3,LSL #3] [2] |
0x41cfd0 FADD Z2.D, Z2.D, Z3.D |
0x41cfd4 LD1D {Z3.D}, P1/Z, [X17, X4,LSL #3] [3] |
0x41cfd8 FADD Z2.D, Z2.D, Z3.D |
0x41cfdc LD1D {Z3.D}, P1/Z, [X0, X4,LSL #3] [1] |
0x41cfe0 FADD Z2.D, Z2.D, Z3.D |
0x41cfe4 FMUL Z2.D, Z2.D, Z1.D |
0x41cfe8 ST1D {Z2.D}, P1, [X5, X3,LSL #3] [4] |
0x41cfec WHILELO P1.D, W2, W16 |
0x41cff0 B.MI 41cfa8 |
/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 127 - 130 |
-------------------------------------------------------------------------------- |
127: !$OMP SIMD |
128: DO j=x_min-2,x_max+2 |
129: ! Find staggered mesh mass fluxes, nodal masses and volumes. |
130: node_flux(j,k)=0.25_8*(mass_flux_x(j,k-1 )+mass_flux_x(j ,k) & |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.40+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.05 |
| Bottlenecks | P10, P11, |
| Function | _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par |
| Source | advec_mom_kernel.f90:127-130 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | 4 |
| CQA cycles | 2.50 |
| CQA cycles if no scalar integer | 2.50 |
| CQA cycles if FP arith vectorized | 2.50 |
| CQA cycles if fully vectorized | 2.50 |
| Front-end cycles | 2.38 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 2.25 |
| P3 cycles | 2.25 |
| P4 cycles | 2.25 |
| P5 cycles | 2.25 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 2.00 |
| P10 cycles | 2.50 |
| P11 cycles | 2.50 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 19.00 |
| Nb uops | 19.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 6.40 |
| Nb FLOP add-sub | 12.00 |
| Nb FLOP mul | 4.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 32.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 4.00 |
| Vectorization ratio all | 90.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 75.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 91.25 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 78.13 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.05 |
| Bottlenecks | P10, P11, |
| Function | _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par |
| Source | advec_mom_kernel.f90:127-130 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | 4 |
| CQA cycles | 2.50 |
| CQA cycles if no scalar integer | 2.50 |
| CQA cycles if FP arith vectorized | 2.50 |
| CQA cycles if fully vectorized | 2.50 |
| Front-end cycles | 2.38 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 2.25 |
| P3 cycles | 2.25 |
| P4 cycles | 2.25 |
| P5 cycles | 2.25 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 2.00 |
| P10 cycles | 2.50 |
| P11 cycles | 2.50 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 19.00 |
| Nb uops | 19.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 6.40 |
| Nb FLOP add-sub | 12.00 |
| Nb FLOP mul | 4.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 32.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 4.00 |
| Vectorization ratio all | 90.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 75.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 91.25 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 78.13 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par |
| Source file and lines | advec_mom_kernel.f90:127-130 |
| Module | exec |
| nb instructions | 19 |
| nb uops | 19 |
| loop length | 76 |
| used w registers | 5 |
| used x registers | 9 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 3 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 3.00 |
| micro-operation queue | 2.38 cycles |
| front end | 2.38 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 2.25 | 2.25 | 2.25 | 2.25 | 2.00 | 2.00 | 0.50 | 0.50 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 2.25 | 2.25 | 2.25 | 2.25 | 2.00 | 2.00 | 2.00 | 2.00 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.38 |
| Dispatch | 2.50 |
| Data deps. | 1.00 |
| Overall L1 | 2.50 |
| all | 83% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 90% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 75% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 85% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 91% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 78% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB W3, W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SBFM X4, X1, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W2, W2, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W1, W1, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X3, X3, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X4, X4, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X3, X3, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z2.D}, P1/Z, [X17, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| ADD X3, X3, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z3.D}, P1/Z, [X6, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P1/Z, [X17, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P1/Z, [X0, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FMUL Z2.D, Z2.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| ST1D {Z2.D}, P1, [X5, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P1.D, W2, W16 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 41cfa8 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0xc78> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Function | _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par |
| Source file and lines | advec_mom_kernel.f90:127-130 |
| Module | exec |
| nb instructions | 19 |
| nb uops | 19 |
| loop length | 76 |
| used w registers | 5 |
| used x registers | 9 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 3 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 3.00 |
| micro-operation queue | 2.38 cycles |
| front end | 2.38 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 2.25 | 2.25 | 2.25 | 2.25 | 2.00 | 2.00 | 0.50 | 0.50 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 2.25 | 2.25 | 2.25 | 2.25 | 2.00 | 2.00 | 2.00 | 2.00 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.38 |
| Dispatch | 2.50 |
| Data deps. | 1.00 |
| Overall L1 | 2.50 |
| all | 83% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 90% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 75% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 85% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 91% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 78% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB W3, W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SBFM X4, X1, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W2, W2, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W1, W1, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X3, X3, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X4, X4, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X3, X3, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z2.D}, P1/Z, [X17, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| ADD X3, X3, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z3.D}, P1/Z, [X6, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P1/Z, [X17, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P1/Z, [X0, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FMUL Z2.D, Z2.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| ST1D {Z2.D}, P1, [X5, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P1.D, W2, W16 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 41cfa8 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0xc78> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
