OV - exec - Loop 243

	Loop Id: 243	Module: exec	Source: calc_dt_kernel.f90:91-129	Coverage: 2.58%

  (241) 0x420c68 CMP	W9, W8

  (241) 0x420c6c ADD	W9, W9, #1

  (241) 0x420c70 B.EQ	420e48

  (241) 0x420c74 CBZ	W13, 420c68

0x420c78 LDP	X2, X0, [SP, #72]

0x420c7c ADD	W17, W10, W9

0x420c80 LDUR	X1, [X29, #440]

0x420c84 ORR	W14, WZR, WZR

0x420c88 SBFM	X15, X17, #0, #31

0x420c8c ADD	W17, W17, #1

0x420c90 LDR	D4, [X7]

0x420c94 LDR	D5, [X30]

0x420c98 SBFM	X17, X17, #0, #31

0x420c9c SUB	X18, X15, X0

0x420ca0 SUB	X0, X17, X0

0x420ca4 MUL	X15, X18, X1

0x420ca8 MUL	X16, X18, X2

0x420cac LDR	D3, [X6, X18,LSL #3]

0x420cb0 MUL	X17, X0, X2

0x420cb4 MUL	X18, X0, X1

0x420cb8 LDP	X0, X1, [X29, #960]

0x420cbc FNEG	D16, D4

0x420cc0 ADD	X18, X27, X18,LSL #3

0x420cc4 LDR	D6, [X1]

0x420cc8 LDR	D7, [X0]

0x420ccc FADD	D6, D6, D6

0x420cd0 FADD	D7, D7, D7

0x420cd4 B	420d30

0x420ce8 FMUL	D18, D18, D5

0x420cec ADD	W14, W14, #1

0x420cf0 FDIV	D17, D18, D17

0x420cf4 FMUL	D18, D6, D19

0x420cf8 FMUL	D19, D19, D7

0x420cfc FDIV	D18, D18, D20

0x420d00 FCMP	D2, D17

0x420d04 FDIV	D19, D19, D21

0x420d08 FCSEL	D2, D2, D17, #4

0x420d0c FCMP	D2, D18

0x420d10 FCSEL	D2, D2, D18, #4

0x420d14 FCMP	D2, D19

0x420d18 FCSEL	D2, D2, D19, #4

0x420d1c FCMP	D2, D22

0x420d20 FCSEL	D2, D2, D22, #4

0x420d24 CMP	W12, W14

0x420d28 STUR	D2, [X29, #488]

0x420d2c B.LS	420c68

0x420d30 ADD	W0, W11, W14

0x420d34 SBFM	X1, X0, #0, #31

0x420d38 ADD	W0, W0, #1

0x420d3c SUB	X1, X1, X19

0x420d40 SBFM	X0, X0, #0, #31

0x420d44 ADD	X2, X1, X15

0x420d48 ADD	X3, X1, X16

0x420d4c ADD	X4, X1, X17

0x420d50 SUB	X0, X0, X19

0x420d54 LDR	D18, [X21, X1,LSL #3]

0x420d58 LDR	D19, [X24, X2,LSL #3]

0x420d5c LDR	D20, [X25, X2,LSL #3]

0x420d60 LDR	D17, [X23, X2,LSL #3]

0x420d64 ADD	X5, X0, X16

0x420d68 ADD	X0, X0, X17

0x420d6c LDR	D21, [X28, X0,LSL #3]

0x420d70 LDR	D24, [X26, X5,LSL #3]

0x420d74 LDR	D25, [X26, X0,LSL #3]

0x420d78 FADD	D19, D19, D19

0x420d7c FDIV	D19, D19, D20

0x420d80 LDR	D20, [X28, X4,LSL #3]

0x420d84 FMADD	D17, D17, D17, D19

0x420d88 LDR	D19, [X28, X3,LSL #3]

0x420d8c FSQRT	D17, D17

0x420d90 FADD	D19, D19, D20

0x420d94 LDR	D20, [X20, X3,LSL #3]

0x420d98 FMUL	D20, D19, D20

0x420d9c LDR	D19, [X28, X5,LSL #3]

0x420da0 FADD	D19, D19, D21

0x420da4 LDR	D21, [X20, X5,LSL #3]

0x420da8 FCMP	D17, D4

0x420dac FCSEL	D17, D17, D4, #12

0x420db0 FCMP	D18, D3

0x420db4 FMUL	D21, D19, D21

0x420db8 FCSEL	D18, D18, D3, #4

0x420dbc FADD	D19, D21, D0

0x420dc0 FABS	D21, D21

0x420dc4 FSUB	D22, D19, S20

0x420dc8 FABS	D20, D20

0x420dcc LDR	D19, [X22, X2,LSL #3]

0x420dd0 FCMP	D20, D21

0x420dd4 FCSEL	D20, D20, D21, #12

0x420dd8 LDR	D21, [X26, X3,LSL #3]

0x420ddc FMUL	D23, D4, D19

0x420de0 FCMP	D20, D23

0x420de4 FADD	D21, D21, D24

0x420de8 LDR	D24, [X27, X2,LSL #3]

0x420dec FCSEL	D20, D20, D23, #12

0x420df0 FMUL	D21, D21, D24

0x420df4 LDR	D24, [X26, X4,LSL #3]

0x420df8 FADD	D24, D24, D25

0x420dfc LDR	D25, [X18, X1,LSL #3]

0x420e00 FMUL	D24, D24, D25

0x420e04 FADD	D22, D22, D24

0x420e08 FABS	D24, D24

0x420e0c FSUB	D22, D22, S21

0x420e10 FABS	D21, D21

0x420e14 FCMP	D21, D24

0x420e18 FCSEL	D21, D21, D24, #12

0x420e1c FCMP	D21, D23

0x420e20 FCSEL	D21, D21, D23, #12

0x420e24 FADD	D23, D19, D19

0x420e28 FDIV	D22, D22, D23

0x420e2c FCMP	D22, D16

0x420e30 B.PL	420ce0

0x420e34 FDIV	D22, D1, D22

0x420e38 LDUR	X0, [X29, #464]

0x420e3c LDR	D23, [X0]

0x420e40 FMUL	D22, D22, D23

0x420e44 B	420ce8

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 91 - 129

--------------------------------------------------------------------------------

91:     !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val)

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

Coverage (%)	Name	Source Location	Module
►98.38+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.62+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	calc_dt_kernel	calc_dt_kernel.f90:87	exec
○	calc_dt	calc_dt.f90:49	exec
○	timestep	timestep.f90:87	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.71 - 3.03
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.28 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.77
Bottlenecks	P6, P8,
Function	_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par
Source	calc_dt_kernel.f90:91-93,calc_dt_kernel.f90:96-103,calc_dt_kernel.f90:107-126,calc_dt_kernel.f90:129-129
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00 - 24.72
CQA cycles if no scalar integer	8.17
CQA cycles if FP arith vectorized	11.00 - 12.36
CQA cycles if fully vectorized	6.13 - 12.36
Front-end cycles	14.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	6.25
P3 cycles	6.25
P4 cycles	6.25
P5 cycles	6.25
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	14.00
P9 cycles	14.00
P10 cycles	9.50
P11 cycles	9.17
P12 cycles	9.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	12.26 - 24.72
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	112.00
Nb loads	NA
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	2.14 - 1.21
Nb FLOP add-sub	12.00
Nb FLOP mul	9.00
Nb FLOP fma	1.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.98
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	29.17

Metric	Value
CQA speedup if no scalar integer	1.71 - 3.03
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.28 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.77
Bottlenecks	P6, P8,
Function	_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par
Source	calc_dt_kernel.f90:91-93,calc_dt_kernel.f90:96-103,calc_dt_kernel.f90:107-126,calc_dt_kernel.f90:129-129
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00 - 24.72
CQA cycles if no scalar integer	8.17
CQA cycles if FP arith vectorized	11.00 - 12.36
CQA cycles if fully vectorized	6.13 - 12.36
Front-end cycles	14.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	6.25
P3 cycles	6.25
P4 cycles	6.25
P5 cycles	6.25
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	14.00
P9 cycles	14.00
P10 cycles	9.50
P11 cycles	9.17
P12 cycles	9.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	12.26 - 24.72
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	112.00
Nb loads	NA
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	2.14 - 1.21
Nb FLOP add-sub	12.00
Nb FLOP mul	9.00
Nb FLOP fma	1.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.98
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	29.17

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par
Source file and lines	calc_dt_kernel.f90:91-129
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91-129.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91-93,96-103,107-126,129.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.72 to 8.17 cycles (3.03x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 24.72 to 12.36 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.72 to 13.13 cycles (1.88x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 30 FP arithmetical operations:

13: addition or subtraction (1 inside FMA instructions)
10: multiply (1 inside FMA instructions)
6: divide
1: square root

The binary loop does not load or store any data.

General properties

nb instructions	112
nb uops	112
loop length	448
used w registers	8
used x registers	24
used b registers	0
used h registers	0
used s registers	3
used d registers	18
used q registers	0
used v registers	0
used z registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.25	6.25	6.25	6.25	14.00	14.00	14.00	14.00	9.50	9.17	9.33	0.00	0.00
cycles	2.00	2.00	6.25	6.25	6.25	6.25	14.00	14.00	14.00	14.00	9.50	9.17	9.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

12.26-24.72

Cycles summary

Front-end	14.00
Dispatch	14.00
DIV/SQRT	12.26-24.72
Overall L1	14.00-24.72

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	27%
load	25%
store	25%
mul	25%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	25%
add-sub	22%
fma	25%
div/sqrt	25%
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.72 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 420ce8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDP X2, X0, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD W17, W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDUR X1, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR W14, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X15, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W17, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D4, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D5, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X17, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SUB X18, X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X15, X18, X1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X16, X18, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X6, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MUL X17, X0, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X18, X0, X1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDP X0, X1, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
FNEG D16, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X18, X27, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D6, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D7, D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
B 420d30 <_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D18, D18, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FDIV D17, D18, D17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D18, D6, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D19, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D18, D18, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCMP D2, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FDIV D19, D19, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCSEL D2, D2, D17, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D2, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D2, D2, D18, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D2, D19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D2, D2, D19, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D2, D22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D2, D2, D22, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
CMP W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STUR D2, [X29, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
B.LS 420c68 <_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W0, W11, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X0, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X1, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D20, [X25, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D17, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X5, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D24, [X26, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D25, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D19, D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D19, D19, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D20, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D17, D17, D17, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDR D19, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSQRT D17, D17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FADD D19, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D20, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D20, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D19, [X28, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D19, D19, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D21, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D17, D4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D17, D17, D4, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D18, D3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D21, D19, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCSEL D18, D18, D3, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD D19, D21, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D21, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D22, D19, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D19, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D20, D21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D20, D20, D21, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR D21, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D23, D4, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D20, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FADD D21, D21, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D24, [X27, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCSEL D20, D20, D23, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL D21, D21, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D24, [X26, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D24, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D25, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D24, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FADD D22, D22, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D24, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D22, D22, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D21, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D21, D24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D21, D21, D24, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D21, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D21, D21, D23, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD D23, D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D22, D22, D23	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCMP D22, D16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.PL 420ce0 <_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D22, D1, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDUR X0, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D22, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
B 420ce8 <_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par
Source file and lines	calc_dt_kernel.f90:91-129
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.72 to 8.17 cycles (3.03x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.72 to 13.13 cycles (1.88x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 30 FP arithmetical operations:

13: addition or subtraction (1 inside FMA instructions)
10: multiply (1 inside FMA instructions)
6: divide
1: square root

The binary loop does not load or store any data.

General properties

nb instructions	112
nb uops	112
loop length	448
used w registers	8
used x registers	24
used b registers	0
used h registers	0
used s registers	3
used d registers	18
used q registers	0
used v registers	0
used z registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.25	6.25	6.25	6.25	14.00	14.00	14.00	14.00	9.50	9.17	9.33	0.00	0.00
cycles	2.00	2.00	6.25	6.25	6.25	6.25	14.00	14.00	14.00	14.00	9.50	9.17	9.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

12.26-24.72

Cycles summary

Front-end	14.00
Dispatch	14.00
DIV/SQRT	12.26-24.72
Overall L1	14.00-24.72

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	27%
load	25%
store	25%
mul	25%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	25%
add-sub	22%
fma	25%
div/sqrt	25%
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.72 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 420ce8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDP X2, X0, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD W17, W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDUR X1, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR W14, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X15, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W17, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D4, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D5, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X17, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SUB X18, X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X15, X18, X1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X16, X18, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X6, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MUL X17, X0, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X18, X0, X1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDP X0, X1, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
FNEG D16, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X18, X27, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D6, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D7, D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
B 420d30 <_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D18, D18, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FDIV D17, D18, D17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D18, D6, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D19, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D18, D18, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCMP D2, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FDIV D19, D19, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCSEL D2, D2, D17, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D2, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D2, D2, D18, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D2, D19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D2, D2, D19, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D2, D22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D2, D2, D22, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
CMP W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STUR D2, [X29, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
B.LS 420c68 <_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W0, W11, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X0, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X1, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D20, [X25, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D17, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X5, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D24, [X26, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D25, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D19, D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D19, D19, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D20, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D17, D17, D17, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDR D19, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSQRT D17, D17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FADD D19, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D20, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D20, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D19, [X28, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D19, D19, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D21, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D17, D4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D17, D17, D4, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D18, D3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D21, D19, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCSEL D18, D18, D3, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD D19, D21, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D21, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D22, D19, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D19, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D20, D21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D20, D20, D21, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR D21, [X26, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D23, D4, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D20, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FADD D21, D21, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D24, [X27, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCSEL D20, D20, D23, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL D21, D21, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D24, [X26, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D24, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D25, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D24, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FADD D22, D22, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D24, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D22, D22, S21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D21, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D21, D24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D21, D21, D24, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D21, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D21, D21, D23, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD D23, D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D22, D22, D23	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCMP D22, D16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.PL 420ce0 <_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D22, D1, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDUR X0, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D22, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
B 420ce8 <_QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code