OV - exec - Loop 260

	Loop Id: 260	Module: exec	Source: field_summary_kernel.f90:57-71	Coverage: 0.33%

0x42240c ADD	W6, W10, W5

0x422410 ADD	W5, W5, W11

0x422414 SBFM	X6, X6, #0, #31

0x422418 CMP	W16, W5

0x42241c SUB	X6, X6, X21

0x422420 ADD	X7, X6, X3

0x422424 ADD	X27, X20, X7,LSL #3

0x422428 LD1D	{Z3.D}, P1/Z, [X20, X7,LSL #3]    [4]

0x42242c LD1D	{Z23.D}, P1/Z, [X19, X7,LSL #3]    [18]

0x422430 LD1D	{Z22.D}, P1/Z, [X27, X13,LSL #3]    [16]

0x422434 ADD	X27, X19, X7,LSL #3

0x422438 ADD	X7, X6, #1

0x42243c LD1D	{Z24.D}, P1/Z, [X27, X13,LSL #3]    [15]

0x422440 ADD	X27, X7, X3

0x422444 ADD	X7, X7, X4

0x422448 ADD	X30, X20, X27,LSL #3

0x42244c LD1D	{Z25.D}, P1/Z, [X30, X13,LSL #3]    [8]

0x422450 ADD	X30, X19, X27,LSL #3

0x422454 LD1D	{Z26.D}, P1/Z, [X30, X13,LSL #3]    [7]

0x422458 FMUL	Z3.D, Z3.D, Z3.D

0x42245c FMUL	Z23.D, Z23.D, Z23.D

0x422460 FMUL	Z22.D, Z22.D, Z22.D

0x422464 FMUL	Z24.D, Z24.D, Z24.D

0x422468 FADD	Z3.D, Z3.D, Z23.D

0x42246c LD1D	{Z23.D}, P1/Z, [X20, X27,LSL #3]    [4]

0x422470 FADD	Z22.D, Z22.D, Z24.D

0x422474 FMUL	Z24.D, Z25.D, Z25.D

0x422478 LD1D	{Z25.D}, P1/Z, [X19, X27,LSL #3]    [18]

0x42247c FMUL	Z26.D, Z26.D, Z26.D

0x422480 ADD	X27, X6, X4

0x422484 ADD	X30, X20, X27,LSL #3

0x422488 FADD	Z24.D, Z24.D, Z26.D

0x42248c LD1D	{Z26.D}, P1/Z, [X30, X13,LSL #3]    [6]

0x422490 ADD	X30, X19, X27,LSL #3

0x422494 FMUL	Z23.D, Z23.D, Z23.D

0x422498 LD1D	{Z27.D}, P1/Z, [X30, X13,LSL #3]    [5]

0x42249c FMUL	Z24.D, Z24.D, Z2.D

0x4224a0 FMUL	Z25.D, Z25.D, Z25.D

0x4224a4 FMAD	Z22.D, P1/M, Z2.D, Z24.D

0x4224a8 FADD	Z23.D, Z23.D, Z25.D

0x4224ac LD1D	{Z25.D}, P1/Z, [X20, X27,LSL #3]    [4]

0x4224b0 FMUL	Z27.D, Z27.D, Z27.D

0x4224b4 FMUL	Z23.D, Z23.D, Z2.D

0x4224b8 FMAD	Z3.D, P1/M, Z2.D, Z23.D

0x4224bc FMUL	Z23.D, Z25.D, Z25.D

0x4224c0 FMUL	Z25.D, Z26.D, Z26.D

0x4224c4 LD1D	{Z26.D}, P1/Z, [X19, X27,LSL #3]    [18]

0x4224c8 ADD	X27, X20, X7,LSL #3

0x4224cc FADD	Z24.D, Z25.D, Z27.D

0x4224d0 LD1D	{Z25.D}, P1/Z, [X20, X7,LSL #3]    [4]

0x4224d4 FMLA	Z22.D, P1/M, Z24.D, Z2.D

0x4224d8 FMUL	Z26.D, Z26.D, Z26.D

0x4224dc FADD	Z23.D, Z23.D, Z26.D

0x4224e0 LD1D	{Z26.D}, P1/Z, [X27, X13,LSL #3]    [14]

0x4224e4 ADD	X27, X19, X7,LSL #3

0x4224e8 FMUL	Z25.D, Z25.D, Z25.D

0x4224ec LD1D	{Z27.D}, P1/Z, [X27, X13,LSL #3]    [3]

0x4224f0 FMLA	Z3.D, P1/M, Z23.D, Z2.D

0x4224f4 FMUL	Z23.D, Z26.D, Z26.D

0x4224f8 LD1D	{Z26.D}, P1/Z, [X19, X7,LSL #3]    [18]

0x4224fc ADD	X7, X6, X0

0x422500 FMUL	Z27.D, Z27.D, Z27.D

0x422504 ADD	X27, X25, X7,LSL #3

0x422508 LD1D	{Z24.D}, P1/Z, [X25, X7,LSL #3]    [9]

0x42250c FADD	Z23.D, Z23.D, Z27.D

0x422510 LD1D	{Z27.D}, P1/Z, [X26, X7,LSL #3]    [10]

0x422514 FMUL	Z26.D, Z26.D, Z26.D

0x422518 FMLA	Z22.D, P1/M, Z23.D, Z2.D

0x42251c LD1D	{Z23.D}, P1/Z, [X1, X6,LSL #3]    [11]

0x422520 FADD	Z18.D, Z24.D, Z18.D

0x422524 FADD	Z25.D, Z25.D, Z26.D

0x422528 LD1D	{Z26.D}, P1/Z, [X27, X13,LSL #3]    [2]

0x42252c ADD	X27, X26, X7,LSL #3

0x422530 ADD	X7, X1, X6,LSL #3

0x422534 FMUL	Z27.D, Z24.D, Z27.D

0x422538 LD1D	{Z28.D}, P1/Z, [X7, X13,LSL #3]    [13]

0x42253c ADD	X7, X2, X6,LSL #3

0x422540 FMLA	Z3.D, P1/M, Z25.D, Z2.D

0x422544 LD1D	{Z25.D}, P1/Z, [X27, X13,LSL #3]    [1]

0x422548 FADD	Z16.D, Z27.D, Z16.D

0x42254c FMLA	Z6.D, P1/M, Z27.D, Z23.D

0x422550 FMUL	Z27.D, P1/M, Z27.D, #0.0000000

0x422554 FADD	Z17.D, Z26.D, Z17.D

0x422558 FMLA	Z5.D, P1/M, Z3.D, Z27.D

0x42255c LD1D	{Z3.D}, P1/Z, [X2, X6,LSL #3]    [17]

0x422560 FMUL	Z25.D, Z26.D, Z25.D

0x422564 MOVPRFX	Z23, Z25

0x422568 FMUL	Z23.D, P1/M, Z23.D, #0.0000000

0x42256c FMLA	Z20.D, P1/M, Z25.D, Z28.D

0x422570 FADD	Z21.D, Z25.D, Z21.D

0x422574 FMLA	Z4.D, P1/M, Z24.D, Z3.D

0x422578 FMLA	Z19.D, P1/M, Z22.D, Z23.D

0x42257c LD1D	{Z22.D}, P1/Z, [X7, X13,LSL #3]    [12]

0x422580 FMLA	Z7.D, P1/M, Z26.D, Z22.D

0x422584 B.NE	42240c

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 57 - 71

--------------------------------------------------------------------------------

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Coverage (%)	Name	Source Location	Module
►98.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.25+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	field_summary_kernel	field_summary_kernel.f90:77	exec
○	field_summary	field_summary.f90:81	exec
○	hydro	hydro.f90:81	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P6, P7,
Function	_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par
Source	field_summary_kernel.f90:57-71
Source loop unroll info	unrolled by 24
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	24
CQA cycles	23.50
CQA cycles if no scalar integer	23.50
CQA cycles if FP arith vectorized	23.50
CQA cycles if fully vectorized	23.50
Front-end cycles	11.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	5.75
P6 cycles	23.50
P7 cycles	23.50
P8 cycles	23.00
P9 cycles	23.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	95.00
Nb uops	95.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.87
Nb FLOP add-sub	48.00
Nb FLOP mul	88.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.68
Bytes prefetched	0.00
Bytes loaded	768.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	6.00
Vectorization ratio all	95.89
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	92.31
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	97.60
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	93.27
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	56.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P6, P7,
Function	_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par
Source	field_summary_kernel.f90:57-71
Source loop unroll info	unrolled by 24
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	24
CQA cycles	23.50
CQA cycles if no scalar integer	23.50
CQA cycles if FP arith vectorized	23.50
CQA cycles if fully vectorized	23.50
Front-end cycles	11.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	5.75
P6 cycles	23.50
P7 cycles	23.50
P8 cycles	23.00
P9 cycles	23.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	95.00
Nb uops	95.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.87
Nb FLOP add-sub	48.00
Nb FLOP mul	88.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.68
Bytes prefetched	0.00
Bytes loaded	768.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	6.00
Vectorization ratio all	95.89
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	92.31
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	97.60
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	93.27
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	56.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par
Source file and lines	field_summary_kernel.f90:57-71
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:57-71.

The related source loop is unrolled by 24 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 48 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 12 occurrence(s)
Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 232 FP arithmetical operations:

96: addition or subtraction (48 inside FMA instructions)
136: multiply (48 inside FMA instructions)

The binary loop is loading 768 bytes.

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	95
nb uops	95
loop length	380
used w registers	5
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	19
nb stack references	0
ADD-SUB / MUL ratio	0.55

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.88 cycles
front end	11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.75	5.75	5.75	5.75	23.50	23.50	0.00	0.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	5.75	5.75	5.75	5.75	23.50	23.50	23.00	23.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	11.88
Dispatch	23.50
Data deps.	2.00
Overall L1	23.50

Vectorization ratios

INT

all	88%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	92%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	93%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.50 cycles. At this rate:

34% of peak load performance is reached (32.68 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42240c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
ADD W6, W10, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD W5, W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SBFM X6, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP W16, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
SUB X6, X6, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X27, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z3.D}, P1/Z, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X7, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X30, X20, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z25.D}, P1/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X19, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X20, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z24.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X27, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X30, X20, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FADD Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X19, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z22.D, P1/M, Z2.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z23.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X20, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z23.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z3.D, P1/M, Z2.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z23.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z25.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FADD Z24.D, Z25.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z22.D, P1/M, Z24.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z3.D, P1/M, Z23.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z23.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z27.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X27, X25, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P1/Z, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z23.D, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z22.D, P1/M, Z23.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X1, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z18.D, Z24.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z25.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X26, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X1, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z27.D, Z24.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z28.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X2, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMLA Z3.D, P1/M, Z25.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z16.D, Z27.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z6.D, P1/M, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, P1/M, Z27.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z17.D, Z26.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z5.D, P1/M, Z3.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P1/Z, [X2, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z25.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z23, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z23.D, P1/M, Z23.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z20.D, P1/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z21.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z24.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z22.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z7.D, P1/M, Z26.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
B.NE 42240c <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par
Source file and lines	field_summary_kernel.f90:57-71
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 48 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 12 occurrence(s)
Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 232 FP arithmetical operations:

96: addition or subtraction (48 inside FMA instructions)
136: multiply (48 inside FMA instructions)

The binary loop is loading 768 bytes.

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	95
nb uops	95
loop length	380
used w registers	5
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	19
nb stack references	0
ADD-SUB / MUL ratio	0.55

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.88 cycles
front end	11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.75	5.75	5.75	5.75	23.50	23.50	0.00	0.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	5.75	5.75	5.75	5.75	23.50	23.50	23.00	23.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	11.88
Dispatch	23.50
Data deps.	2.00
Overall L1	23.50

Vectorization ratios

INT

all	88%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	92%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	93%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.50 cycles. At this rate:

34% of peak load performance is reached (32.68 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42240c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
ADD W6, W10, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD W5, W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SBFM X6, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP W16, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
SUB X6, X6, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X27, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z3.D}, P1/Z, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X7, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X30, X20, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z25.D}, P1/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X19, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X20, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z24.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X27, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X30, X20, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FADD Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X19, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z22.D, P1/M, Z2.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z23.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X20, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z23.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z3.D, P1/M, Z2.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z23.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z25.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FADD Z24.D, Z25.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z22.D, P1/M, Z24.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z3.D, P1/M, Z23.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z23.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z27.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X27, X25, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P1/Z, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z23.D, Z23.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z22.D, P1/M, Z23.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X1, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z18.D, Z24.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z25.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X26, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X1, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z27.D, Z24.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z28.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X2, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMLA Z3.D, P1/M, Z25.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z16.D, Z27.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z6.D, P1/M, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, P1/M, Z27.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z17.D, Z26.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z5.D, P1/M, Z3.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P1/Z, [X2, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z25.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z23, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z23.D, P1/M, Z23.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z20.D, P1/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z21.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z24.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z22.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z7.D, P1/M, Z26.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
B.NE 42240c <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code