OV - exec - Loop 298

	Loop Id: 298	Module: exec	Source: generate_chunk_kernel.f90:127-137	Coverage: 0.01%

0x424708 ADD	W23, W21, #1

0x42470c SBFM	X10, X21, #0, #31

0x424710 ADD	W30, W30, W25

0x424714 ADD	W21, W21, W25

0x424718 SBFM	X23, X23, #0, #31

0x42471c SUB	X10, X10, X20

0x424720 SUB	X23, X23, X20

0x424724 LD1D	{Z4.D}, P2/Z, [X28, X23,LSL #3]    [3]

0x424728 ADD	X23, X10, X6

0x42472c FCMGE	P1.D, P3/Z, Z4.D, Z2.D

0x424730 LD1D	{Z4.D}, P2/Z, [X28, X10,LSL #3]    [3]

0x424734 FCMGT	P1.D, P1/Z, Z3.D, Z4.D

0x424738 AND	P1.B, P2/Z, P2.B, P1.B

0x42473c LD1D	{Z4.D}, P1/Z, [X2, Z16.D,LSL #3]    [9]

0x424740 LD1D	{Z5.D}, P1/Z, [X26, Z16.D,LSL #3]    [13]

0x424744 LD1D	{Z6.D}, P1/Z, [X3, Z16.D,LSL #3]    [10]

0x424748 LD1D	{Z7.D}, P1/Z, [X15, Z16.D,LSL #3]    [5]

0x42474c FCMGE	P2.D, P3/Z, Z4.D, Z5.D

0x424750 FCMGT	P2.D, P2/Z, Z7.D, Z6.D

0x424754 AND	P1.B, P1/Z, P1.B, P2.B

0x424758 WHILELO	P2.D, W30, W18

0x42475c LD1D	{Z4.D}, P1/Z, [X11, Z16.D,LSL #3]    [4]

0x424760 ST1D	{Z4.D}, P1, [X4, X10,LSL #3]    [11]

0x424764 LD1D	{Z4.D}, P1/Z, [X12, Z16.D,LSL #3]    [6]

0x424768 ST1D	{Z4.D}, P1, [X5, X10,LSL #3]    [12]

0x42476c LD1D	{Z4.D}, P1/Z, [X13, Z16.D,LSL #3]    [7]

0x424770 LD1D	{Z5.D}, P1/Z, [X14, Z16.D,LSL #3]    [8]

0x424774 ST1D	{Z4.D}, P1, [X27, X23,LSL #3]    [2]

0x424778 ST1D	{Z5.D}, P1, [X24, X23,LSL #3]    [1]

0x42477c ADD	X23, X10, #1

0x424780 ADD	X10, X10, X7

0x424784 ADD	X19, X23, X6

0x424788 ST1D	{Z4.D}, P1, [X27, X19,LSL #3]    [2]

0x42478c ST1D	{Z5.D}, P1, [X24, X19,LSL #3]    [1]

0x424790 ADD	X19, X23, X7

0x424794 ST1D	{Z4.D}, P1, [X27, X10,LSL #3]    [2]

0x424798 ST1D	{Z5.D}, P1, [X24, X10,LSL #3]    [1]

0x42479c ST1D	{Z4.D}, P1, [X27, X19,LSL #3]    [2]

0x4247a0 ST1D	{Z5.D}, P1, [X24, X19,LSL #3]    [1]

0x4247a4 B.MI	424708

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 127 - 137

--------------------------------------------------------------------------------

127:       !$OMP SIMD

128:         DO j=x_min-2,x_max+2

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

Coverage (%)	Name	Source Location	Module
►98.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:50	exec
○	start	start.f90:106	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par
Source	generate_chunk_kernel.f90:127-137
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	10.00
Front-end cycles	5.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	4.00
P7 cycles	3.50
P8 cycles	3.25
P9 cycles	3.25
P10 cycles	10.00
P11 cycles	10.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	320.00
Stride 0	8.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	5.00
Vectorization ratio all	92.86
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	87.50
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	70.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par
Source	generate_chunk_kernel.f90:127-137
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	10.00
Front-end cycles	5.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	4.00
P7 cycles	3.50
P8 cycles	3.25
P9 cycles	3.25
P10 cycles	10.00
P11 cycles	10.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	320.00
Stride 0	8.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	5.00
Vectorization ratio all	92.86
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	87.50
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	70.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par
Source file and lines	generate_chunk_kernel.f90:127-137
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:127-137.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 87% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 320 bytes. The binary loop is storing 320 bytes.

General properties

nb instructions	40
nb uops	40
loop length	160
used w registers	5
used x registers	20
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	7
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.75	3.75	3.75	3.75	4.00	3.50	3.25	3.25	10.00	10.00	0.00	0.00	0.00
cycles	0.50	0.50	3.75	3.75	3.75	3.75	4.00	3.50	3.25	3.25	10.00	10.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Dispatch	10.00
Data deps.	1.00
Overall L1	10.00

Vectorization ratios

INT

all	91%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	92%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	87%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
66% of peak store performance is reached (32.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424708

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD W23, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X10, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W30, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W21, W21, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X23, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X10, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X23, X23, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z4.D}, P2/Z, [X28, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X23, X10, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FCMGE P1.D, P3/Z, Z4.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X28, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P1.D, P1/Z, Z3.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
AND P1.B, P2/Z, P2.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z4.D}, P1/Z, [X2, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [X26, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P1/Z, [X3, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P1/Z, [X15, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGE P2.D, P3/Z, Z4.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P2.D, P2/Z, Z7.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
AND P1.B, P1/Z, P1.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
WHILELO P2.D, W30, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
LD1D {Z4.D}, P1/Z, [X11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z4.D}, P1, [X4, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X12, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z4.D}, P1, [X5, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X13, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [X14, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z4.D}, P1, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z5.D}, P1, [X24, X23,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X23, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X23, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z4.D}, P1, [X27, X19,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z5.D}, P1, [X24, X19,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X19, X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z4.D}, P1, [X27, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z5.D}, P1, [X24, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z4.D}, P1, [X27, X19,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z5.D}, P1, [X24, X19,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
B.MI 424708 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par
Source file and lines	generate_chunk_kernel.f90:127-137
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 87% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 320 bytes. The binary loop is storing 320 bytes.

General properties

nb instructions	40
nb uops	40
loop length	160
used w registers	5
used x registers	20
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	7
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.75	3.75	3.75	3.75	4.00	3.50	3.25	3.25	10.00	10.00	0.00	0.00	0.00
cycles	0.50	0.50	3.75	3.75	3.75	3.75	4.00	3.50	3.25	3.25	10.00	10.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Dispatch	10.00
Data deps.	1.00
Overall L1	10.00

Vectorization ratios

INT

all	91%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	92%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	87%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
66% of peak store performance is reached (32.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424708

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD W23, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X10, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W30, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W21, W21, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X23, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X10, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X23, X23, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z4.D}, P2/Z, [X28, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X23, X10, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FCMGE P1.D, P3/Z, Z4.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X28, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P1.D, P1/Z, Z3.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
AND P1.B, P2/Z, P2.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z4.D}, P1/Z, [X2, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [X26, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P1/Z, [X3, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P1/Z, [X15, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGE P2.D, P3/Z, Z4.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P2.D, P2/Z, Z7.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
AND P1.B, P1/Z, P1.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
WHILELO P2.D, W30, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
LD1D {Z4.D}, P1/Z, [X11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z4.D}, P1, [X4, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X12, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z4.D}, P1, [X5, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X13, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [X14, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z4.D}, P1, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z5.D}, P1, [X24, X23,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X23, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X23, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z4.D}, P1, [X27, X19,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z5.D}, P1, [X24, X19,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X19, X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z4.D}, P1, [X27, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z5.D}, P1, [X24, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z4.D}, P1, [X27, X19,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z5.D}, P1, [X24, X19,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
B.MI 424708 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code