OV - exec - Loop 41

	Loop Id: 41	Module: exec	Source: PdV_kernel.f90:110-135 [...]	Coverage: 7.91%

0x4170ec SBFM	X4, X2, #0, #31

0x4170f0 ADD	W7, W2, #1

0x4170f4 ADD	W3, W3, W15

0x4170f8 ADD	W2, W2, W15

0x4170fc SUB	X4, X4, X25

0x417100 SBFM	X7, X7, #0, #31

0x417104 ADD	X5, X4, X17

0x417108 ADD	X6, X4, X18

0x41710c SUB	X7, X7, X25

0x417110 ADD	X13, X4, X0

0x417114 LD1D	{Z7.D}, P2/Z, [X21, X5,LSL #3]    [4]

0x417118 LD1D	{Z16.D}, P2/Z, [X21, X6,LSL #3]    [4]

0x41711c ADD	X30, X7, X17

0x417120 ADD	X7, X7, X18

0x417124 LD1D	{Z6.D}, P2/Z, [X20, X5,LSL #3]    [2]

0x417128 LD1D	{Z17.D}, P2/Z, [X21, X7,LSL #3]    [4]

0x41712c LD1D	{Z18.D}, P2/Z, [X23, X30,LSL #3]    [7]

0x417130 LD1D	{Z19.D}, P2/Z, [X23, X7,LSL #3]    [7]

0x417134 FADD	Z7.D, Z7.D, Z16.D

0x417138 LD1D	{Z16.D}, P2/Z, [X26, X5,LSL #3]    [10]

0x41713c FADD	Z7.D, Z7.D, Z16.D

0x417140 LD1D	{Z16.D}, P2/Z, [X26, X6,LSL #3]    [10]

0x417144 FADD	Z7.D, Z7.D, Z16.D

0x417148 LD1D	{Z16.D}, P2/Z, [X21, X30,LSL #3]    [4]

0x41714c FMUL	Z6.D, Z6.D, Z7.D

0x417150 LD1D	{Z7.D}, P2/Z, [X20, X30,LSL #3]    [2]

0x417154 FMUL	Z6.D, Z6.D, Z4.D

0x417158 FADD	Z16.D, Z16.D, Z17.D

0x41715c LD1D	{Z17.D}, P2/Z, [X26, X30,LSL #3]    [10]

0x417160 FMUL	Z6.D, Z1.D, Z6.D

0x417164 FADD	Z16.D, Z16.D, Z17.D

0x417168 LD1D	{Z17.D}, P2/Z, [X26, X7,LSL #3]    [10]

0x41716c FADD	Z16.D, Z16.D, Z17.D

0x417170 LD1D	{Z17.D}, P2/Z, [X23, X5,LSL #3]    [7]

0x417174 FMUL	Z7.D, Z7.D, Z16.D

0x417178 LD1D	{Z16.D}, P2/Z, [X22, X13,LSL #3]    [6]

0x41717c FMUL	Z7.D, Z7.D, Z4.D

0x417180 FADD	Z17.D, Z17.D, Z18.D

0x417184 LD1D	{Z18.D}, P2/Z, [X27, X5,LSL #3]    [12]

0x417188 FNMLS	Z6.D, P1/M, Z1.D, Z7.D

0x41718c FADD	Z17.D, Z17.D, Z18.D

0x417190 LD1D	{Z18.D}, P2/Z, [X27, X30,LSL #3]    [12]

0x417194 LDUR	X30, [X29, #472]    [15]

0x417198 LD1D	{Z7.D}, P2/Z, [X30, X13,LSL #3]    [3]

0x41719c FADD	Z17.D, Z17.D, Z18.D

0x4171a0 LD1D	{Z18.D}, P2/Z, [X23, X6,LSL #3]    [7]

0x4171a4 FMUL	Z16.D, Z16.D, Z17.D

0x4171a8 LD1D	{Z17.D}, P2/Z, [X1, X4,LSL #3]    [11]

0x4171ac FMUL	Z16.D, Z16.D, Z4.D

0x4171b0 FADD	Z18.D, Z18.D, Z19.D

0x4171b4 LD1D	{Z19.D}, P2/Z, [X27, X6,LSL #3]    [12]

0x4171b8 FADD	Z18.D, Z18.D, Z19.D

0x4171bc LD1D	{Z19.D}, P2/Z, [X27, X7,LSL #3]    [12]

0x4171c0 FADD	Z18.D, Z18.D, Z19.D

0x4171c4 LD1D	{Z19.D}, P2/Z, [X8, X13,LSL #3]    [1]

0x4171c8 FMUL	Z17.D, Z17.D, Z18.D

0x4171cc LD1D	{Z18.D}, P2/Z, [X14, X13,LSL #3]    [8]

0x4171d0 FMUL	Z17.D, Z17.D, Z4.D

0x4171d4 FMLA	Z6.D, P1/M, Z1.D, Z17.D

0x4171d8 LD1D	{Z17.D}, P2/Z, [X12, X13,LSL #3]    [5]

0x4171dc FDIV	Z19.D, P1/M, Z19.D, Z18.D

0x4171e0 FMLS	Z6.D, P1/M, Z1.D, Z16.D

0x4171e4 FDIV	Z17.D, P1/M, Z17.D, Z18.D

0x4171e8 FADD	Z16.D, Z7.D, Z6.D

0x4171ec FADD	Z17.D, Z17.D, Z19.D

0x4171f0 MOVPRFX	Z19, Z5

0x4171f4 FDIV	Z19.D, P1/M, Z19.D, Z7.D

0x4171f8 FDIV	Z7.D, P1/M, Z7.D, Z16.D

0x4171fc FMUL	Z6.D, Z17.D, Z6.D

0x417200 LD1D	{Z17.D}, P2/Z, [X28, X13,LSL #3]    [13]

0x417204 FMSB	Z6.D, P1/M, Z19.D, Z17.D

0x417208 ST1D	{Z6.D}, P2, [X19, X13,LSL #3]    [14]

0x41720c FMUL	Z6.D, Z18.D, Z7.D

0x417210 ST1D	{Z6.D}, P2, [X24, X13,LSL #3]    [9]

0x417214 WHILELO	P2.D, W3, W16

0x417218 B.MI	4170ec

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 110 - 135

--------------------------------------------------------------------------------

110:       !$OMP SIMD

111:         DO j=x_min,x_max

112:

113:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:58	exec
○	hydro	hydro.f90:60	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.65 - 3.31
Bottlenecks	P6, P8,
Function	_QMpdv_kernel_modulePpdv_kernel..omp_par
Source	PdV_kernel.f90:110-123,PdV_kernel.f90:129-135
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	9.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	17.00
P7 cycles	17.00
P8 cycles	14.50
P9 cycles	14.50
P10 cycles	13.50
P11 cycles	13.50
P12 cycles	1.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	76.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.29 - 2.63
Nb FLOP add-sub	56.00
Nb FLOP mul	44.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.34 - 30.89
Bytes prefetched	0.00
Bytes loaded	800.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	14.00
Vectorization ratio all	96.77
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	93.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.59
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	94.17
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.65 - 3.31
Bottlenecks	P6, P8,
Function	_QMpdv_kernel_modulePpdv_kernel..omp_par
Source	PdV_kernel.f90:110-123,PdV_kernel.f90:129-135
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	9.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	17.00
P7 cycles	17.00
P8 cycles	14.50
P9 cycles	14.50
P10 cycles	13.50
P11 cycles	13.50
P12 cycles	1.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	76.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.29 - 2.63
Nb FLOP add-sub	56.00
Nb FLOP mul	44.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.34 - 30.89
Bytes prefetched	0.00
Bytes loaded	800.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	14.00
Vectorization ratio all	96.77
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	93.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.59
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	94.17
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMpdv_kernel_modulePpdv_kernel..omp_par
Source file and lines	PdV_kernel.f90:110-135
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:110-123,129-135.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

96% of VPU instructions are used in vector version (process two or more data elements in vector registers):

93% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 15.00 cycles (3.76x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 14 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
60: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 800 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	76
loop length	304
used w registers	5
used x registers	25
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	9
nb stack references	0
ADD-SUB / MUL ratio	1.27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.25	3.25	3.25	3.25	17.00	17.00	1.00	1.00	13.50	13.50	1.00	0.00	0.00
cycles	0.50	0.50	3.25	3.25	3.25	3.25	17.00	17.00	14.50	14.50	13.50	13.50	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.50
Dispatch	17.00
DIV/SQRT	27.97-56.34
Data deps.	1.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	93%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

14% of peak load performance is reached (14.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4170ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SBFM X4, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W3, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X4, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X7, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z7.D}, P2/Z, [X21, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X21, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X30, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P2/Z, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X21, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X26, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X26, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z6.D, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z7.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X27, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FNMLS Z6.D, P1/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X27, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDUR X30, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z7.D}, P2/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X23, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X27, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X14, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z6.D, P1/M, Z1.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X12, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z6.D, P1/M, Z1.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z17.D, P1/M, Z17.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z16.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z19, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z7.D, P1/M, Z7.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z6.D, Z17.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X28, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMSB Z6.D, P1/M, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z6.D}, P2, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
FMUL Z6.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z6.D}, P2, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
WHILELO P2.D, W3, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 4170ec <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMpdv_kernel_modulePpdv_kernel..omp_par
Source file and lines	PdV_kernel.f90:110-135
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

96% of VPU instructions are used in vector version (process two or more data elements in vector registers):

93% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 15.00 cycles (3.76x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 14 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
60: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 800 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	76
loop length	304
used w registers	5
used x registers	25
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	9
nb stack references	0
ADD-SUB / MUL ratio	1.27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.25	3.25	3.25	3.25	17.00	17.00	1.00	1.00	13.50	13.50	1.00	0.00	0.00
cycles	0.50	0.50	3.25	3.25	3.25	3.25	17.00	17.00	14.50	14.50	13.50	13.50	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.50
Dispatch	17.00
DIV/SQRT	27.97-56.34
Data deps.	1.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	93%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

14% of peak load performance is reached (14.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4170ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SBFM X4, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W3, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X4, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X7, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z7.D}, P2/Z, [X21, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X21, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X30, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P2/Z, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X21, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X26, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X26, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z6.D, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z7.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X27, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FNMLS Z6.D, P1/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X27, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDUR X30, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z7.D}, P2/Z, [X30, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X23, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X27, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X14, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z6.D, P1/M, Z1.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X12, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z6.D, P1/M, Z1.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z17.D, P1/M, Z17.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z16.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z19, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z7.D, P1/M, Z7.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z6.D, Z17.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X28, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMSB Z6.D, P1/M, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z6.D}, P2, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
FMUL Z6.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z6.D}, P2, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
WHILELO P2.D, W3, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 4170ec <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code