OV - exec - Loop 44

	Loop Id: 44	Module: exec	Source: PdV_kernel.f90:71-99 [...]	Coverage: 6.38%

  (46) 0x416ba0 CMP	W12, W8

  (46) 0x416ba4 ADD	W12, W12, #1

  (46) 0x416ba8 B.EQ	416e60

  (46) 0x416bac LDR	W11, [SP, #48]

  (46) 0x416bb0 SUB	X3, XZR, X15

  (46) 0x416bb4 ORR	P2.B, P0/Z, P0.B, P0.B

  (46) 0x416bb8 ORR	W2, WZR, W9

  (46) 0x416bbc ADD	W18, W11, W12

  (46) 0x416bc0 LDP	X13, X11, [SP, #64]

  (46) 0x416bc4 SBFM	X17, X18, #0, #31

  (46) 0x416bc8 ADD	W18, W18, #1

  (46) 0x416bcc SBFM	X18, X18, #0, #31

  (46) 0x416bd0 SUB	X0, X17, X13

  (46) 0x416bd4 SUB	X1, X18, X13

  (46) 0x416bd8 LDR	W13, [SP, #40]

  (46) 0x416bdc MUL	X17, X0, X11

  (46) 0x416be0 MUL	X18, X1, X11

  (46) 0x416be4 LDR	X11, [SP, #56]

  (46) 0x416be8 MUL	X0, X0, X11

  (46) 0x416bec MUL	X1, X1, X11

  (46) 0x416bf0 ADD	W11, W9, #1

  (46) 0x416bf4 CMP	W13, W11

  (46) 0x416bf8 LDP	X11, X13, [X29, #968]

  (46) 0x416bfc ADD	X1, X22, X1,LSL #3

  (46) 0x416c00 B.GE	416d40

  (46) 0x416c04 ORR	W2, WZR, WZR

    (45) 0x416c08 ADD	W3, W9, W2

    (45) 0x416c0c ADD	W2, W2, #1

    (45) 0x416c10 SBFM	X4, X3, #0, #31

    (45) 0x416c14 ADD	W3, W3, #1

    (45) 0x416c18 CMP	W10, W2

    (45) 0x416c1c SUB	X4, X4, X25

    (45) 0x416c20 SBFM	X3, X3, #0, #31

    (45) 0x416c24 ADD	X5, X4, X17

    (45) 0x416c28 ADD	X6, X4, X18

    (45) 0x416c2c SUB	X3, X3, X25

    (45) 0x416c30 ADD	X26, X4, X0

    (45) 0x416c34 LDR	D19, [X21, X5,LSL #3]

    (45) 0x416c38 LDR	D20, [X21, X6,LSL #3]

    (45) 0x416c3c ADD	X7, X3, X17

    (45) 0x416c40 ADD	X3, X3, X18

    (45) 0x416c44 LDR	D18, [X20, X5,LSL #3]

    (45) 0x416c48 ADD	X30, X22, X26,LSL #3

    (45) 0x416c4c UBFM	X27, X26, #61, #60

    (45) 0x416c50 LDR	D23, [X23, X3,LSL #3]

    (45) 0x416c54 FADD	D21, D19, D20

    (45) 0x416c58 FADD	D19, D19, D21

    (45) 0x416c5c LDR	D21, [X21, X3,LSL #3]

    (45) 0x416c60 FADD	D19, D20, D19

    (45) 0x416c64 LDR	D20, [X21, X7,LSL #3]

    (45) 0x416c68 FMUL	D18, D18, D19

    (45) 0x416c6c LDR	D19, [X20, X7,LSL #3]

    (45) 0x416c70 FMUL	D18, D18, D2

    (45) 0x416c74 FADD	D22, D20, D21

    (45) 0x416c78 FADD	D20, D20, D22

    (45) 0x416c7c LDR	D22, [X23, X6,LSL #3]

    (45) 0x416c80 FMUL	D18, D0, D18

    (45) 0x416c84 FADD	D20, D21, D20

    (45) 0x416c88 LDR	D21, [X23, X7,LSL #3]

    (45) 0x416c8c FMUL	D18, D18, D3

    (45) 0x416c90 FMUL	D19, D19, D20

    (45) 0x416c94 LDR	D20, [X23, X5,LSL #3]

    (45) 0x416c98 FADD	D25, D22, D23

    (45) 0x416c9c FMUL	D19, D19, D2

    (45) 0x416ca0 FADD	D22, D22, D25

    (45) 0x416ca4 FADD	D24, D20, D21

    (45) 0x416ca8 FMUL	D19, D0, D19

    (45) 0x416cac FADD	D20, D20, D24

    (45) 0x416cb0 FNMSUB	D18, D19, D3, D18

    (45) 0x416cb4 FADD	D20, D21, D20

    (45) 0x416cb8 FADD	D21, D23, D22

    (45) 0x416cbc LDR	D22, [X1, X4,LSL #3]

    (45) 0x416cc0 LDR	D23, [X14, X27]

    (45) 0x416cc4 MOV	V21.D[1], V20.D[0]

    (45) 0x416cc8 LD1	{V22.D[1]}, [X30]

    (45) 0x416ccc LDUR	X30, [X29, #472]

    (45) 0x416cd0 FMUL	V20.2D, V22.2D, V21.2D

    (45) 0x416cd4 LDR	D22, [X11, X27]

    (45) 0x416cd8 FMUL	V20.2D, V20.2D, V4.2D

    (45) 0x416cdc FMUL	V20.2D, V20.2D, V0.D[0]

    (45) 0x416ce0 FDIV	D23, D23, D22

    (45) 0x416ce4 FMUL	V20.2D, V20.2D, V5.2D

    (45) 0x416ce8 FADD	D18, D18, D20

    (45) 0x416cec MOV	D19, V20.D[1]

    (45) 0x416cf0 FSUB	D18, D18, S19

    (45) 0x416cf4 LDR	D19, [X30, X27]

    (45) 0x416cf8 FADD	D20, D19, D18

    (45) 0x416cfc FDIV	D21, D6, D19

    (45) 0x416d00 FDIV	D19, D19, D20

    (45) 0x416d04 LDR	D20, [X13, X27]

    (45) 0x416d08 FDIV	D20, D20, D22

    (45) 0x416d0c FADD	D20, D20, D23

    (45) 0x416d10 LDR	D23, [X28, X27]

    (45) 0x416d14 FMUL	D18, D20, D18

    (45) 0x416d18 FMADD	D18, D21, D18, D23

    (45) 0x416d1c STR	D18, [X19, X26,LSL #3]

    (45) 0x416d20 FMUL	D18, D22, D19

    (45) 0x416d24 STR	D18, [X24, X26,LSL #3]

    (45) 0x416d28 B.HI	416c08

  (46) 0x416d2c B	416ba0

0x416d40 SBFM	X4, X2, #0, #31

0x416d44 ADD	W7, W2, #1

0x416d48 ADD	W3, W3, W15

0x416d4c ADD	W2, W2, W15

0x416d50 SUB	X4, X4, X25

0x416d54 SBFM	X7, X7, #0, #31

0x416d58 ADD	X5, X4, X17

0x416d5c ADD	X6, X4, X18

0x416d60 SUB	X7, X7, X25

0x416d64 ADD	X27, X4, X0

0x416d68 LD1D	{Z19.D}, P2/Z, [X21, X5,LSL #3]

0x416d6c LD1D	{Z20.D}, P2/Z, [X21, X6,LSL #3]

0x416d70 ADD	X26, X7, X17

0x416d74 ADD	X7, X7, X18

0x416d78 LD1D	{Z18.D}, P2/Z, [X20, X5,LSL #3]

0x416d7c FADD	Z21.D, Z19.D, Z20.D

0x416d80 FADD	Z19.D, Z19.D, Z21.D

0x416d84 LD1D	{Z21.D}, P2/Z, [X21, X7,LSL #3]

0x416d88 FADD	Z19.D, Z20.D, Z19.D

0x416d8c LD1D	{Z20.D}, P2/Z, [X21, X26,LSL #3]

0x416d90 FMUL	Z18.D, Z18.D, Z19.D

0x416d94 LD1D	{Z19.D}, P2/Z, [X20, X26,LSL #3]

0x416d98 FMUL	Z18.D, Z18.D, Z7.D

0x416d9c FADD	Z22.D, Z20.D, Z21.D

0x416da0 FADD	Z20.D, Z20.D, Z22.D

0x416da4 LD1D	{Z22.D}, P2/Z, [X23, X26,LSL #3]

0x416da8 FMUL	Z18.D, Z1.D, Z18.D

0x416dac FADD	Z20.D, Z21.D, Z20.D

0x416db0 LD1D	{Z21.D}, P2/Z, [X23, X5,LSL #3]

0x416db4 FMUL	Z18.D, P1/M, Z18.D, #0.0000000

0x416db8 FMUL	Z19.D, Z19.D, Z20.D

0x416dbc LD1D	{Z20.D}, P2/Z, [X22, X27,LSL #3]

0x416dc0 FMUL	Z19.D, Z19.D, Z7.D

0x416dc4 FADD	Z23.D, Z21.D, Z22.D

0x416dc8 FADD	Z21.D, Z21.D, Z23.D

0x416dcc LD1D	{Z23.D}, P2/Z, [X23, X7,LSL #3]

0x416dd0 FMUL	Z19.D, Z1.D, Z19.D

0x416dd4 FADD	Z21.D, Z22.D, Z21.D

0x416dd8 LD1D	{Z22.D}, P2/Z, [X23, X6,LSL #3]

0x416ddc FNMLS	Z18.D, P1/M, Z19.D, Z16.D

0x416de0 LD1D	{Z19.D}, P2/Z, [X30, X27,LSL #3]

0x416de4 FMUL	Z20.D, Z20.D, Z21.D

0x416de8 LD1D	{Z21.D}, P2/Z, [X1, X4,LSL #3]

0x416dec FMUL	Z20.D, Z20.D, Z7.D

0x416df0 FADD	Z24.D, Z22.D, Z23.D

0x416df4 FADD	Z22.D, Z22.D, Z24.D

0x416df8 LD1D	{Z24.D}, P2/Z, [X14, X27,LSL #3]

0x416dfc FMUL	Z20.D, Z1.D, Z20.D

0x416e00 FADD	Z22.D, Z23.D, Z22.D

0x416e04 LD1D	{Z23.D}, P2/Z, [X11, X27,LSL #3]

0x416e08 FMUL	Z21.D, Z21.D, Z22.D

0x416e0c LD1D	{Z22.D}, P2/Z, [X13, X27,LSL #3]

0x416e10 FMUL	Z21.D, Z21.D, Z7.D

0x416e14 FDIV	Z24.D, P1/M, Z24.D, Z23.D

0x416e18 FDIV	Z22.D, P1/M, Z22.D, Z23.D

0x416e1c FMUL	Z21.D, Z1.D, Z21.D

0x416e20 FMLA	Z18.D, P1/M, Z21.D, Z16.D

0x416e24 MOVPRFX	Z21, Z17

0x416e28 FDIV	Z21.D, P1/M, Z21.D, Z19.D

0x416e2c FMLS	Z18.D, P1/M, Z20.D, Z16.D

0x416e30 FADD	Z20.D, Z19.D, Z18.D

0x416e34 FDIV	Z19.D, P1/M, Z19.D, Z20.D

0x416e38 FADD	Z22.D, Z22.D, Z24.D

0x416e3c FMUL	Z18.D, Z22.D, Z18.D

0x416e40 LD1D	{Z22.D}, P2/Z, [X28, X27,LSL #3]

0x416e44 FMSB	Z18.D, P1/M, Z21.D, Z22.D

0x416e48 ST1D	{Z18.D}, P2, [X19, X27,LSL #3]

0x416e4c FMUL	Z18.D, Z23.D, Z19.D

0x416e50 ST1D	{Z18.D}, P2, [X24, X27,LSL #3]

0x416e54 WHILELO	P2.D, W3, W16

0x416e58 B.MI	416d40

0x416e5c B	416ba0

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 71 - 99

--------------------------------------------------------------------------------

71:       !$OMP DO PRIVATE(right_flux,left_flux,top_flux,bottom_flux,total_flux,min_cell_volume, &

72:       !$OMP            energy_change,recip_volume,volume_change_s)

73:       DO k=y_min,y_max

74:       !$OMP SIMD

75:         DO j=x_min,x_max

76:

77:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

78:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

79:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

80:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

81:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

82:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

83:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

84:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

85:           total_flux=right_flux-left_flux+top_flux-bottom_flux

86:

87:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

93:           recip_volume=1.0/volume(j,k)

94:

95:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

96:

97:           energy1(j,k)=energy0(j,k)-energy_change

98:

99:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:58	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47 - 2.97
Bottlenecks	P6, P8,
Function	_QMpdv_kernel_modulePpdv_kernel..omp_par
Source	PdV_kernel.f90:74-74,PdV_kernel.f90:77-87,PdV_kernel.f90:93-99
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	9.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	19.00
P7 cycles	19.00
P8 cycles	16.50
P9 cycles	16.50
P10 cycles	9.50
P11 cycles	9.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.86 - 2.91
Nb FLOP add-sub	56.00
Nb FLOP mul	60.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.79 - 21.74
Bytes prefetched	0.00
Bytes loaded	544.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	96.55
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	93.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.49
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	94.17
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47 - 2.97
Bottlenecks	P6, P8,
Function	_QMpdv_kernel_modulePpdv_kernel..omp_par
Source	PdV_kernel.f90:74-74,PdV_kernel.f90:77-87,PdV_kernel.f90:93-99
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	9.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	19.00
P7 cycles	19.00
P8 cycles	16.50
P9 cycles	16.50
P10 cycles	9.50
P11 cycles	9.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.86 - 2.91
Nb FLOP add-sub	56.00
Nb FLOP mul	60.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.79 - 21.74
Bytes prefetched	0.00
Bytes loaded	544.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	96.55
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	93.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.49
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	94.17
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMpdv_kernel_modulePpdv_kernel..omp_par
Source file and lines	PdV_kernel.f90:71-99
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:71-87,93-99.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:74,77-87,93-99.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

96% of VPU instructions are used in vector version (process two or more data elements in vector registers):

93% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 17.00 cycles (3.31x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
76: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 544 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	72
nb uops	72
loop length	288
used w registers	5
used x registers	23
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	11
nb stack references	0
ADD-SUB / MUL ratio	0.93

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	3.25	3.25	3.25	3.25	19.00	19.00	1.00	1.00	9.50	9.50	0.00	0.00	0.00
cycles	1.00	1.00	3.25	3.25	3.25	3.25	19.00	19.00	16.50	16.50	9.50	9.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

27.97-56.34

Cycles summary

Front-end	9.00
Dispatch	19.00
DIV/SQRT	27.97-56.34
Overall L1	27.97-56.34

Vectorization ratios

INT

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	93%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	95%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

10% of peak load performance is reached (9.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 416d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X4, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W3, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X4, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X7, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X27, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z19.D}, P2/Z, [X21, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X21, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X26, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z18.D}, P2/Z, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z21.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, Z19.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X21, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X21, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X20, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z22.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z20.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X23, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z1.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z20.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, P1/M, Z18.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X22, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z19.D, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z19.D, Z1.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z22.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X23, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FNMLS Z18.D, P1/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X30, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z20.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z24.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z1.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z22.D, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X11, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X13, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z24.D, P1/M, Z24.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z22.D, P1/M, Z22.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z21.D, Z1.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z21.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z21, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z21.D, P1/M, Z21.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z18.D, P1/M, Z20.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z20.D, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z22.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X28, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMSB Z18.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z18.D}, P2, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z18.D, Z23.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z18.D}, P2, [X24, X27,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W3, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 416d40 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 416ba0 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMpdv_kernel_modulePpdv_kernel..omp_par
Source file and lines	PdV_kernel.f90:71-99
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

96% of VPU instructions are used in vector version (process two or more data elements in vector registers):

93% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 17.00 cycles (3.31x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
76: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 544 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	72
nb uops	72
loop length	288
used w registers	5
used x registers	23
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	11
nb stack references	0
ADD-SUB / MUL ratio	0.93

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	3.25	3.25	3.25	3.25	19.00	19.00	1.00	1.00	9.50	9.50	0.00	0.00	0.00
cycles	1.00	1.00	3.25	3.25	3.25	3.25	19.00	19.00	16.50	16.50	9.50	9.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

27.97-56.34

Cycles summary

Front-end	9.00
Dispatch	19.00
DIV/SQRT	27.97-56.34
Overall L1	27.97-56.34

Vectorization ratios

INT

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	93%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	95%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

10% of peak load performance is reached (9.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 416d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X4, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W3, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X4, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X7, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X27, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z19.D}, P2/Z, [X21, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X21, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X26, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z18.D}, P2/Z, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z21.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, Z19.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X21, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X21, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X20, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z22.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z20.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X23, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, Z1.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z20.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, P1/M, Z18.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X22, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z19.D, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z19.D, Z1.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z22.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X23, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FNMLS Z18.D, P1/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X30, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z20.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z24.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z20.D, Z1.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z22.D, Z23.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X11, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X13, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z24.D, P1/M, Z24.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z22.D, P1/M, Z22.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z21.D, Z1.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z21.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z21, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z21.D, P1/M, Z21.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z18.D, P1/M, Z20.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z20.D, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z19.D, P1/M, Z19.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z22.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X28, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMSB Z18.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z18.D}, P2, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FMUL Z18.D, Z23.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z18.D}, P2, [X24, X27,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W3, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 416d40 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 416ba0 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code