OV - exec - Loop 62

	Loop Id: 62	Module: exec	Source: accelerate_kernel.f90:61-75 [...]	Coverage: 7.03%

0x41846c SBFM	X12, X5, #0, #31

0x418470 SUB	W7, W5, #1

0x418474 ADD	W6, W6, W14

0x418478 ADD	W5, W5, W14

0x41847c SUB	X12, X12, X23

0x418480 SBFM	X7, X7, #0, #31

0x418484 ADD	X13, X12, X16

0x418488 SUB	X7, X7, X23

0x41848c ADD	X8, X12, X17

0x418490 LD1D	{Z18.D}, P2/Z, [X0, X12,LSL #3]    [8]

0x418494 ADD	X10, X12, X18

0x418498 LD1D	{Z6.D}, P2/Z, [X21, X13,LSL #3]    [4]

0x41849c LD1D	{Z7.D}, P2/Z, [X22, X13,LSL #3]    [5]

0x4184a0 ADD	X30, X7, X16

0x4184a4 ADD	X11, X7, X17

0x4184a8 LD1D	{Z19.D}, P2/Z, [X25, X13,LSL #3]    [7]

0x4184ac LD1D	{Z21.D}, P2/Z, [X1, X7,LSL #3]    [10]

0x4184b0 LD1D	{Z4.D}, P2/Z, [X21, X30,LSL #3]    [4]

0x4184b4 LD1D	{Z5.D}, P2/Z, [X22, X30,LSL #3]    [5]

0x4184b8 LD1D	{Z20.D}, P2/Z, [X25, X30,LSL #3]    [7]

0x4184bc LD1D	{Z16.D}, P2/Z, [X25, X11,LSL #3]    [7]

0x4184c0 FMUL	Z6.D, Z6.D, Z7.D

0x4184c4 LD1D	{Z7.D}, P2/Z, [X25, X8,LSL #3]    [7]

0x4184c8 FSUB	Z19.D, Z19.D, Z20.D

0x4184cc LD1D	{Z20.D}, P2/Z, [X1, X12,LSL #3]    [10]

0x4184d0 FMAD	Z4.D, P1/M, Z5.D, Z6.D

0x4184d4 LD1D	{Z5.D}, P2/Z, [X21, X8,LSL #3]    [4]

0x4184d8 LD1D	{Z6.D}, P2/Z, [X22, X8,LSL #3]    [5]

0x4184dc FMUL	Z19.D, Z18.D, Z19.D

0x4184e0 FSUB	Z17.D, Z7.D, Z16.D

0x4184e4 FSUB	Z16.D, Z16.D, Z21.D

0x4184e8 FSUB	Z7.D, Z7.D, Z20.D

0x4184ec LD1D	{Z20.D}, P2/Z, [X28, X11,LSL #3]    [13]

0x4184f0 FMLA	Z4.D, P1/M, Z5.D, Z6.D

0x4184f4 LD1D	{Z5.D}, P2/Z, [X21, X11,LSL #3]    [4]

0x4184f8 LD1D	{Z6.D}, P2/Z, [X22, X11,LSL #3]    [5]

0x4184fc FMUL	Z16.D, Z20.D, Z16.D

0x418500 FMLA	Z4.D, P1/M, Z5.D, Z6.D

0x418504 LD1D	{Z6.D}, P2/Z, [X24, X10,LSL #3]    [6]

0x418508 LD1D	{Z5.D}, P2/Z, [X9, X10,LSL #3]    [2]

0x41850c FMUL	Z4.D, Z4.D, Z3.D

0x418510 FMAD	Z17.D, P1/M, Z6.D, Z19.D

0x418514 LD1D	{Z19.D}, P2/Z, [X28, X8,LSL #3]    [13]

0x418518 FDIVR	Z4.D, P1/M, Z4.D, Z1.D

0x41851c FMAD	Z7.D, P1/M, Z19.D, Z16.D

0x418520 LD1D	{Z16.D}, P2/Z, [X2, X7,LSL #3]    [12]

0x418524 FMLS	Z5.D, P1/M, Z4.D, Z17.D

0x418528 LD1D	{Z17.D}, P2/Z, [X27, X10,LSL #3]    [11]

0x41852c FMSB	Z7.D, P1/M, Z4.D, Z17.D

0x418530 LD1D	{Z17.D}, P2/Z, [X3, X7,LSL #3]    [14]

0x418534 ST1D	{Z7.D}, P2, [X19, X10,LSL #3]    [15]

0x418538 LD1D	{Z7.D}, P2/Z, [X2, X12,LSL #3]    [12]

0x41853c FSUB	Z7.D, Z7.D, Z16.D

0x418540 LD1D	{Z16.D}, P2/Z, [X3, X12,LSL #3]    [14]

0x418544 FSUB	Z21.D, Z16.D, Z17.D

0x418548 FMUL	Z18.D, Z18.D, Z21.D

0x41854c FMAD	Z6.D, P1/M, Z7.D, Z18.D

0x418550 LD1D	{Z7.D}, P2/Z, [X20, X11,LSL #3]    [3]

0x418554 FMLS	Z5.D, P1/M, Z4.D, Z6.D

0x418558 LD1D	{Z6.D}, P2/Z, [X20, X8,LSL #3]    [3]

0x41855c FSUB	Z7.D, Z7.D, Z17.D

0x418560 FMUL	Z7.D, Z20.D, Z7.D

0x418564 FSUB	Z6.D, Z6.D, Z16.D

0x418568 ST1D	{Z5.D}, P2, [X26, X10,LSL #3]    [9]

0x41856c LD1D	{Z5.D}, P2/Z, [X4, X12,LSL #3]    [1]

0x418570 FMAD	Z6.D, P1/M, Z19.D, Z7.D

0x418574 FMSB	Z4.D, P1/M, Z6.D, Z5.D

0x418578 ST1D	{Z4.D}, P2, [X4, X12,LSL #3]    [1]

0x41857c WHILELO	P2.D, W6, W15

0x418580 B.MI	41846c

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 61 - 75

--------------------------------------------------------------------------------

61:     !$OMP SIMD

62:       DO j=x_min,x_max+1

63:         stepbymass_s=halfdt/((density0(j-1,k-1)*volume(j-1,k-1)  &

[...]

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	accelerate_kernel	accelerate_kernel.f90:83	exec
○	accelerate	accelerate.f90:41	exec
○	hydro	hydro.f90:58	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par
Source	accelerate_kernel.f90:61-63,accelerate_kernel.f90:69-75
Source loop unroll info	unrolled by 144
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	144
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	15.00
Front-end cycles	8.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	13.00
P7 cycles	13.00
P8 cycles	12.50
P9 cycles	12.50
P10 cycles	15.00
P11 cycles	15.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.00
Nb uops	70.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	9.87
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	864.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	15.00
Vectorization ratio all	98.25
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	98.46
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	90.28
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par
Source	accelerate_kernel.f90:61-63,accelerate_kernel.f90:69-75
Source loop unroll info	unrolled by 144
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	144
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	15.00
Front-end cycles	8.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	3.25
P6 cycles	13.00
P7 cycles	13.00
P8 cycles	12.50
P9 cycles	12.50
P10 cycles	15.00
P11 cycles	15.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.00
Nb uops	70.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	9.87
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	864.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	15.00
Vectorization ratio all	98.25
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	98.46
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	90.28
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par
Source file and lines	accelerate_kernel.f90:61-75
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:61-63,69-75.

The related source loop is unrolled by 144 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU addition or subtraction instructions are used in vector version.

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 15 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 864 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	70
nb uops	70
loop length	280
used w registers	5
used x registers	27
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	12
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.75 cycles
front end	8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.25	3.25	3.25	3.25	13.00	13.00	1.50	1.50	15.00	15.00	0.00	0.00	0.00
cycles	0.50	0.50	3.25	3.25	3.25	3.25	13.00	13.00	12.50	12.50	15.00	15.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.75
Dispatch	15.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	90%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

60% of peak load performance is reached (57.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41846c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X12, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB W7, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W6, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W5, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X12, X12, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X7, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z18.D}, P2/Z, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X10, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P2/Z, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X7, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z19.D}, P2/Z, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X1, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X25, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X25, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X25, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z4.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X21, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X22, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z19.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z17.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z16.D, Z16.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X28, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X21, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z20.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X24, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z17.D, P1/M, Z6.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X28, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIVR Z4.D, P1/M, Z4.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAD Z7.D, P1/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLS Z5.D, P1/M, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X27, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMSB Z7.D, P1/M, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X3, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z7.D}, P2, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X3, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z21.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z6.D, P1/M, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLS Z5.D, P1/M, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z7.D, Z20.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z6.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z5.D}, P2, [X26, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z6.D, P1/M, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMSB Z4.D, P1/M, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z4.D}, P2, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W6, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 41846c <_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par
Source file and lines	accelerate_kernel.f90:61-75
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU addition or subtraction instructions are used in vector version.

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 15 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 864 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	70
nb uops	70
loop length	280
used w registers	5
used x registers	27
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	12
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.75 cycles
front end	8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.25	3.25	3.25	3.25	13.00	13.00	1.50	1.50	15.00	15.00	0.00	0.00	0.00
cycles	0.50	0.50	3.25	3.25	3.25	3.25	13.00	13.00	12.50	12.50	15.00	15.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.75
Dispatch	15.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	90%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

60% of peak load performance is reached (57.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41846c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X12, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB W7, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W6, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W5, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X12, X12, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X7, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z18.D}, P2/Z, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X10, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P2/Z, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X22, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X30, X7, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z19.D}, P2/Z, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X1, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X25, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X25, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X25, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z4.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X21, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X22, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z19.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z17.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z16.D, Z16.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X28, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X21, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z20.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X24, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z17.D, P1/M, Z6.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X28, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIVR Z4.D, P1/M, Z4.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAD Z7.D, P1/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLS Z5.D, P1/M, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X27, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMSB Z7.D, P1/M, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X3, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ST1D {Z7.D}, P2, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X3, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z21.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z6.D, P1/M, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLS Z5.D, P1/M, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z7.D, Z20.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z6.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z5.D}, P2, [X26, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z6.D, P1/M, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMSB Z4.D, P1/M, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z4.D}, P2, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W6, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 41846c <_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code