OV - exec - Loop 72

	Loop Id: 72	Module: exec	Source: advec_cell_kernel.f90:161-170	Coverage: 3.61%

  (74) 0x41a0c0 CMP	W10, W8

  (74) 0x41a0c4 ADD	W10, W10, #1

  (74) 0x41a0c8 B.EQ	41a200

  (74) 0x41a0cc LDP	X18, X17, [SP, #136]

  (74) 0x41a0d0 ADD	W16, W11, W10

  (74) 0x41a0d4 SUB	X1, XZR, X14

  (74) 0x41a0d8 ORR	P2.B, P0/Z, P0.B, P0.B

  (74) 0x41a0dc ORR	W0, WZR, W9

  (74) 0x41a0e0 ORR	W2, WZR, W9

  (74) 0x41a0e4 SBFM	X16, X16, #0, #31

  (74) 0x41a0e8 SUB	X17, X16, X17

  (74) 0x41a0ec MUL	X16, X17, X7

  (74) 0x41a0f0 MUL	X17, X17, X18

  (74) 0x41a0f4 ADD	X18, X22, X16,LSL #3

  (74) 0x41a0f8 TBZ	W13, #0, 41a180

  (74) 0x41a0fc HINT	#0

    (73) 0x41a100 SBFM	X0, X2, #0, #31

    (73) 0x41a104 ADD	W2, W2, #1

    (73) 0x41a108 SUB	X4, X17, X24

    (73) 0x41a10c SUB	X0, X0, X24

    (73) 0x41a110 ADD	X4, X4, W2,SXTW

    (73) 0x41a114 CMP	W12, W2

    (73) 0x41a118 ADD	X1, X0, X16

    (73) 0x41a11c ADD	X3, X0, X17

    (73) 0x41a120 LDR	D0, [X20, X1,LSL #3]

    (73) 0x41a124 LDR	D1, [X21, X3,LSL #3]

    (73) 0x41a128 LDR	D2, [X28, X3,LSL #3]

    (73) 0x41a12c LDR	D3, [X28, X4,LSL #3]

    (73) 0x41a130 LDR	D4, [X19, X3,LSL #3]

    (73) 0x41a134 FMUL	D0, D0, D1

    (73) 0x41a138 FADD	D2, D0, D2

    (73) 0x41a13c FSUB	D2, D2, S3

    (73) 0x41a140 LDR	D3, [X22, X1,LSL #3]

    (73) 0x41a144 FMADD	D0, D0, D3, D4

    (73) 0x41a148 LDR	D3, [X19, X4,LSL #3]

    (73) 0x41a14c FSUB	D0, D0, S3

    (73) 0x41a150 LDR	D3, [X27, X3,LSL #3]

    (73) 0x41a154 FDIV	D0, D0, D2

    (73) 0x41a158 FADD	D1, D1, D3

    (73) 0x41a15c LDR	D3, [X27, X4,LSL #3]

    (73) 0x41a160 FSUB	D1, D1, S3

    (73) 0x41a164 FDIV	D1, D2, D1

    (73) 0x41a168 STR	D0, [X18, X0,LSL #3]

    (73) 0x41a16c STR	D1, [X20, X1,LSL #3]

    (73) 0x41a170 B.NE	41a100

  (74) 0x41a174 B	41a0c0

0x41a180 SBFM	X2, X0, #0, #31

0x41a184 ADD	W5, W0, #1

0x41a188 SUB	X6, X17, X24

0x41a18c ADD	W1, W1, W14

0x41a190 ADD	W0, W0, W14

0x41a194 SUB	X2, X2, X24

0x41a198 ADD	X5, X6, W5,SXTW

0x41a19c ADD	X3, X2, X16

0x41a1a0 ADD	X4, X2, X17

0x41a1a4 LD1D	{Z0.D}, P2/Z, [X20, X3,LSL #3]

0x41a1a8 LD1D	{Z1.D}, P2/Z, [X21, X4,LSL #3]

0x41a1ac LD1D	{Z2.D}, P2/Z, [X28, X4,LSL #3]

0x41a1b0 LD1D	{Z3.D}, P2/Z, [X28, X5,LSL #3]

0x41a1b4 LD1D	{Z4.D}, P2/Z, [X19, X4,LSL #3]

0x41a1b8 FMUL	Z0.D, Z0.D, Z1.D

0x41a1bc FADD	Z2.D, Z0.D, Z2.D

0x41a1c0 FSUB	Z2.D, Z2.D, Z3.D

0x41a1c4 LD1D	{Z3.D}, P2/Z, [X22, X3,LSL #3]

0x41a1c8 FMAD	Z0.D, P1/M, Z3.D, Z4.D

0x41a1cc LD1D	{Z3.D}, P2/Z, [X19, X5,LSL #3]

0x41a1d0 FSUB	Z0.D, Z0.D, Z3.D

0x41a1d4 LD1D	{Z3.D}, P2/Z, [X27, X4,LSL #3]

0x41a1d8 FDIV	Z0.D, P1/M, Z0.D, Z2.D

0x41a1dc FADD	Z1.D, Z1.D, Z3.D

0x41a1e0 LD1D	{Z3.D}, P2/Z, [X27, X5,LSL #3]

0x41a1e4 FSUB	Z1.D, Z1.D, Z3.D

0x41a1e8 FDIVR	Z1.D, P1/M, Z1.D, Z2.D

0x41a1ec ST1D	{Z0.D}, P2, [X18, X2,LSL #3]

0x41a1f0 ST1D	{Z1.D}, P2, [X20, X3,LSL #3]

0x41a1f4 WHILELO	P2.D, W1, W15

0x41a1f8 B.MI	41a180

0x41a1fc B	41a0c0

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 161 - 170

--------------------------------------------------------------------------------

161:       !$OMP DO PRIVATE(pre_mass_s,post_mass_s,post_ener_s,advec_vol_s)

162:       DO k=y_min,y_max

163:       !$OMP SIMD

164:         DO j=x_min,x_max

165:           pre_mass_s=density1(j,k)*pre_vol(j,k)

166:           post_mass_s=pre_mass_s+mass_flux_x(j,k)-mass_flux_x(j+1,k)

167:           post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j+1,k))/post_mass_s

168:           advec_vol_s=pre_vol(j,k)+vol_flux_x(j,k)-vol_flux_x(j+1,k)

169:           density1(j,k)=post_mass_s/advec_vol_s

170:           energy1(j,k)=post_ener_s

Coverage (%)	Name	Module
►98.42+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.54 - 5.12
Bottlenecks	P6, P8,
Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source	advec_cell_kernel.f90:163-170
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.99 - 28.17
CQA cycles if no scalar integer	13.99 - 28.17
CQA cycles if FP arith vectorized	13.99 - 28.17
CQA cycles if fully vectorized	13.99 - 28.17
Front-end cycles	4.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	5.50
P11 cycles	5.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.86 - 1.42
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.50 - 25.17
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	90.91
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	71.43
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	92.61
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	76.79
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.54 - 5.12
Bottlenecks	P6, P8,
Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source	advec_cell_kernel.f90:163-170
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.99 - 28.17
CQA cycles if no scalar integer	13.99 - 28.17
CQA cycles if FP arith vectorized	13.99 - 28.17
CQA cycles if fully vectorized	13.99 - 28.17
Front-end cycles	4.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	5.50
P11 cycles	5.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.86 - 1.42
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.50 - 25.17
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	90.91
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	71.43
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	92.61
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	76.79
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source file and lines	advec_cell_kernel.f90:161-170
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:161-170.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:163-170.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 92% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

71% of VPU addition or subtraction instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 5.50 cycles (5.12x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	32
nb uops	32
loop length	128
used w registers	5
used x registers	16
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	5
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.50	2.50	2.50	2.50	4.50	4.50	1.00	1.00	5.50	5.50	0.00	0.00	0.00
cycles	1.00	1.00	2.50	2.50	2.50	2.50	4.50	4.50	3.50	3.50	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

13.99-28.17

Cycles summary

Front-end	4.00
Dispatch	5.50
DIV/SQRT	13.99-28.17
Overall L1	13.99-28.17

Vectorization ratios

INT

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	100%
add-sub	71%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	87%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	76%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

10% of peak load performance is reached (10.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X17, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W1, W1, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W0, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X2, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X6, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	2	0.50	N/A
ADD X3, X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z0.D}, P2/Z, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P2/Z, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P2/Z, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X28, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z2.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X22, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z0.D, P1/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X27, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z1.D, P1/M, Z1.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z0.D}, P2, [X18, X2,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z1.D}, P2, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W1, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 41a180 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x12e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41a0c0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source file and lines	advec_cell_kernel.f90:161-170
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 92% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

71% of VPU addition or subtraction instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 5.50 cycles (5.12x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	32
nb uops	32
loop length	128
used w registers	5
used x registers	16
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	5
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.50	2.50	2.50	2.50	4.50	4.50	1.00	1.00	5.50	5.50	0.00	0.00	0.00
cycles	1.00	1.00	2.50	2.50	2.50	2.50	4.50	4.50	3.50	3.50	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

13.99-28.17

Cycles summary

Front-end	4.00
Dispatch	5.50
DIV/SQRT	13.99-28.17
Overall L1	13.99-28.17

Vectorization ratios

INT

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	100%
add-sub	71%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	87%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	76%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

10% of peak load performance is reached (10.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X17, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W1, W1, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W0, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X2, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X6, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	2	0.50	N/A
ADD X3, X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z0.D}, P2/Z, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P2/Z, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P2/Z, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X28, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z2.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X22, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z0.D, P1/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X27, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z1.D, P1/M, Z1.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z0.D}, P2, [X18, X2,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z1.D}, P2, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W1, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 41a180 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x12e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41a0c0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code