| Loop Id: 77 | Module: exec | Source: advec_cell_kernel.f90:96-101 | Coverage: 0.97% |
|---|
| Loop Id: 77 | Module: exec | Source: advec_cell_kernel.f90:96-101 | Coverage: 0.97% |
|---|
(78) 0x419b8c ORR W4, WZR, WZR |
(78) 0x419b90 ADD W4, W4, W10 |
(78) 0x419b94 SBFM X5, X4, #0, #31 |
(78) 0x419b98 SUB X5, X5, X24 |
(78) 0x419b9c LDR D0, [X3, X5,LSL #3] |
(78) 0x419ba0 ADD W3, W4, #1 |
(78) 0x419ba4 ADD X1, X5, X1 |
(78) 0x419ba8 SBFM X3, X3, #0, #31 |
(78) 0x419bac LDR D2, [X27, X1,LSL #3] |
(78) 0x419bb0 SUB X3, X3, X24 |
(78) 0x419bb4 LDR D1, [X2, X3,LSL #3] |
(78) 0x419bb8 STR D0, [X0, X5,LSL #3] |
(78) 0x419bbc FADD D1, D0, D1 |
(78) 0x419bc0 FSUB D1, D1, S2 |
(78) 0x419bc4 STR D1, [X21, X1,LSL #3] |
(78) 0x419bc8 CMP W13, W8 |
(78) 0x419bcc ADD W13, W13, #1 |
(78) 0x419bd0 B.EQ 419d08 |
(78) 0x419bd4 LDR X1, [SP, #144] |
(78) 0x419bd8 ADD W0, W12, W13 |
(78) 0x419bdc SUB W4, W9, #1 |
(78) 0x419be0 SUB X5, XZR, X16 |
(78) 0x419be4 ORR P1.B, P0/Z, P0.B, P0.B |
(78) 0x419be8 SBFM X0, X0, #0, #31 |
(78) 0x419bec SUB X0, X0, X1 |
(78) 0x419bf0 MUL X1, X0, X30 |
(78) 0x419bf4 ADD X3, X26, X1,LSL #3 |
(78) 0x419bf8 LDR X1, [SP, #136] |
(78) 0x419bfc MUL X1, X0, X1 |
(78) 0x419c00 LDR X0, [SP, #120] |
(78) 0x419c04 ADD X2, X27, X1,LSL #3 |
(78) 0x419c08 ADD X0, X0, X1,LSL #3 |
(78) 0x419c0c TBZ W15, #0, 419ca0 |
(78) 0x419c10 CMP W14, W9 |
(78) 0x419c14 B.EQ 419b8c |
(78) 0x419c18 ORR W4, WZR, WZR |
(78) 0x419c1c ORR W5, WZR, W9 |
(79) 0x419c20 SUB W6, W5, #2 |
(79) 0x419c24 SUB W7, W5, #1 |
(79) 0x419c28 SBFM X19, X5, #0, #31 |
(79) 0x419c2c ADD W4, W4, #2 |
(79) 0x419c30 ADD W5, W5, #2 |
(79) 0x419c34 SBFM X6, X6, #0, #31 |
(79) 0x419c38 SBFM X7, X7, #0, #31 |
(79) 0x419c3c SUB X19, X19, X24 |
(79) 0x419c40 LDR D0, [X2, X19,LSL #3] |
(79) 0x419c44 SUB X6, X6, X24 |
(79) 0x419c48 SUB X7, X7, X24 |
(79) 0x419c4c CMP W18, W4 |
(79) 0x419c50 LDR D1, [X3, X6,LSL #3] |
(79) 0x419c54 LDR D2, [X2, X7,LSL #3] |
(79) 0x419c58 ADD X19, X6, X1 |
(79) 0x419c5c FADD D2, D1, D2 |
(79) 0x419c60 STR D1, [X0, X6,LSL #3] |
(79) 0x419c64 LDR D1, [X27, X19,LSL #3] |
(79) 0x419c68 ADD X6, X7, X1 |
(79) 0x419c6c FSUB D1, D2, S1 |
(79) 0x419c70 LDR D2, [X3, X7,LSL #3] |
(79) 0x419c74 STR D1, [X21, X19,LSL #3] |
(79) 0x419c78 LDR D1, [X27, X6,LSL #3] |
(79) 0x419c7c FADD D0, D2, D0 |
(79) 0x419c80 STR D2, [X0, X7,LSL #3] |
(79) 0x419c84 FSUB D0, D0, S1 |
(79) 0x419c88 STR D0, [X21, X6,LSL #3] |
(79) 0x419c8c B.NE 419c20 |
(78) 0x419c90 TBNZ W11, #0, 419b90 |
(78) 0x419c94 B 419bc8 |
0x419ca0 SUB W6, W4, #1 |
0x419ca4 SBFM X7, X4, #0, #31 |
0x419ca8 ADD W5, W5, W16 |
0x419cac ADD W4, W4, W16 |
0x419cb0 SBFM X6, X6, #0, #31 |
0x419cb4 SUB X7, X7, X24 |
0x419cb8 SUB X6, X6, X24 |
0x419cbc LD1D {Z1.D}, P1/Z, [X2, X7,LSL #3] |
0x419cc0 LD1D {Z0.D}, P1/Z, [X3, X6,LSL #3] |
0x419cc4 ADD X7, X6, X1 |
0x419cc8 LD1D {Z2.D}, P1/Z, [X27, X7,LSL #3] |
0x419ccc FADD Z1.D, Z0.D, Z1.D |
0x419cd0 ST1D {Z0.D}, P1, [X0, X6,LSL #3] |
0x419cd4 FSUB Z1.D, Z1.D, Z2.D |
0x419cd8 ST1D {Z1.D}, P1, [X21, X7,LSL #3] |
0x419cdc WHILELO P1.D, W5, W17 |
0x419ce0 B.MI 419ca0 |
0x419ce4 B 419bc8 |
/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 96 - 101 |
-------------------------------------------------------------------------------- |
96: !$OMP DO |
97: DO k=y_min-2,y_max+2 |
98: !$OMP SIMD |
99: DO j=x_min-2,x_max+2 |
100: pre_vol(j,k)=volume(j,k)+vol_flux_x(j+1,k)-vol_flux_x(j,k) |
101: post_vol(j,k)=volume(j,k) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.42+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 | |
| ►1.58+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_fork_call | libomp.so | |
| ○ | __kmpc_fork_call | libomp.so | |
| ○ | advec_cell_kernel | advec_cell_kernel.f90:270 | exec |
| ○ | advec_cell_driver | advec_cell_driver.f90:84 | exec |
| ○ | advection | advection.f90:89 | exec |
| ○ | hydro | hydro.f90:64 | exec |
| ○ | main | clover_leaf.f90:76 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.11 |
| Bottlenecks | P10, P11, |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source | advec_cell_kernel.f90:98-101 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.50 |
| CQA cycles if no scalar integer | 2.50 |
| CQA cycles if FP arith vectorized | 2.50 |
| CQA cycles if fully vectorized | 2.50 |
| Front-end cycles | 2.25 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 2.25 |
| P3 cycles | 2.25 |
| P4 cycles | 2.25 |
| P5 cycles | 2.25 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 2.50 |
| P11 cycles | 2.50 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 18.00 |
| Nb uops | 18.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.20 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 96.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 87.50 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 66.67 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 89.06 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 70.83 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.11 |
| Bottlenecks | P10, P11, |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source | advec_cell_kernel.f90:98-101 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.50 |
| CQA cycles if no scalar integer | 2.50 |
| CQA cycles if FP arith vectorized | 2.50 |
| CQA cycles if fully vectorized | 2.50 |
| Front-end cycles | 2.25 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 2.25 |
| P3 cycles | 2.25 |
| P4 cycles | 2.25 |
| P5 cycles | 2.25 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 2.50 |
| P11 cycles | 2.50 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 18.00 |
| Nb uops | 18.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.20 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 96.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 87.50 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 66.67 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 89.06 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 70.83 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source file and lines | advec_cell_kernel.f90:96-101 |
| Module | exec |
| nb instructions | 18 |
| nb uops | 18 |
| loop length | 72 |
| used w registers | 5 |
| used x registers | 10 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 3 |
| nb stack references | 0 |
| micro-operation queue | 2.25 cycles |
| front end | 2.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 1.00 | 1.00 | 1.00 | 1.00 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 1.00 | 1.00 | 1.00 | 1.00 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 2.25 |
| Dispatch | 2.50 |
| Overall L1 | 2.50 |
| all | 83% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 87% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 85% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 89% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 70% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB W6, W4, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SBFM X7, X4, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W5, W5, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W4, W4, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X6, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X7, X7, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X6, X6, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z1.D}, P1/Z, [X2, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z0.D}, P1/Z, [X3, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| ADD X7, X6, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z2.D}, P1/Z, [X27, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z1.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z0.D}, P1, [X0, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FSUB Z1.D, Z1.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z1.D}, P1, [X21, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P1.D, W5, W17 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 419ca0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xe00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 419bc8 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xd28> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source file and lines | advec_cell_kernel.f90:96-101 |
| Module | exec |
| nb instructions | 18 |
| nb uops | 18 |
| loop length | 72 |
| used w registers | 5 |
| used x registers | 10 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 3 |
| nb stack references | 0 |
| micro-operation queue | 2.25 cycles |
| front end | 2.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 1.00 | 1.00 | 1.00 | 1.00 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 2.25 | 2.25 | 2.25 | 2.25 | 1.00 | 1.00 | 1.00 | 1.00 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 2.25 |
| Dispatch | 2.50 |
| Overall L1 | 2.50 |
| all | 83% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 87% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 85% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 89% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 70% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SUB W6, W4, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SBFM X7, X4, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W5, W5, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W4, W4, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X6, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X7, X7, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X6, X6, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z1.D}, P1/Z, [X2, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z0.D}, P1/Z, [X3, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| ADD X7, X6, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z2.D}, P1/Z, [X27, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z1.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z0.D}, P1, [X0, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FSUB Z1.D, Z1.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z1.D}, P1, [X21, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P1.D, W5, W17 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 419ca0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xe00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 419bc8 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xd28> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
