OV - exec - Loop 80

	Loop Id: 80	Module: exec	Source: advec_cell_kernel.f90:252-261	Coverage: 3.99%

  (82) 0x41996c CMP	W11, W8

  (82) 0x419970 ADD	W11, W11, #1

  (82) 0x419974 B.EQ	419ab8

  (82) 0x419978 LDP	X1, X0, [SP, #136]

  (82) 0x41997c ADD	W18, W12, W11

  (82) 0x419980 CMP	W10, W9

  (82) 0x419984 SUB	X3, XZR, X14

  (82) 0x419988 ORR	P2.B, P0/Z, P0.B, P0.B

  (82) 0x41998c ORR	W2, WZR, W9

  (82) 0x419990 ORR	W4, WZR, W9

  (82) 0x419994 SBFM	X16, X18, #0, #31

  (82) 0x419998 ADD	W18, W18, #1

  (82) 0x41999c SBFM	X18, X18, #0, #31

  (82) 0x4199a0 SUB	X17, X16, X0

  (82) 0x4199a4 SUB	X0, X18, X0

  (82) 0x4199a8 MUL	X16, X17, X27

  (82) 0x4199ac MUL	X18, X0, X27

  (82) 0x4199b0 MUL	X0, X0, X1

  (82) 0x4199b4 MUL	X17, X17, X1

  (82) 0x4199b8 ADD	X0, X26, X0,LSL #3

  (82) 0x4199bc ADD	X1, X22, X16,LSL #3

  (82) 0x4199c0 B.GE	419a40

    (81) 0x4199c4 SBFM	X2, X4, #0, #31

    (81) 0x4199c8 ADD	W4, W4, #1

    (81) 0x4199cc SUB	X2, X2, X24

    (81) 0x4199d0 CMP	W13, W4

    (81) 0x4199d4 ADD	X3, X2, X16

    (81) 0x4199d8 ADD	X5, X2, X17

    (81) 0x4199dc ADD	X6, X2, X18

    (81) 0x4199e0 LDR	D0, [X20, X3,LSL #3]

    (81) 0x4199e4 LDR	D1, [X21, X5,LSL #3]

    (81) 0x4199e8 LDR	D2, [X25, X3,LSL #3]

    (81) 0x4199ec LDR	D3, [X25, X6,LSL #3]

    (81) 0x4199f0 LDR	D4, [X22, X3,LSL #3]

    (81) 0x4199f4 FMUL	D0, D0, D1

    (81) 0x4199f8 FADD	D2, D0, D2

    (81) 0x4199fc FSUB	D2, D2, S3

    (81) 0x419a00 LDR	D3, [X26, X5,LSL #3]

    (81) 0x419a04 FMADD	D0, D0, D4, D3

    (81) 0x419a08 LDR	D3, [X0, X2,LSL #3]

    (81) 0x419a0c FSUB	D0, D0, S3

    (81) 0x419a10 LDR	D3, [X19, X3,LSL #3]

    (81) 0x419a14 FDIV	D0, D0, D2

    (81) 0x419a18 FADD	D1, D1, D3

    (81) 0x419a1c LDR	D3, [X19, X6,LSL #3]

    (81) 0x419a20 FSUB	D1, D1, S3

    (81) 0x419a24 FDIV	D1, D2, D1

    (81) 0x419a28 STR	D0, [X1, X2,LSL #3]

    (81) 0x419a2c STR	D1, [X20, X3,LSL #3]

    (81) 0x419a30 B.NE	4199c4

  (82) 0x419a34 B	41996c

0x419a40 SBFM	X4, X2, #0, #31

0x419a44 ADD	W3, W3, W14

0x419a48 ADD	W2, W2, W14

0x419a4c SUB	X4, X4, X24

0x419a50 ADD	X5, X4, X16

0x419a54 ADD	X6, X4, X17

0x419a58 ADD	X7, X4, X18

0x419a5c LD1D	{Z0.D}, P2/Z, [X20, X5,LSL #3]

0x419a60 LD1D	{Z1.D}, P2/Z, [X21, X6,LSL #3]

0x419a64 LD1D	{Z2.D}, P2/Z, [X25, X5,LSL #3]

0x419a68 LD1D	{Z3.D}, P2/Z, [X25, X7,LSL #3]

0x419a6c LD1D	{Z4.D}, P2/Z, [X26, X6,LSL #3]

0x419a70 FMUL	Z0.D, Z0.D, Z1.D

0x419a74 FADD	Z2.D, Z0.D, Z2.D

0x419a78 FSUB	Z2.D, Z2.D, Z3.D

0x419a7c LD1D	{Z3.D}, P2/Z, [X22, X5,LSL #3]

0x419a80 FMAD	Z0.D, P1/M, Z3.D, Z4.D

0x419a84 LD1D	{Z3.D}, P2/Z, [X0, X4,LSL #3]

0x419a88 FSUB	Z0.D, Z0.D, Z3.D

0x419a8c LD1D	{Z3.D}, P2/Z, [X19, X5,LSL #3]

0x419a90 FDIV	Z0.D, P1/M, Z0.D, Z2.D

0x419a94 FADD	Z1.D, Z1.D, Z3.D

0x419a98 LD1D	{Z3.D}, P2/Z, [X19, X7,LSL #3]

0x419a9c FSUB	Z1.D, Z1.D, Z3.D

0x419aa0 FDIVR	Z1.D, P1/M, Z1.D, Z2.D

0x419aa4 ST1D	{Z0.D}, P2, [X1, X4,LSL #3]

0x419aa8 ST1D	{Z1.D}, P2, [X20, X5,LSL #3]

0x419aac WHILELO	P2.D, W3, W15

0x419ab0 B.MI	419a40

0x419ab4 B	41996c

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 252 - 261

--------------------------------------------------------------------------------

252:       !$OMP DO PRIVATE(pre_mass_s,post_mass_s,post_ener_s,advec_vol_s)

253:       DO k=y_min,y_max

254:       !$OMP SIMD

255:         DO j=x_min,x_max

256:           pre_mass_s=density1(j,k)*pre_vol(j,k)

257:           post_mass_s=pre_mass_s+mass_flux_y(j,k)-mass_flux_y(j,k+1)

258:           post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j,k+1))/post_mass_s

259:           advec_vol_s=pre_vol(j,k)+vol_flux_y(j,k)-vol_flux_y(j,k+1)

260:           density1(j,k)=post_mass_s/advec_vol_s

261:           energy1(j,k)=post_ener_s

Coverage (%)	Name	Module
►98.44+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.54 - 5.12
Bottlenecks	P6, P8,
Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source	advec_cell_kernel.f90:254-261
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.99 - 28.17
CQA cycles if no scalar integer	13.99 - 28.17
CQA cycles if FP arith vectorized	13.99 - 28.17
CQA cycles if fully vectorized	13.99 - 28.17
Front-end cycles	3.75
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	5.50
P11 cycles	5.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.86 - 1.42
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.50 - 25.17
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	95.24
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	83.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	95.83
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	85.42
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.54 - 5.12
Bottlenecks	P6, P8,
Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source	advec_cell_kernel.f90:254-261
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.99 - 28.17
CQA cycles if no scalar integer	13.99 - 28.17
CQA cycles if FP arith vectorized	13.99 - 28.17
CQA cycles if fully vectorized	13.99 - 28.17
Front-end cycles	3.75
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	5.50
P11 cycles	5.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.86 - 1.42
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.50 - 25.17
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	95.24
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	83.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	95.83
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	85.42
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source file and lines	advec_cell_kernel.f90:252-261
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:252-261.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:254-261.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

83% of VPU addition or subtraction instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 5.50 cycles (5.12x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	30
nb uops	30
loop length	120
used w registers	4
used x registers	17
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	5
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.00	2.00	2.00	2.00	4.50	4.50	1.00	1.00	5.50	5.50	0.00	0.00	0.00
cycles	1.00	1.00	2.00	2.00	2.00	2.00	4.50	4.50	3.50	3.50	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

13.99-28.17

Cycles summary

Front-end	3.75
Dispatch	5.50
DIV/SQRT	13.99-28.17
Overall L1	13.99-28.17

Vectorization ratios

INT

all	91%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	83%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	92%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	85%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

10% of peak load performance is reached (10.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 419a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X4, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W3, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X4, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z0.D}, P2/Z, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P2/Z, [X21, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P2/Z, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z2.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z0.D, P1/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z1.D, P1/M, Z1.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z0.D}, P2, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z1.D}, P2, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W3, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 419a40 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41996c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xacc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source file and lines	advec_cell_kernel.f90:252-261
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

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Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

83% of VPU addition or subtraction instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 5.50 cycles (5.12x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	30
nb uops	30
loop length	120
used w registers	4
used x registers	17
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	5
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.00	2.00	2.00	2.00	4.50	4.50	1.00	1.00	5.50	5.50	0.00	0.00	0.00
cycles	1.00	1.00	2.00	2.00	2.00	2.00	4.50	4.50	3.50	3.50	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

13.99-28.17

Cycles summary

Front-end	3.75
Dispatch	5.50
DIV/SQRT	13.99-28.17
Overall L1	13.99-28.17

Vectorization ratios

INT

all	91%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	83%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	92%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	85%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

10% of peak load performance is reached (10.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 419a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X4, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W3, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X4, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z0.D}, P2/Z, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P2/Z, [X21, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P2/Z, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z2.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMAD Z0.D, P1/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z1.D, P1/M, Z1.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z0.D}, P2, [X1, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z1.D}, P2, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W3, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 419a40 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41996c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xacc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code