| Loop Id: 84 | Module: exec | Source: advec_cell_kernel.f90:188-193 | Coverage: 1.05% |
|---|
| Loop Id: 84 | Module: exec | Source: advec_cell_kernel.f90:188-193 | Coverage: 1.05% |
|---|
(85) 0x4193e0 ORR W5, WZR, WZR |
(85) 0x4193e4 ADD W5, W5, W10 |
(85) 0x4193e8 SBFM X5, X5, #0, #31 |
(85) 0x4193ec SUB X5, X5, X24 |
(85) 0x4193f0 ADD X3, X5, X3 |
(85) 0x4193f4 LDR D1, [X1, X5,LSL #3] |
(85) 0x4193f8 LDR D0, [X26, X3,LSL #3] |
(85) 0x4193fc FADD D0, D0, D1 |
(85) 0x419400 LDR D1, [X19, X3,LSL #3] |
(85) 0x419404 FSUB D0, D0, S1 |
(85) 0x419408 STR D0, [X0, X5,LSL #3] |
(85) 0x41940c LDR D0, [X2, X5,LSL #3] |
(85) 0x419410 STR D0, [X4, X5,LSL #3] |
(85) 0x419414 CMP W13, W8 |
(85) 0x419418 ADD W13, W13, #1 |
(85) 0x41941c B.EQ 419560 |
(85) 0x419420 LDP X2, X4, [SP, #136] |
(85) 0x419424 ADD W0, W12, W13 |
(85) 0x419428 LDR X5, [SP, #120] |
(85) 0x41942c CMP W15, W10 |
(85) 0x419430 SUB X6, XZR, X16 |
(85) 0x419434 ORR P1.B, P0/Z, P0.B, P0.B |
(85) 0x419438 ADD W1, W0, #1 |
(85) 0x41943c SBFM X0, X0, #0, #31 |
(85) 0x419440 SBFM X1, X1, #0, #31 |
(85) 0x419444 SUB X0, X0, X4 |
(85) 0x419448 SUB X1, X1, X4 |
(85) 0x41944c MUL X3, X0, X30 |
(85) 0x419450 MUL X1, X1, X30 |
(85) 0x419454 MUL X4, X0, X2 |
(85) 0x419458 ADD X1, X19, X1,LSL #3 |
(85) 0x41945c ADD X0, X21, X4,LSL #3 |
(85) 0x419460 ADD X2, X26, X3,LSL #3 |
(85) 0x419464 ADD X4, X5, X4,LSL #3 |
(85) 0x419468 SUB W5, W9, #2 |
(85) 0x41946c B.GE 419500 |
(85) 0x419470 CMP W14, W9 |
(85) 0x419474 B.EQ 4193e0 |
(85) 0x419478 SUB W6, W9, #1 |
(85) 0x41947c ORR W5, WZR, WZR |
(86) 0x419480 SUB W7, W6, #1 |
(86) 0x419484 SBFM X23, X6, #0, #31 |
(86) 0x419488 ADD W5, W5, #2 |
(86) 0x41948c ADD W6, W6, #2 |
(86) 0x419490 SBFM X7, X7, #0, #31 |
(86) 0x419494 SUB X23, X23, X24 |
(86) 0x419498 CMP W18, W5 |
(86) 0x41949c SUB X7, X7, X24 |
(86) 0x4194a0 ADD X27, X23, X3 |
(86) 0x4194a4 LDR D0, [X1, X23,LSL #3] |
(86) 0x4194a8 LDR D2, [X2, X7,LSL #3] |
(86) 0x4194ac ADD X28, X7, X3 |
(86) 0x4194b0 LDR D1, [X1, X7,LSL #3] |
(86) 0x4194b4 STR D2, [X4, X7,LSL #3] |
(86) 0x4194b8 LDR D2, [X26, X27,LSL #3] |
(86) 0x4194bc FADD D0, D2, D0 |
(86) 0x4194c0 LDR D2, [X26, X28,LSL #3] |
(86) 0x4194c4 FADD D1, D2, D1 |
(86) 0x4194c8 LDR D2, [X19, X27,LSL #3] |
(86) 0x4194cc FSUB D0, D0, S2 |
(86) 0x4194d0 LDR D2, [X19, X28,LSL #3] |
(86) 0x4194d4 FSUB D1, D1, S2 |
(86) 0x4194d8 STR D1, [X0, X7,LSL #3] |
(86) 0x4194dc STR D0, [X0, X23,LSL #3] |
(86) 0x4194e0 LDR D0, [X2, X23,LSL #3] |
(86) 0x4194e4 STR D0, [X4, X23,LSL #3] |
(86) 0x4194e8 B.NE 419480 |
(85) 0x4194ec TBNZ W11, #0, 4193e4 |
(85) 0x4194f0 B 419414 |
0x419500 SBFM X7, X5, #0, #31 |
0x419504 ADD W6, W6, W16 |
0x419508 ADD W5, W5, W16 |
0x41950c SUB X7, X7, X24 |
0x419510 ADD X23, X7, X3 |
0x419514 LD1D {Z1.D}, P1/Z, [X1, X7,LSL #3] |
0x419518 LD1D {Z0.D}, P1/Z, [X26, X23,LSL #3] |
0x41951c FADD Z0.D, Z0.D, Z1.D |
0x419520 LD1D {Z1.D}, P1/Z, [X19, X23,LSL #3] |
0x419524 FSUB Z0.D, Z0.D, Z1.D |
0x419528 ST1D {Z0.D}, P1, [X0, X7,LSL #3] |
0x41952c LD1D {Z0.D}, P1/Z, [X2, X7,LSL #3] |
0x419530 ST1D {Z0.D}, P1, [X4, X7,LSL #3] |
0x419534 WHILELO P1.D, W6, W17 |
0x419538 B.MI 419500 |
0x41953c B 419414 |
/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 188 - 193 |
-------------------------------------------------------------------------------- |
188: !$OMP DO |
189: DO k=y_min-2,y_max+2 |
190: !$OMP SIMD |
191: DO j=x_min-2,x_max+2 |
192: pre_vol(j,k)=volume(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k) |
193: post_vol(j,k)=volume(j,k) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.43+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 | |
| ►1.57+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_fork_call | libomp.so | |
| ○ | __kmpc_fork_call | libomp.so | |
| ○ | advec_cell_kernel | advec_cell_kernel.f90:270 | exec |
| ○ | advec_cell_driver | advec_cell_driver.f90:84 | exec |
| ○ | advection | advection.f90:89 | exec |
| ○ | hydro | hydro.f90:64 | exec |
| ○ | main | clover_leaf.f90:76 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.50 |
| Bottlenecks | P10, P11, |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source | advec_cell_kernel.f90:190-193 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 3.00 |
| CQA cycles if no scalar integer | 3.00 |
| CQA cycles if FP arith vectorized | 3.00 |
| CQA cycles if fully vectorized | 3.00 |
| Front-end cycles | 2.00 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 1.50 |
| P3 cycles | 1.50 |
| P4 cycles | 1.50 |
| P5 cycles | 1.50 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 3.00 |
| P11 cycles | 3.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 16.00 |
| Nb uops | 16.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.67 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 88.89 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 66.67 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 90.28 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 70.83 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.50 |
| Bottlenecks | P10, P11, |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source | advec_cell_kernel.f90:190-193 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 3.00 |
| CQA cycles if no scalar integer | 3.00 |
| CQA cycles if FP arith vectorized | 3.00 |
| CQA cycles if fully vectorized | 3.00 |
| Front-end cycles | 2.00 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 1.50 |
| P3 cycles | 1.50 |
| P4 cycles | 1.50 |
| P5 cycles | 1.50 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 1.00 |
| P10 cycles | 3.00 |
| P11 cycles | 3.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 16.00 |
| Nb uops | 16.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.67 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 88.89 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 66.67 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 90.28 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 70.83 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source file and lines | advec_cell_kernel.f90:188-193 |
| Module | exec |
| nb instructions | 16 |
| nb uops | 16 |
| loop length | 64 |
| used w registers | 4 |
| used x registers | 11 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 2 |
| nb stack references | 0 |
| micro-operation queue | 2.00 cycles |
| front end | 2.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 1.50 | 1.50 | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 1.50 | 1.50 | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 2.00 |
| Dispatch | 3.00 |
| Overall L1 | 3.00 |
| all | 85% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 88% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 87% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 90% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 70% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SBFM X7, X5, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W6, W6, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W5, W5, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SUB X7, X7, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X23, X7, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z1.D}, P1/Z, [X1, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z0.D}, P1/Z, [X26, X23,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z1.D}, P1/Z, [X19, X23,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FSUB Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z0.D}, P1, [X0, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z0.D}, P1/Z, [X2, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| ST1D {Z0.D}, P1, [X4, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P1.D, W6, W17 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 419500 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x660> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 419414 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x574> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source file and lines | advec_cell_kernel.f90:188-193 |
| Module | exec |
| nb instructions | 16 |
| nb uops | 16 |
| loop length | 64 |
| used w registers | 4 |
| used x registers | 11 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 2 |
| nb stack references | 0 |
| micro-operation queue | 2.00 cycles |
| front end | 2.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 1.50 | 1.50 | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 1.50 | 1.50 | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 2.00 |
| Dispatch | 3.00 |
| Overall L1 | 3.00 |
| all | 85% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 88% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 87% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 90% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 70% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SBFM X7, X5, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W6, W6, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W5, W5, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SUB X7, X7, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X23, X7, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z1.D}, P1/Z, [X1, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z0.D}, P1/Z, [X26, X23,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FADD Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z1.D}, P1/Z, [X19, X23,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FSUB Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z0.D}, P1, [X0, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z0.D}, P1/Z, [X2, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| ST1D {Z0.D}, P1, [X4, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P1.D, W6, W17 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 419500 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x660> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 419414 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x574> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
