OV - exec - Function __viscosity_kernel_module_MOD_viscosity_kernel._omp

	Function: __viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0	Module: exec	Source: viscosity_kernel.f90:50-89	Coverage (incl. loops): 2.43% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 50 - 89

--------------------------------------------------------------------------------

50:     !$OMP PARALLEL

51:

52:     !$OMP DO PRIVATE(ugrad,vgrad,div,strain2,pgradx,pgrady,pgradx2,pgrady2,limiter,pgrad,xgrad,ygrad,grad,grad2,dirx,diry)

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

0x448c60 STP	X29, X30, [SP, #832]!

0x448c64 ADD	X29, SP, #0

0x448c68 STP	X19, X20, [SP, #16]

0x448c6c ORR	X19, XZR, X0

0x448c70 STP	X21, X22, [SP, #32]

0x448c74 LDR	X0, [X0, #16]

0x448c78 LDR	W21, [X0]

0x448c7c BL	4103b0

0x448c80 ORR	W20, WZR, W0

0x448c84 BL	410330

0x448c88 LDR	X1, [X19, #24]

0x448c8c LDR	W2, [X1]

0x448c90 ADD	W3, W2, #1

0x448c94 SUB	W4, W3, W21

0x448c98 SDIV	W5, W4, W20

0x448c9c MSUB	W6, W5, W20, W4

0x448ca0 CMP	W0, W6

0x448ca4 B.LT	449048

0x448ca8 MADD	W7, W5, W0, W6

0x448cac ADD	W8, W5, W7

0x448cb0 CMP	W7, W8

0x448cb4 B.GE	449038

0x448cb8 STP	X23, X24, [SP, #48]

0x448cbc ADD	W10, W21, W8

0x448cc0 ADD	W9, W21, W7

0x448cc4 SBFM	X9, X9, #0, #31

0x448cc8 ADRP	X11,

0x448ccc FMOV	D31, #0.5000000

0x448cd0 MOVZ	W2, #0

0x448cd4 STP	X25, X26, [SP, #64]

0x448cd8 STP	X27, X28, [SP, #80]

0x448cdc ADD	X28, X9, #1

0x448ce0 LDP	X12, X13, [X19]

0x448ce4 STR	W10, [SP, #148]

0x448ce8 LDR	X26, [X19, #152]

0x448cec LDR	W24, [X13]

0x448cf0 LDR	W21, [X12]

0x448cf4 MUL	X0, X26, X9

0x448cf8 UBFM	X15, X26, #61, #60

0x448cfc LDR	X16, [X19, #32]

0x448d00 MADD	X23, X9, X26, X26

0x448d04 ADD	W6, W24, #1

0x448d08 STR	X15, [SP, #168]

0x448d0c LDR	X17, [X19, #48]

0x448d10 SBFM	X22, X21, #0, #31

0x448d14 SUB	W1, W24, W21

0x448d18 STR	W6, [SP, #188]

0x448d1c LDR	X25, [X19, #72]

0x448d20 ADD	X5, X1, X0

0x448d24 CMP	W21, W24

0x448d28 CSINC	W3, W21, W24, #12

0x448d2c STR	W3, [SP, #136]

0x448d30 LDR	X14, [X19, #96]

0x448d34 ADD	X17, X17, X22,LSL #3

0x448d38 LDR	X18, [X19, #120]

0x448d3c LDR	X27, [X19, #168]

0x448d40 STP	W21, W24, [SP, #140]

0x448d44 LDR	X7, [X19, #160]

0x448d48 STR	X17, [SP, #120]

0x448d4c MADD	X20, X9, X18, X18

0x448d50 LDR	X4, [X19, #40]

0x448d54 MADD	X30, X9, X27, X27

0x448d58 LDR	X13, [X19, #64]

0x448d5c ADD	X8, X22, X7

0x448d60 ADD	X21, X23, X7

0x448d64 ADD	X10, X5, X8

0x448d68 LDR	X5, [X19, #88]

0x448d6c ADD	X0, X7, X0

0x448d70 ADD	X14, X4, X14,LSL #3

0x448d74 LDR	X24, [X19, #56]

0x448d78 ADD	X4, X13, X22,LSL #3

0x448d7c ADD	X15, X14, #8

0x448d80 LDR	X23, [X19, #80]

0x448d84 ADD	X3, X22, X5

0x448d88 LDR	X7, [X19, #104]

0x448d8c ADD	X16, X16, X3,LSL #3

0x448d90 ADD	X1, X24, X22,LSL #3

0x448d94 STR	X4, [SP, #112]

0x448d98 LDR	D30, [X11, #2088]

0x448d9c ADD	X11, X25, #8

0x448da0 ADD	X25, X25, X22,LSL #3

0x448da4 ADD	X12, X11, X10,LSL #3

0x448da8 STR	X16, [SP, #128]

0x448dac ADD	X6, X1, #8

0x448db0 LDR	X8, [X19, #112]

0x448db4 ADD	X22, X23, X22,LSL #3

0x448db8 STR	X7, [SP, #160]

0x448dbc LDP	X10, X11, [X19, #128]

0x448dc0 MADD	X24, X7, X9, X8

0x448dc4 STR	X19, [SP, #176]

0x448dc8 LDR	X23, [X19, #144]

0x448dcc MADD	X16, X18, X9, X10

0x448dd0 ADD	X20, X20, X10

0x448dd4 STR	X10, [SP, #104]

0x448dd8 LDR	X13, [X19, #176]

0x448ddc ORR	X19, XZR, X6

0x448de0 STR	X11, [SP, #152]

0x448de4 LDR	W3, [SP, #184]

0x448de8 MADD	X23, X11, X9, X23

0x448dec MADD	X17, X27, X9, X13

0x448df0 ADD	X30, X30, X13

(811) 0x448df4 LDP	W1, W6, [SP, #140]

(811) 0x448df8 CMP	W1, W6

(811) 0x448dfc B.GT	449054

(811) 0x448e00 LDR	X11, [SP, #104]

(811) 0x448e04 SUB	W3, W9, #1

(811) 0x448e08 ADD	X2, X25, X0,LSL #3

(811) 0x448e0c SBFM	X8, X3, #0, #31

(811) 0x448e10 LDP	X10, X7, [SP, #120]

(811) 0x448e14 ADD	X6, X25, X21,LSL #3

(811) 0x448e18 ADD	X5, X22, X30,LSL #3

(811) 0x448e1c SUB	X13, X20, X16

(811) 0x448e20 ADD	X4, X22, X17,LSL #3

(811) 0x448e24 ADD	X1, X19, X16,LSL #3

(811) 0x448e28 MADD	X3, X8, X18, X11

(811) 0x448e2c LDR	X8, [SP, #112]

(811) 0x448e30 ADD	X10, X10, X24,LSL #3

(811) 0x448e34 SUB	X11, X3, X16

(811) 0x448e38 ADD	X8, X8, X23,LSL #3

(811) 0x448e3c HINT	#0

  (813) 0x448e40 SUB	X3, X1, #8

  (813) 0x448e44 LDR	D18, [X14, X9,LSL #3]

  (813) 0x448e48 LDR	D6, [X3, X13,LSL #3]

  (813) 0x448e4c LDR	D17, [X15, X9,LSL #3]

  (813) 0x448e50 LDR	D20, [X3, X11,LSL #3]

  (813) 0x448e54 LDUR	D7, [X1, #496]

  (813) 0x448e58 FADD	D0, D18, D17

  (813) 0x448e5c LDR	D1, [X1]

  (813) 0x448e60 FSUB	D26, D6, S20

  (813) 0x448e64 LDP	D23, D22, [X4]

  (813) 0x448e68 LDP	D25, D5, [X5]

  (813) 0x448e6c LDP	D27, D29, [X2]

  (813) 0x448e70 FSUB	D19, D1, S7

  (813) 0x448e74 FDIV	D17, D26, D0

  (813) 0x448e78 LDP	D0, D28, [X6]

  (813) 0x448e7c FADD	D16, D23, D22

  (813) 0x448e80 FADD	D2, D5, D22

  (813) 0x448e84 FADD	D4, D25, D5

  (813) 0x448e88 FADD	D1, D28, D0

  (813) 0x448e8c FADD	D7, D27, D0

  (813) 0x448e90 FSUB	D3, D2, S23

  (813) 0x448e94 FADD	D23, D29, D28

  (813) 0x448e98 FSUB	D21, D4, S16

  (813) 0x448e9c LDP	D0, D4, [X7]

  (813) 0x448ea0 FSUB	D27, D1, S27

  (813) 0x448ea4 FSUB	D24, D3, S25

  (813) 0x448ea8 FSUB	D16, D23, S7

  (813) 0x448eac FADD	D3, D0, D4

  (813) 0x448eb0 FMUL	D26, D21, D31

  (813) 0x448eb4 FMUL	D2, D17, D17

  (813) 0x448eb8 FSUB	D29, D27, S29

  (813) 0x448ebc FMUL	D6, D24, D31

  (813) 0x448ec0 FMUL	D25, D16, D31

  (813) 0x448ec4 FDIV	D19, D19, D3

  (813) 0x448ec8 FMUL	D22, D29, D31

  (813) 0x448ecc FDIV	D20, D6, D0

  (813) 0x448ed0 FDIV	D5, D22, D18

  (813) 0x448ed4 FMUL	D7, D19, D19

  (813) 0x448ed8 FDIV	D28, D26, D18

  (813) 0x448edc FADD	D27, D7, D2

  (813) 0x448ee0 FMAXNM	D23, D27, D30

  (813) 0x448ee4 FDIV	D6, D25, D0

  (813) 0x448ee8 FADD	D24, D5, D20

  (813) 0x448eec FMUL	D29, D28, D2

  (813) 0x448ef0 FMUL	D1, D24, D19

  (813) 0x448ef4 FMADD	D22, D7, D6, D29

  (813) 0x448ef8 FMADD	D25, D17, D1, D22

  (813) 0x448efc FDIV	D5, D25, D23

  (813) 0x448f00 FCMPE	D5, #0

  (813) 0x448f04 B.GT	449018

  (813) 0x448f08 FMUL	D16, D0, D16

  (813) 0x448f0c FMADD	D21, D18, D21, D16

  (813) 0x448f10 FCMPE	D21, #0

  (813) 0x448f14 B.GE	449018

  (813) 0x448f18 FCMPE	D19, #0

  (813) 0x448f1c FABS	D2, D19

  (813) 0x448f20 FMAXNM	D1, D2, D30

  (813) 0x448f24 B.MI	448ff8

  (813) 0x448f28 FMOV	D3, #1.0000000

  (813) 0x448f2c FABS	D17, D17

  (813) 0x448f30 FMAXNM	D20, D17, D30

  (813) 0x448f34 FMUL	D24, D3, D20

  (813) 0x448f38 LDR	D25, [X10]

  (813) 0x448f3c FMUL	D19, D24, D24

  (813) 0x448f40 FADD	D16, D25, D25

  (813) 0x448f44 FMADD	D26, D1, D1, D19

  (813) 0x448f48 FSQRT	D6, D26

  (813) 0x448f4c FMUL	D0, D0, D6

  (813) 0x448f50 FMUL	D18, D18, D6

  (813) 0x448f54 FDIV	D28, D0, D1

  (813) 0x448f58 FDIV	D7, D18, D24

  (813) 0x448f5c FABS	D27, D28

  (813) 0x448f60 FABS	D23, D7

  (813) 0x448f64 FMINNM	D29, D27, D23

  (813) 0x448f68 FMUL	D22, D29, D29

  (813) 0x448f6c FMUL	D21, D16, D22

  (813) 0x448f70 FMUL	D2, D21, D5

  (813) 0x448f74 FMUL	D5, D2, D5

  (813) 0x448f78 STR	D5, [X8]

  (813) 0x448f7c HINT	#0

  (813) 0x448f80 ADD	X2, X2, #8

  (813) 0x448f84 ADD	X6, X6, #8

  (813) 0x448f88 ADD	X5, X5, #8

  (813) 0x448f8c ADD	X4, X4, #8

  (813) 0x448f90 ADD	X7, X7, #8

  (813) 0x448f94 ADD	X1, X1, #8

  (813) 0x448f98 ADD	X10, X10, #8

  (813) 0x448f9c ADD	X8, X8, #8

  (813) 0x448fa0 CMP	X12, X2

  (813) 0x448fa4 B.NE	448e40

(811) 0x448fa8 LDR	X5, [SP, #152]

(811) 0x448fac ADD	X0, X0, X26

(811) 0x448fb0 ADD	X21, X21, X26

(811) 0x448fb4 ADD	X30, X30, X27

(811) 0x448fb8 ADD	X17, X17, X27

(811) 0x448fbc LDR	X13, [SP, #160]

(811) 0x448fc0 ADD	X16, X16, X18

(811) 0x448fc4 ADD	X20, X20, X18

(811) 0x448fc8 ORR	X9, XZR, X28

(811) 0x448fcc MOVZ	W2, #1

(811) 0x448fd0 LDR	X6, [SP, #168]

(811) 0x448fd4 ADD	X23, X23, X5

(811) 0x448fd8 LDR	W4, [SP, #148]

(811) 0x448fdc ADD	X24, X24, X13

(811) 0x448fe0 ADD	X12, X12, X6

(811) 0x448fe4 CMP	W4, W28

(811) 0x448fe8 B.LE	449020

(811) 0x448fec LDR	W3, [SP, #136]

(811) 0x448ff0 ADD	X28, X28, #1

(811) 0x448ff4 B	448df4

  (813) 0x448ff8 FCMPE	D1, #0

  (813) 0x448ffc FNEG	D4, D1

  (813) 0x449000 B.GT	44900c

  (813) 0x449004 FMOV	D1, D4

  (813) 0x449008 B	448f28

  (813) 0x44900c FMOV	D1, D4

  (813) 0x449010 FMOV	D3, #-1.0000000

  (813) 0x449014 B	448f2c

  (813) 0x449018 STR	XZR, [X8]

  (813) 0x44901c B	448f80

0x449020 LDR	X14, [SP, #176]

0x449024 LDR	W15, [SP, #136]

0x449028 STR	W15, [X14, #184]

0x44902c LDP	X23, X24, [SP, #48]

0x449030 LDP	X25, X26, [SP, #64]

0x449034 LDP	X27, X28, [SP, #80]

0x449038 LDP	X19, X20, [SP, #16]

0x44903c LDP	X21, X22, [SP, #32]

0x449040 LDP	X29, X30, [SP], #192

0x449044 RET

0x449048 ADD	W5, W5, #1

0x44904c MOVZ	W6, #0

0x449050 B	448ca8

(811) 0x449054 LDR	W9, [SP, #148]

(811) 0x449058 SUB	W5, W9, W28

(811) 0x44905c ANDS	W8, W5, #0x3

(811) 0x449060 B.EQ	449200

(811) 0x449064 LDR	W7, [SP, #136]

(811) 0x449068 LDR	W4, [SP, #188]

(811) 0x44906c CMP	W4, W7

(811) 0x449070 B.EQ	448fa8

(811) 0x449074 LDR	X1, [SP, #168]

(811) 0x449078 ADD	X0, X0, X26

(811) 0x44907c ADD	X21, X21, X26

(811) 0x449080 LDP	X11, X13, [SP, #152]

(811) 0x449084 ADD	X30, X30, X27

(811) 0x449088 ADD	X17, X17, X27

(811) 0x44908c ADD	X16, X16, X18

(811) 0x449090 ADD	X20, X20, X18

(811) 0x449094 LDR	W10, [SP, #148]

(811) 0x449098 ADD	X12, X12, X1

(811) 0x44909c ADD	X24, X24, X13

(811) 0x4490a0 ADD	X23, X23, X11

(811) 0x4490a4 CMP	W10, W28

(811) 0x4490a8 B.LE	4491b0

(811) 0x4490ac ADD	X28, X28, #1

(811) 0x4490b0 CMP	W8, #1

(811) 0x4490b4 B.EQ	4491e4

(811) 0x4490b8 CMP	W8, #2

(811) 0x4490bc B.EQ	4490e8

(811) 0x4490c0 ADD	X12, X12, X1

(811) 0x4490c4 ADD	X24, X24, X13

(811) 0x4490c8 ADD	X23, X23, X11

(811) 0x4490cc ADD	X0, X0, X26

(811) 0x4490d0 ADD	X21, X21, X26

(811) 0x4490d4 ADD	X30, X30, X27

(811) 0x4490d8 ADD	X17, X17, X27

(811) 0x4490dc ADD	X16, X16, X18

(811) 0x4490e0 ADD	X20, X20, X18

(811) 0x4490e4 ADD	X28, X28, #1

(811) 0x4490e8 LDR	W9, [SP, #136]

(811) 0x4490ec LDR	W8, [SP, #188]

(811) 0x4490f0 CMP	W8, W9

(811) 0x4490f4 B.EQ	448fa8

(811) 0x4490f8 LDR	X5, [SP, #168]

(811) 0x4490fc ADD	X0, X0, X26

(811) 0x449100 ADD	X21, X21, X26

(811) 0x449104 LDP	X7, X4, [SP, #152]

(811) 0x449108 ADD	X30, X30, X27

(811) 0x44910c ADD	X17, X17, X27

(811) 0x449110 ADD	X16, X16, X18

(811) 0x449114 ADD	X20, X20, X18

(811) 0x449118 ADD	X28, X28, #1

(811) 0x44911c LDR	W6, [SP, #148]

(811) 0x449120 ADD	X12, X12, X5

(811) 0x449124 ADD	X24, X24, X4

(811) 0x449128 ADD	X23, X23, X7

(811) 0x44912c B	44916c

  (812) 0x449130 ADD	X11, X21, X26,LSL #1

  (812) 0x449134 ADD	X12, X13, X5

  (812) 0x449138 ADD	X0, X10, X26

  (812) 0x44913c ADD	X13, X30, X27,LSL #1

  (812) 0x449140 ADD	X24, X24, X4

  (812) 0x449144 ADD	X23, X23, X7

  (812) 0x449148 ADD	X1, X17, X27,LSL #1

  (812) 0x44914c ADD	X21, X11, X26

  (812) 0x449150 ADD	X28, X28, #4

  (812) 0x449154 ADD	X16, X16, X18,LSL #1

  (812) 0x449158 ADD	X30, X13, X27

  (812) 0x44915c ADD	X10, X20, X18,LSL #1

  (812) 0x449160 ADD	X17, X1, X27

  (812) 0x449164 ADD	X16, X16, X18

  (812) 0x449168 ADD	X20, X10, X18

  (812) 0x44916c CMP	W8, W9

  (812) 0x449170 B.EQ	448fa8

  (812) 0x449174 ADD	X10, X12, X5

  (812) 0x449178 ADD	X11, X24, X4

  (812) 0x44917c ADD	X1, X23, X7

  (812) 0x449180 ADD	X0, X0, X26

  (812) 0x449184 ADD	X13, X10, X5,LSL #1

  (812) 0x449188 ADD	X24, X11, X4,LSL #1

  (812) 0x44918c ADD	X21, X21, X26

  (812) 0x449190 ADD	X30, X30, X27

  (812) 0x449194 ADD	X23, X1, X7,LSL #1

  (812) 0x449198 ADD	X17, X17, X27

  (812) 0x44919c ADD	X16, X16, X18

  (812) 0x4491a0 ADD	X10, X0, X26,LSL #1

  (812) 0x4491a4 ADD	X20, X20, X18

  (812) 0x4491a8 CMP	W6, W28

  (812) 0x4491ac B.GT	449130

0x4491b0 STR	W3, [SP, #184]

0x4491b4 LDR	X14, [SP, #176]

0x4491b8 CBNZ	W2, 4491d8

0x4491bc LDP	X23, X24, [SP, #48]

0x4491c0 LDP	X25, X26, [SP, #64]

0x4491c4 LDP	X27, X28, [SP, #80]

0x4491c8 LDP	X19, X20, [SP, #16]

0x4491cc LDP	X21, X22, [SP, #32]

0x4491d0 LDP	X29, X30, [SP], #192

0x4491d4 RET

0x4491d8 LDR	W2, [SP, #184]

0x4491dc STR	W2, [SP, #136]

0x4491e0 B	449024

(811) 0x4491e4 LDR	X5, [SP, #168]

(811) 0x4491e8 ORR	X7, XZR, X11

(811) 0x4491ec ORR	X4, XZR, X13

(811) 0x4491f0 LDR	W9, [SP, #136]

(811) 0x4491f4 LDR	W6, [SP, #148]

(811) 0x4491f8 LDR	W8, [SP, #188]

(811) 0x4491fc B	44916c

(811) 0x449200 LDR	X5, [SP, #168]

(811) 0x449204 LDP	X7, X4, [SP, #152]

(811) 0x449208 LDR	W9, [SP, #136]

(811) 0x44920c LDR	W6, [SP, #148]

(811) 0x449210 LDR	W8, [SP, #188]

(811) 0x449214 B	44916c

0x449218 HINT	#0

0x44921c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.42+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	GOMP_parallel		libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:50-89.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.50 to 12.50 cycles (1.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 21.50 to 12.50 cycles (1.72x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 21 bytes. The binary function is storing 18 bytes.

General properties

nb instructions	129
nb uops	127
loop length	516
used w registers	16
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	37

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.88 cycles
front end	15.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	14.00	14.00	14.00	14.00	0.25	0.25	0.25	0.25	21.50	21.17	21.33	10.50	10.50
cycles	4.50	4.50	14.00	14.00	14.00	14.00	0.25	0.25	0.25	0.25	21.50	21.17	21.33	10.50	10.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	15.88
Dispatch	21.50
DIV/SQRT	5.00-12.50
Overall L1	21.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	30%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	22%
other	31%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	30%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	22%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.50 cycles. At this rate:

1% of peak load performance is reached (0.98 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 448c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #832]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 449048 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W7, W5, W0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 449038 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W10, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X9, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADRP X11, <464cc8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D31, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X28, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR W10, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X26, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W21, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL X0, X26, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X15, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X23, X9, X26, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W6, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X15, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X22, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SUB W1, W24, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W6, [SP, #188]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X25, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W21, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W3, W21, W24, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X14, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X17, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X18, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X27, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP W21, W24, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X20, X9, X18, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X4, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X30, X9, X27, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X13, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X22, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X4, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X13, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X23, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X3, X22, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X7, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X16, X16, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X24, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D30, [X11, #2088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X11, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X25, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X6, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X22, X23, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X7, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MADD X24, X7, X9, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X16, X18, X9, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X20, X20, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MADD X23, X11, X9, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD X17, X27, X9, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X30, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W15, [X14, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #192	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 448ca8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X14, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ W2, 4491d8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #192	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 449024 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 21 bytes. The binary function is storing 18 bytes.

General properties

nb instructions	129
nb uops	127
loop length	516
used w registers	16
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	37

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.88 cycles
front end	15.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	14.00	14.00	14.00	14.00	0.25	0.25	0.25	0.25	21.50	21.17	21.33	10.50	10.50
cycles	4.50	4.50	14.00	14.00	14.00	14.00	0.25	0.25	0.25	0.25	21.50	21.17	21.33	10.50	10.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	15.88
Dispatch	21.50
DIV/SQRT	5.00-12.50
Overall L1	21.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	30%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	22%
other	31%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	30%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	22%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.50 cycles. At this rate:

1% of peak load performance is reached (0.98 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 448c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #832]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 449048 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W7, W5, W0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 449038 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W10, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X9, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADRP X11, <464cc8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D31, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X28, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR W10, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X26, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W21, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL X0, X26, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X15, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X23, X9, X26, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W6, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X15, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X22, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SUB W1, W24, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W6, [SP, #188]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X25, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W21, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W3, W21, W24, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X14, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X17, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X18, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X27, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP W21, W24, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X20, X9, X18, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X4, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X30, X9, X27, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X13, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X22, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X4, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X13, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X23, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X3, X22, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X7, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X16, X16, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X24, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D30, [X11, #2088]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X11, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X25, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X11, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X6, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X22, X23, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X7, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MADD X24, X7, X9, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X16, X18, X9, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X20, X20, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MADD X23, X11, X9, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD X17, X27, X9, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X30, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W15, [X14, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #192	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 448ca8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X14, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ W2, 4491d8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #192	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 449024 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0–	2.43	3.22
▼Loop 811 - viscosity_kernel.f90:50-89 - exec–	0.00	0.02
○Loop 813 - viscosity_kernel.f90:56-89 - exec	2.43	3.20
○Loop 812 - viscosity_kernel.f90:52-52 - exec	0.00	0.00

Report Configuration

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Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

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ASM code

Code clean check

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Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code