OV - exec - Function __field_summary_kernel_module_MOD_field_summary_kernel._omp

	Function: __field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0	Module: exec	Source: field_summary_kernel.f90:54-71	Coverage (incl. loops): 0.34% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 54 - 71

--------------------------------------------------------------------------------

54:     !$OMP PARALLEL

55:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

56:     DO k=y_min,y_max

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

0x4247a0 STP	X29, X30, [SP, #896]!

0x4247a4 ADD	X29, SP, #0

0x4247a8 STP	X19, X20, [SP, #16]

0x4247ac STP	X21, X22, [SP, #32]

0x4247b0 ORR	X21, XZR, X0

0x4247b4 STP	D11, D12, [SP, #80]

0x4247b8 STP	D13, D14, [SP, #96]

0x4247bc LDR	X0, [X0, #16]

0x4247c0 LDR	W20, [X0]

0x4247c4 STR	D15, [SP, #112]

0x4247c8 BL	4103b0

0x4247cc ORR	W19, WZR, W0

0x4247d0 BL	410330

0x4247d4 LDR	X2, [X21, #24]

0x4247d8 ORR	W1, WZR, W0

0x4247dc LDR	W3, [X2]

0x4247e0 ADD	W4, W3, #1

0x4247e4 SUB	W5, W4, W20

0x4247e8 SDIV	W6, W5, W19

0x4247ec MSUB	W7, W6, W19, W5

0x4247f0 CMP	W0, W7

0x4247f4 B.LT	424ae0

0x4247f8 MADD	W8, W6, W1, W7

0x4247fc ADD	W9, W6, W8

0x424800 CMP	W8, W9

0x424804 B.GE	424a54

0x424808 STP	X23, X24, [SP, #48]

0x42480c ADD	W16, W20, W8

0x424810 ADD	W20, W20, W9

0x424814 SBFM	X2, X16, #0, #31

0x424818 MOVI	D15, #0

0x42481c MOVZ	W1, #0

0x424820 CNTD	X15, ALL

0x424824 FDUP	Z30.D, #80

0x424828 DUP	Z31.D, #0

0x42482c STP	X25, X26, [SP, #64]

0x424830 FMOV	D14, D15

0x424834 FMOV	D13, D15

0x424838 LDP	X10, X11, [X21]

0x42483c FMOV	D12, D15

0x424840 FMOV	D11, D15

0x424844 LDP	X25, X26, [X21, #120]

0x424848 LDP	X4, X3, [X21, #192]

0x42484c LDP	X23, X19, [X21, #152]

0x424850 MADD	X7, X2, X3, X3

0x424854 UBFM	X18, X3, #61, #60

0x424858 LDP	X24, X13, [X21, #136]

0x42485c LDP	X30, X12, [X21, #168]

0x424860 LDR	W17, [X10]

0x424864 LDR	X5, [X21, #208]

0x424868 LDR	X14, [X21, #40]

0x42486c SBFM	X0, X17, #0, #31

0x424870 ADD	X6, X0, X26

0x424874 ADD	X10, X0, X19

0x424878 ADD	X9, X0, X5

0x42487c LDR	X5, [X21, #184]

0x424880 ADD	X4, X0, X4

0x424884 MADD	X26, X2, X25, X6

0x424888 ADD	X8, X0, X13

0x42488c ADD	X12, X0, X12

0x424890 MADD	X3, X2, X3, X9

0x424894 ADD	X9, X7, X9

0x424898 UBFM	X25, X25, #61, #60

0x42489c MADD	X13, X24, X2, X8

0x4248a0 UBFM	X24, X24, #61, #60

0x4248a4 MADD	X8, X23, X2, X10

0x4248a8 LDR	X10, [X21, #32]

0x4248ac UBFM	X23, X23, #61, #60

0x4248b0 MADD	X7, X5, X2, X4

0x4248b4 UBFM	X19, X5, #61, #60

0x4248b8 ADD	X14, X14, X26,LSL #3

0x4248bc LDR	W26, [X11]

0x4248c0 MADD	X11, X2, X5, X5

0x4248c4 MADD	X2, X2, X30, X12

0x4248c8 LDR	X12, [X21, #64]

0x4248cc UBFM	X30, X30, #61, #60

0x4248d0 ADD	X6, X11, X4

0x4248d4 LDR	X4, [X21, #72]

0x4248d8 ADD	X0, X12, X7,LSL #3

0x4248dc LDP	X5, X7, [X21, #48]

0x4248e0 ADD	X11, X12, X6,LSL #3

0x4248e4 ADD	X3, X4, X3,LSL #3

0x4248e8 ADD	X4, X4, X9,LSL #3

0x4248ec ADD	X12, X10, X2,LSL #3

0x4248f0 ADD	W10, W26, #1

0x4248f4 ADD	X13, X5, X13,LSL #3

0x4248f8 SUB	W2, W10, W17

0x4248fc WHILELO	P15.D, XZR, X2

0x424900 ADD	X5, X7, X8,LSL #3

(168) 0x424904 ADD	W16, W16, #1

(168) 0x424908 CMP	W17, W26

(168) 0x42490c B.GT	424a14

    (166) 0x424910 MOVZ	X1, #0

    (166) 0x424914 ADD	X22, X0, #8

    (166) 0x424918 ORR	P7.B, P15/Z, P15.B, P15.B

    (166) 0x42491c ADD	X9, X3, #8

    (166) 0x424920 ADD	X8, X11, #8

    (166) 0x424924 ADD	X6, X4, #8

      (165) 0x424928 LD1D	{Z4.D}, P7/Z, [X12, X1,LSL #3]

      (165) 0x42492c LD1D	{Z0.D}, P7/Z, [X0, X1,LSL #3]

      (165) 0x424930 LD1D	{Z24.D}, P7/Z, [X3, X1,LSL #3]

      (165) 0x424934 LD1D	{Z23.D}, P7/Z, [X22, X1,LSL #3]

      (165) 0x424938 LD1D	{Z22.D}, P7/Z, [X9, X1,LSL #3]

      (165) 0x42493c LD1D	{Z20.D}, P7/Z, [X11, X1,LSL #3]

      (165) 0x424940 LD1D	{Z19.D}, P7/Z, [X4, X1,LSL #3]

      (165) 0x424944 LD1D	{Z17.D}, P7/Z, [X8, X1,LSL #3]

      (165) 0x424948 LD1D	{Z16.D}, P7/Z, [X6, X1,LSL #3]

      (165) 0x42494c LD1D	{Z6.D}, P7/Z, [X14, X1,LSL #3]

      (165) 0x424950 LD1D	{Z25.D}, P7/Z, [X13, X1,LSL #3]

      (165) 0x424954 MOVPRFX	Z5, Z4

      (165) 0x424958 FMUL	Z5.D, P7/M, Z5.D, Z6.D

      (165) 0x42495c LD1D	{Z27.D}, P7/Z, [X5, X1,LSL #3]

      (165) 0x424960 MOVPRFX	Z29, Z5

      (165) 0x424964 FMUL	Z29.D, P7/M, Z29.D, Z25.D

      (165) 0x424968 MOVPRFX	Z28, Z0

      (165) 0x42496c FMUL	Z28.D, P7/M, Z28.D, Z0.D

      (165) 0x424970 MOVPRFX	Z21, Z23

      (165) 0x424974 FMUL	Z21.D, P7/M, Z21.D, Z23.D

      (165) 0x424978 FMLA	Z28.D, P7/M, Z24.D, Z24.D

      (165) 0x42497c FMLA	Z21.D, P7/M, Z22.D, Z22.D

      (165) 0x424980 FMUL	Z28.D, P7/M, Z28.D, Z30.D

      (165) 0x424984 MOVPRFX	Z18, Z20

      (165) 0x424988 FMUL	Z18.D, P7/M, Z18.D, Z20.D

      (165) 0x42498c FADD	Z28.D, P7/M, Z28.D, Z31.D

      (165) 0x424990 FMLA	Z18.D, P7/M, Z19.D, Z19.D

      (165) 0x424994 FMLA	Z28.D, P7/M, Z21.D, Z30.D

      (165) 0x424998 MOVPRFX	Z7, Z17

      (165) 0x42499c FMUL	Z7.D, P7/M, Z7.D, Z17.D

      (165) 0x4249a0 FMLA	Z28.D, P7/M, Z18.D, Z30.D

      (165) 0x4249a4 FMLA	Z7.D, P7/M, Z16.D, Z16.D

      (165) 0x4249a8 FADDA	D11, P7, D11, Z4.D

      (165) 0x4249ac FMLA	Z28.D, P7/M, Z7.D, Z30.D

      (165) 0x4249b0 FADDA	D12, P7, D12, Z5.D

      (165) 0x4249b4 FMUL	Z4.D, P7/M, Z4.D, Z27.D

      (165) 0x4249b8 FMUL	Z5.D, P7/M, Z5.D, #0.0000000

      (165) 0x4249bc ADD	X1, X1, X15

      (165) 0x4249c0 FMUL	Z5.D, P7/M, Z5.D, Z28.D

      (165) 0x4249c4 FADDA	D14, P7, D14, Z29.D

      (165) 0x4249c8 FADDA	D13, P7, D13, Z4.D

      (165) 0x4249cc FADDA	D15, P7, D15, Z5.D

      (165) 0x4249d0 WHILELO	P7.D, X1, X2

      (165) 0x4249d4 B.NE	424928

    (166) 0x4249d8 ORR	W22, WZR, W10

    (166) 0x4249dc ADD	X0, X0, X19

    (166) 0x4249e0 ADD	X3, X3, X18

    (166) 0x4249e4 ADD	X11, X11, X19

    (166) 0x4249e8 ADD	X4, X4, X18

    (166) 0x4249ec ADD	X12, X12, X30

    (166) 0x4249f0 ADD	X14, X14, X25

    (166) 0x4249f4 ADD	X13, X13, X24

    (166) 0x4249f8 ADD	X5, X5, X23

    (166) 0x4249fc CMP	W20, W16

    (166) 0x424a00 B.LE	424ad0

    (166) 0x424a04 MOVZ	W1, #1

    (166) 0x424a08 ADD	W16, W16, #1

    (166) 0x424a0c CMP	W17, W26

    (166) 0x424a10 B.LE	424910

  (167) 0x424a14 CMP	W17, W10

  (167) 0x424a18 B.EQ	424aec

(168) 0x424a1c ADD	X0, X0, X19

(168) 0x424a20 ADD	X3, X3, X18

(168) 0x424a24 ADD	X11, X11, X19

(168) 0x424a28 ADD	X4, X4, X18

(168) 0x424a2c ADD	X12, X12, X30

(168) 0x424a30 ADD	X14, X14, X25

(168) 0x424a34 ADD	X13, X13, X24

(168) 0x424a38 ADD	X5, X5, X23

(168) 0x424a3c CMP	W20, W16

(168) 0x424a40 B.GT	424904

0x424a44 CBNZ	W1, 424ad0

0x424a48 LDP	X23, X24, [SP, #48]

0x424a4c LDP	X25, X26, [SP, #64]

0x424a50 B	424a68

0x424a54 MOVI	D15, #0

0x424a58 FMOV	D14, D15

0x424a5c FMOV	D13, D15

0x424a60 FMOV	D12, D15

0x424a64 FMOV	D11, D15

0x424a68 BL	410150

0x424a6c LDP	X20, X15, [X21, #80]

0x424a70 LDP	X18, X19, [X21, #96]

0x424a74 LDR	D3, [X20]

0x424a78 LDR	X21, [X21, #112]

0x424a7c FADD	D1, D3, D11

0x424a80 STR	D1, [X20]

0x424a84 LDR	D2, [X15]

0x424a88 FADD	D26, D2, D12

0x424a8c STR	D26, [X15]

0x424a90 LDR	D12, [X21]

0x424a94 FADD	D13, D12, D13

0x424a98 STR	D13, [X21]

0x424a9c LDR	D11, [X18]

0x424aa0 FADD	D14, D11, D14

0x424aa4 STR	D14, [X18]

0x424aa8 LDR	D30, [X19]

0x424aac FADD	D31, D30, D15

0x424ab0 LDR	D15, [SP, #112]

0x424ab4 STR	D31, [X19]

0x424ab8 LDP	D11, D12, [SP, #80]

0x424abc LDP	X19, X20, [SP, #16]

0x424ac0 LDP	X21, X22, [SP, #32]

0x424ac4 LDP	D13, D14, [SP, #96]

0x424ac8 LDP	X29, X30, [SP], #128

0x424acc B	4101b0

0x424ad0 STR	W22, [X21, #216]

0x424ad4 LDP	X23, X24, [SP, #48]

0x424ad8 LDP	X25, X26, [SP, #64]

0x424adc B	424a68

0x424ae0 ADD	W6, W6, #1

0x424ae4 MOVZ	W7, #0

0x424ae8 B	4247f8

  (167) 0x424aec ORR	W22, WZR, W17

  (167) 0x424af0 B	4249dc

0x424af4 HINT	#0

0x424af8 HINT	#0

0x424afc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.42+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.26+	GOMP_parallel		libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:77	exec
○	field_summary	field_summary.f90:81	exec
○	hydro	hydro.f90:74	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 12.50 cycles (1.36x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 17.00 to 4.86 cycles (3.49x speedup).

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 12 bytes. The binary function is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	134
nb uops	131
loop length	536
used w registers	18
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	11
used q registers	0
used v registers	0
used z registers	2
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	14.25	14.25	14.25	14.25	6.25	6.25	6.25	6.25	17.00	17.00	17.00	3.00	3.00
cycles	5.00	5.00	14.25	14.25	14.25	14.25	6.25	6.25	6.25	6.25	17.00	17.00	17.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	16.38
Dispatch	17.00
DIV/SQRT	5.00-12.50
Overall L1	17.00

Vectorization ratios

INT

all	5%
load	7%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	7%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	35%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	21%
other	17%

all	23%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

INT+FP

all	27%
load	35%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.00 cycles. At this rate:

0% of peak load performance is reached (0.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.18 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4247a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP D11, D12, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D15, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W3, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W5, W4, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W6, W5, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W7, W6, W19, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 424ae0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W8, W6, W1, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W6, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424a54 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W16, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W20, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X2, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D15, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FDUP Z30.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
DUP Z31.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FMOV D14, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D13, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X10, X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FMOV D12, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D11, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X25, X26, [X21, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X4, X3, [X21, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X19, [X21, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MADD X7, X2, X3, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X18, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X24, X13, [X21, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X30, X12, [X21, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR W17, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X5, [X21, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X0, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X21, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X26, X2, X25, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X8, X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X3, X2, X3, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, X7, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X25, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X13, X24, X2, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X8, X23, X2, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X10, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X7, X5, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X19, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W26, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MADD X11, X2, X5, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X2, X2, X30, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X12, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X30, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X11, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X21, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X12, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X5, X7, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X11, X12, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X4, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X10, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W10, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X5, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W2, W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X5, X7, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ W1, 424ad0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 424a68 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D15, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D14, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D13, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D12, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D11, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X15, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X18, X19, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X21, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADD D1, D3, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D1, [X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D26, D2, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D26, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D12, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D13, D12, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D13, [X21]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D11, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D14, D11, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D14, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D30, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D31, D30, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D31, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP D11, D12, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W22, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 424a68 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 4247f8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 12 bytes. The binary function is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	134
nb uops	131
loop length	536
used w registers	18
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	11
used q registers	0
used v registers	0
used z registers	2
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	14.25	14.25	14.25	14.25	6.25	6.25	6.25	6.25	17.00	17.00	17.00	3.00	3.00
cycles	5.00	5.00	14.25	14.25	14.25	14.25	6.25	6.25	6.25	6.25	17.00	17.00	17.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	16.38
Dispatch	17.00
DIV/SQRT	5.00-12.50
Overall L1	17.00

Vectorization ratios

INT

all	5%
load	7%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	7%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	35%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	21%
other	17%

all	23%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

INT+FP

all	27%
load	35%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.00 cycles. At this rate:

0% of peak load performance is reached (0.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.18 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4247a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP D11, D12, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D15, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W3, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W5, W4, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W6, W5, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W7, W6, W19, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 424ae0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W8, W6, W1, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W6, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424a54 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W16, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W20, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X2, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D15, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FDUP Z30.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
DUP Z31.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FMOV D14, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D13, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X10, X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FMOV D12, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D11, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X25, X26, [X21, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X4, X3, [X21, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X19, [X21, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MADD X7, X2, X3, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X18, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X24, X13, [X21, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X30, X12, [X21, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR W17, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X5, [X21, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X0, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X21, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X26, X2, X25, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X8, X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X3, X2, X3, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X9, X7, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X25, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X13, X24, X2, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X8, X23, X2, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X10, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X7, X5, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X19, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W26, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MADD X11, X2, X5, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X2, X2, X30, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X12, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X30, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X11, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X21, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X12, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X5, X7, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X11, X12, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X4, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X10, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W10, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X5, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W2, W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X5, X7, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ W1, 424ad0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 424a68 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D15, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D14, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D13, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D12, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D11, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X15, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X18, X19, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X21, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADD D1, D3, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D1, [X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D26, D2, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D26, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D12, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D13, D12, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D13, [X21]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D11, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D14, D11, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D14, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D30, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D31, D30, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D31, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP D11, D12, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W22, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 424a68 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 4247f8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0–	0.34	0.45
▼Loop 168 - field_summary_kernel.f90:55-71 - exec–	0.00	0.00
▼Loop 167 - field_summary_kernel.f90:55-71 - exec–	0.00	0.00
▼Loop 166 - field_summary_kernel.f90:62-71 - exec–	0.00	0.00
○Loop 165 - field_summary_kernel.f90:62-71 - exec	0.34	0.45

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

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Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code