OV - exec - Function __flux_calc_kernel_module_MOD_flux_calc_kernel._omp

	Function: __flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0	Module: exec	Source: flux_calc_kernel.f90:49-60	Coverage (incl. loops): 4.69% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 49 - 60

--------------------------------------------------------------------------------

49:     !$OMP PARALLEL

50:

51:     ! Note that the loops calculate one extra flux than required, but this

52:     ! allows loop fusion that improves performance

53:     !$OMP DO

54:     DO k=y_min,y_max+1

55:     !$OMP SIMD

56:       DO j=x_min,x_max+1

57:         vol_flux_x(j,k)=0.25_8*dt*xarea(j,k)                  &

58:           *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1))

59:         vol_flux_y(j,k)=0.25_8*dt*yarea(j,k)                  &

60:           *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k))

0x424f80 STP	X29, X30, [SP, #896]!

0x424f84 ADD	X29, SP, #0

0x424f88 STP	X19, X20, [SP, #16]

0x424f8c ORR	X19, XZR, X0

0x424f90 STP	X21, X22, [SP, #32]

0x424f94 LDR	X0, [X0, #16]

0x424f98 LDR	W21, [X0]

0x424f9c BL	4103b0

0x424fa0 ORR	W20, WZR, W0

0x424fa4 BL	410330

0x424fa8 LDR	X1, [X19, #24]

0x424fac ORR	W17, WZR, W0

0x424fb0 LDR	W2, [X1]

0x424fb4 ADD	W3, W2, #2

0x424fb8 SUB	W4, W3, W21

0x424fbc SDIV	W5, W4, W20

0x424fc0 MSUB	W6, W5, W20, W4

0x424fc4 CMP	W0, W6

0x424fc8 B.LT	425238

0x424fcc MADD	W7, W5, W17, W6

0x424fd0 ADD	W8, W5, W7

0x424fd4 CMP	W7, W8

0x424fd8 B.GE	4251e0

0x424fdc STP	X23, X24, [SP, #48]

0x424fe0 ADD	W17, W21, W7

0x424fe4 ADD	W30, W21, W8

0x424fe8 SBFM	X15, X17, #0, #31

0x424fec CNTD	X16, ALL

0x424ff0 PTRUE	P6.B, ALL

0x424ff4 FDUP	Z31.D, #80

0x424ff8 STP	X25, X26, [SP, #64]

0x424ffc STP	X27, X28, [SP, #80]

0x425000 LDP	X18, X1, [X19]

0x425004 LDP	X6, X4, [X19, #168]

0x425008 LDP	X9, X5, [X19, #152]

0x42500c UBFM	X26, X6, #61, #60

0x425010 SUB	X13, XZR, X6,LSL #3

0x425014 LDP	X23, X11, [X19, #136]

0x425018 MADD	X12, X15, X26, X26

0x42501c UBFM	X27, X9, #61, #60

0x425020 SUB	X28, XZR, X9,LSL #3

0x425024 LDP	X21, X8, [X19, #200]

0x425028 MADD	X14, X15, X27, X27

0x42502c LDP	X22, X10, [X19, #184]

0x425030 MADD	X28, X28, X15, X14

0x425034 LDP	X25, X3, [X19, #104]

0x425038 LDP	X24, X2, [X19, #120]

0x42503c LDR	W18, [X18]

0x425040 LDR	X20, [X19, #216]

0x425044 LDR	W1, [X1]

0x425048 SBFM	X0, X18, #0, #31

0x42504c ADD	X7, X0, X5

0x425050 ADD	X11, X0, X11

0x425054 ADD	X5, X0, X4

0x425058 MADD	X4, X13, X15, X12

0x42505c ADD	X10, X0, X10

0x425060 MADD	X13, X15, X23, X11

0x425064 LDR	X11, [X19, #224]

0x425068 ADD	X3, X0, X3

0x42506c MADD	X14, X15, X6, X5

0x425070 ADD	X6, X0, X8

0x425074 ADD	X2, X0, X2

0x425078 MADD	X9, X15, X9, X7

0x42507c LDR	X12, [X19, #40]

0x425080 UBFM	X23, X23, #61, #60

0x425084 MADD	X8, X15, X21, X6

0x425088 LDP	X5, X6, [X19, #48]

0x42508c UBFM	X21, X21, #61, #60

0x425090 MADD	X7, X15, X22, X10

0x425094 UBFM	X22, X22, #61, #60

0x425098 ADD	X0, X0, X11

0x42509c MADD	X3, X15, X25, X3

0x4250a0 UBFM	X25, X25, #61, #60

0x4250a4 MADD	X2, X15, X24, X2

0x4250a8 UBFM	X24, X24, #61, #60

0x4250ac MADD	X15, X15, X20, X0

0x4250b0 ADD	W0, W1, #2

0x4250b4 UBFM	X20, X20, #61, #60

0x4250b8 ADD	X10, X5, X7,LSL #3

0x4250bc LDP	X7, X1, [X19, #72]

0x4250c0 CMP	W18, W0

0x4250c4 ADD	X11, X12, X13,LSL #3

0x4250c8 CSEL	W13, W18, W0, #10

0x4250cc ADD	X9, X6, X9,LSL #3

0x4250d0 STR	X4, [SP, #104]

0x4250d4 SUB	W4, W0, W18

0x4250d8 WHILELO	P15.D, XZR, X4

0x4250dc STP	W13, WZR, [SP, #116]

0x4250e0 ADD	X7, X7, X14,LSL #3

0x4250e4 LDR	X14, [X19, #64]

0x4250e8 ADD	X6, X1, X15,LSL #3

0x4250ec LDP	X12, X15, [X19, #88]

0x4250f0 LDR	X5, [X19, #32]

0x4250f4 ADD	X8, X14, X8,LSL #3

0x4250f8 ADD	X3, X12, X3,LSL #3

0x4250fc ADD	X2, X15, X2,LSL #3

(171) 0x425100 ADD	W17, W17, #1

(171) 0x425104 CMP	W18, W0

(171) 0x425108 B.GE	42519c

(171) 0x42510c LDR	X14, [SP, #104]

(171) 0x425110 MOVZ	X1, #0

(171) 0x425114 ADD	X15, X9, X28

(171) 0x425118 ADD	X13, X8, #8

(171) 0x42511c ADD	X12, X6, #8

(171) 0x425120 ORR	P7.B, P15/Z, P15.B, P15.B

(171) 0x425124 ADD	X14, X7, X14

  (172) 0x425128 LD1D	{Z4.D}, P7/Z, [X9, X1,LSL #3]

  (172) 0x42512c LD1D	{Z7.D}, P7/Z, [X15, X1,LSL #3]

  (172) 0x425130 LD1D	{Z6.D}, P7/Z, [X7, X1,LSL #3]

  (172) 0x425134 LD1D	{Z5.D}, P7/Z, [X14, X1,LSL #3]

  (172) 0x425138 LD1D	{Z16.D}, P7/Z, [X11, X1,LSL #3]

  (172) 0x42513c LD1RD	{Z3.D}, P6/Z, [X5]

  (172) 0x425140 FADD	Z4.D, P7/M, Z4.D, Z7.D

  (172) 0x425144 FMUL	Z3.D, P7/M, Z3.D, Z31.D

  (172) 0x425148 FADD	Z4.D, P7/M, Z4.D, Z6.D

  (172) 0x42514c FMUL	Z3.D, P7/M, Z3.D, Z16.D

  (172) 0x425150 FADD	Z4.D, P7/M, Z4.D, Z5.D

  (172) 0x425154 FMUL	Z3.D, P7/M, Z3.D, Z4.D

  (172) 0x425158 ST1D	{Z3.D}, P7, [X3, X1,LSL #3]

  (172) 0x42515c LD1D	{Z30.D}, P7/Z, [X8, X1,LSL #3]

  (172) 0x425160 LD1D	{Z1.D}, P7/Z, [X13, X1,LSL #3]

  (172) 0x425164 LD1D	{Z0.D}, P7/Z, [X6, X1,LSL #3]

  (172) 0x425168 LD1D	{Z28.D}, P7/Z, [X12, X1,LSL #3]

  (172) 0x42516c LD1D	{Z2.D}, P7/Z, [X10, X1,LSL #3]

  (172) 0x425170 FADD	Z30.D, P7/M, Z30.D, Z1.D

  (172) 0x425174 LD1RD	{Z29.D}, P6/Z, [X5]

  (172) 0x425178 FADD	Z30.D, P7/M, Z30.D, Z0.D

  (172) 0x42517c FMUL	Z29.D, P7/M, Z29.D, Z31.D

  (172) 0x425180 FADD	Z30.D, P7/M, Z30.D, Z28.D

  (172) 0x425184 FMUL	Z29.D, P7/M, Z29.D, Z2.D

  (172) 0x425188 FMUL	Z29.D, P7/M, Z29.D, Z30.D

  (172) 0x42518c ST1D	{Z29.D}, P7, [X2, X1,LSL #3]

  (172) 0x425190 ADD	X1, X1, X16

  (172) 0x425194 WHILELO	P7.D, X1, X4

  (172) 0x425198 B.NE	425128

(171) 0x42519c ADD	X11, X11, X23

(171) 0x4251a0 ADD	X9, X9, X27

(171) 0x4251a4 ADD	X7, X7, X26

(171) 0x4251a8 ADD	X3, X3, X25

(171) 0x4251ac ADD	X10, X10, X22

(171) 0x4251b0 ADD	X8, X8, X21

(171) 0x4251b4 ADD	X6, X6, X20

(171) 0x4251b8 ADD	X2, X2, X24

(171) 0x4251bc CMP	W18, W0

(171) 0x4251c0 B.LE	4251f0

(171) 0x4251c4 CMP	W30, W17

(171) 0x4251c8 B.GT	425100

0x4251cc LDR	W30, [SP, #120]

0x4251d0 CBNZ	W30, 42520c

0x4251d4 LDP	X23, X24, [SP, #48]

0x4251d8 LDP	X25, X26, [SP, #64]

0x4251dc LDP	X27, X28, [SP, #80]

0x4251e0 LDP	X19, X20, [SP, #16]

0x4251e4 LDP	X21, X22, [SP, #32]

0x4251e8 LDP	X29, X30, [SP], #128

0x4251ec RET

(171) 0x4251f0 CMP	W30, W17

(171) 0x4251f4 B.LE	425214

(171) 0x4251f8 LDR	W15, [SP, #116]

(171) 0x4251fc MOVZ	W13, #1

(171) 0x425200 STR	W13, [SP, #120]

(171) 0x425204 STR	W15, [SP, #124]

(171) 0x425208 B	425100

0x42520c LDR	W16, [SP, #124]

0x425210 STR	W16, [SP, #116]

0x425214 LDR	W27, [SP, #116]

0x425218 STR	W27, [X19, #232]

0x42521c LDP	X23, X24, [SP, #48]

0x425220 LDP	X25, X26, [SP, #64]

0x425224 LDP	X27, X28, [SP, #80]

0x425228 LDP	X19, X20, [SP, #16]

0x42522c LDP	X21, X22, [SP, #32]

0x425230 LDP	X29, X30, [SP], #128

0x425234 RET

0x425238 ADD	W5, W5, #1

0x42523c MOVZ	W6, #0

0x425240 B	424fcc

Coverage (%)	Name	Source Location	Module
►98.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	GOMP_parallel		libgomp.so.1.0.0
○	flux_calc_kernel	flux_calc_kernel.f90:67	exec
○	flux_calc	flux_calc.f90:41	exec
○	hydro	hydro.f90:62	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	flux_calc_kernel.f90:49-60
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:49-60.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.00 to 12.50 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 18.00 to 12.50 cycles (1.44x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.00 to 17.00 cycles (1.06x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:53
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:53

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 21 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	119
nb uops	119
loop length	476
used w registers	18
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	16.00	16.00	18.00	16.00	0.50	0.50	0.00	0.00	15.67	15.67	15.67	5.00	5.00
cycles	4.00	4.00	16.00	16.00	18.00	16.00	0.50	0.50	0.00	0.00	15.67	15.67	15.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	14.88
Dispatch	18.00
DIV/SQRT	5.00-12.50
Overall L1	18.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	38%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	23%
other	28%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	29%
load	38%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	23%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

1% of peak load performance is reached (1.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424f80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W17, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 425238 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W7, W5, W17, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4251e0 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W17, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W30, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X15, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z31.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X18, X1, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X6, X4, [X19, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X5, [X19, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X26, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X13, XZR, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X23, X11, [X19, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X12, X15, X26, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X27, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X28, XZR, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X21, X8, [X19, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X14, X15, X27, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X22, X10, [X19, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X28, X28, X15, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X25, X3, [X19, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X2, [X19, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR W18, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X19, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X0, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X4, X13, X15, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X10, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X13, X15, X23, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X11, [X19, #224]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X3, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X14, X15, X6, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X6, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X9, X15, X9, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X12, [X19, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X8, X15, X21, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X5, X6, [X19, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X21, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X7, X15, X22, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X3, X15, X25, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X25, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X2, X15, X24, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X15, X15, X20, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X20, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X5, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X7, X1, [X19, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP W18, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD X11, X12, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL W13, W18, W0, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X9, X6, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W4, W0, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P15.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
STP W13, WZR, [SP, #116]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X7, X7, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [X19, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X1, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X15, [X19, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [X19, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X14, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X12, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X15, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W30, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CBNZ W30, 42520c <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W16, [SP, #124]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W16, [SP, #116]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W27, [SP, #116]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W27, [X19, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 424fcc <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	flux_calc_kernel.f90:49-60
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.00 to 17.00 cycles (1.06x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:53
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:53

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 21 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	119
nb uops	119
loop length	476
used w registers	18
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	16.00	16.00	18.00	16.00	0.50	0.50	0.00	0.00	15.67	15.67	15.67	5.00	5.00
cycles	4.00	4.00	16.00	16.00	18.00	16.00	0.50	0.50	0.00	0.00	15.67	15.67	15.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	14.88
Dispatch	18.00
DIV/SQRT	5.00-12.50
Overall L1	18.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	38%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	23%
other	28%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	29%
load	38%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	23%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

1% of peak load performance is reached (1.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424f80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W17, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 425238 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W7, W5, W17, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4251e0 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W17, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W30, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X15, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z31.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X18, X1, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X6, X4, [X19, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X5, [X19, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X26, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X13, XZR, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X23, X11, [X19, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X12, X15, X26, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X27, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X28, XZR, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X21, X8, [X19, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X14, X15, X27, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X22, X10, [X19, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X28, X28, X15, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X25, X3, [X19, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X2, [X19, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR W18, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X19, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X0, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X4, X13, X15, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X10, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X13, X15, X23, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X11, [X19, #224]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X3, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X14, X15, X6, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X6, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X9, X15, X9, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X12, [X19, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X8, X15, X21, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X5, X6, [X19, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X21, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X7, X15, X22, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X3, X15, X25, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X25, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X2, X15, X24, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X15, X15, X20, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X20, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X5, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X7, X1, [X19, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP W18, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD X11, X12, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL W13, W18, W0, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X9, X6, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W4, W0, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P15.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
STP W13, WZR, [SP, #116]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X7, X7, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [X19, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X1, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X15, [X19, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [X19, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X14, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X12, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X15, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W30, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CBNZ W30, 42520c <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W16, [SP, #124]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W16, [SP, #116]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W27, [SP, #116]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W27, [X19, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 424fcc <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0–	4.69	6.22
▼Loop 171 - flux_calc_kernel.f90:49-60 - exec–	0.00	0.02
○Loop 172 - flux_calc_kernel.f90:58-60 - exec	4.68	6.17

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Expensive FP math instructions/calls

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code