| Function: __generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0 | Module: exec | Source: generate_chunk_kernel.f90:85-161 | Coverage (incl. loops): 0.03% | (excl. loops): 0.03% |
|---|
| Function: __generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0 | Module: exec | Source: generate_chunk_kernel.f90:85-161 | Coverage (incl. loops): 0.03% | (excl. loops): 0.03% |
|---|
/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 85 - 161 |
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85: !$OMP PARALLEL SHARED(x_cent,y_cent) |
86: !$OMP DO |
87: DO k=y_min-2,y_max+2 |
88: !$OMP SIMD |
89: DO j=x_min-2,x_max+2 |
90: energy0(j,k)=state_energy(1) |
91: ENDDO |
92: ENDDO |
93: !$OMP END DO |
94: !$OMP DO |
95: DO k=y_min-2,y_max+2 |
96: !$OMP SIMD |
97: DO j=x_min-2,x_max+2 |
98: density0(j,k)=state_density(1) |
99: ENDDO |
100: ENDDO |
101: !$OMP END DO |
102: !$OMP DO |
103: DO k=y_min-2,y_max+2 |
104: !$OMP SIMD |
105: DO j=x_min-2,x_max+2 |
106: xvel0(j,k)=state_xvel(1) |
107: ENDDO |
108: ENDDO |
109: !$OMP END DO |
110: !$OMP DO |
111: DO k=y_min-2,y_max+2 |
112: !$OMP SIMD |
113: DO j=x_min-2,x_max+2 |
114: yvel0(j,k)=state_yvel(1) |
115: ENDDO |
116: ENDDO |
117: !$OMP END DO |
118: |
119: DO state=2,number_of_states |
120: |
121: ! Could the velocity setting be thread unsafe? |
122: x_cent=state_xmin(state) |
123: y_cent=state_ymin(state) |
124: |
125: !$OMP DO PRIVATE(radius,jt,kt) |
126: DO k=y_min-2,y_max+2 |
127: !$OMP SIMD |
128: DO j=x_min-2,x_max+2 |
129: IF(state_geometry(state).EQ.g_rect ) THEN |
130: IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN |
131: IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN |
132: energy0(j,k)=state_energy(state) |
133: density0(j,k)=state_density(state) |
134: DO kt=k,k+1 |
135: DO jt=j,j+1 |
136: xvel0(jt,kt)=state_xvel(state) |
137: yvel0(jt,kt)=state_yvel(state) |
138: ENDDO |
139: ENDDO |
140: ENDIF |
141: ENDIF |
142: ELSEIF(state_geometry(state).EQ.g_circ ) THEN |
143: radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent)) |
144: IF(radius.LE.state_radius(state))THEN |
145: energy0(j,k)=state_energy(state) |
146: density0(j,k)=state_density(state) |
147: DO kt=k,k+1 |
148: DO jt=j,j+1 |
149: xvel0(jt,kt)=state_xvel(state) |
150: yvel0(jt,kt)=state_yvel(state) |
151: ENDDO |
152: ENDDO |
153: ENDIF |
154: ELSEIF(state_geometry(state).EQ.g_point) THEN |
155: IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN |
156: energy0(j,k)=state_energy(state) |
157: density0(j,k)=state_density(state) |
158: DO kt=k,k+1 |
159: DO jt=j,j+1 |
160: xvel0(jt,kt)=state_xvel(state) |
161: yvel0(jt,kt)=state_yvel(state) |
0x425680 STP X29, X30, [SP, #656]! |
0x425684 ADD X29, SP, #0 |
0x425688 STP X25, X26, [SP, #64] |
0x42568c ORR X25, XZR, X0 |
0x425690 STP X19, X20, [SP, #16] |
0x425694 STP X21, X22, [SP, #32] |
0x425698 STP X23, X24, [SP, #48] |
0x42569c STP X27, X28, [SP, #80] |
0x4256a0 LDR X0, [X0, #16] |
0x4256a4 LDP X20, X21, [X25, #208] |
0x4256a8 LDR X1, [X25, #224] |
0x4256ac LDR X2, [X25, #232] |
0x4256b0 LDR X3, [X25, #240] |
0x4256b4 STR X1, [SP, #128] |
0x4256b8 LDR X4, [X25, #248] |
0x4256bc STR X2, [SP, #336] |
0x4256c0 LDR X5, [X25, #264] |
0x4256c4 STR X3, [SP, #120] |
0x4256c8 LDR X6, [X25, #280] |
0x4256cc STR X4, [SP, #328] |
0x4256d0 LDR X7, [X25, #296] |
0x4256d4 STR X5, [SP, #320] |
0x4256d8 LDR W26, [X0] |
0x4256dc STR X6, [SP, #312] |
0x4256e0 LDR X19, [X25, #256] |
0x4256e4 STR X7, [SP, #304] |
0x4256e8 BL 4103b0 |
0x4256ec STR W0, [SP, #108] |
0x4256f0 SUB W26, W26, #2 |
0x4256f4 BL 410330 |
0x4256f8 LDR X8, [X25, #24] |
0x4256fc ORR W27, WZR, W0 |
0x425700 LDR W1, [SP, #108] |
0x425704 LDR X24, [X25, #272] |
0x425708 LDR W9, [X8] |
0x42570c LDR X28, [X25, #288] |
0x425710 ADD W10, W9, #3 |
0x425714 SUB W11, W10, W26 |
0x425718 SDIV W12, W11, W1 |
0x42571c MSUB W13, W12, W1, W11 |
0x425720 CMP W0, W13 |
0x425724 B.LT 4263b0 |
0x425728 MADD W14, W12, W27, W13 |
0x42572c ADD W15, W12, W14 |
0x425730 CMP W14, W15 |
0x425734 B.GE 4257b0 |
0x425738 LDP X17, X18, [X25] |
0x42573c ADD W6, W26, W14 |
0x425740 ADD W7, W26, W15 |
0x425744 SBFM X16, X6, #0, #31 |
0x425748 MOVZ W9, #0 |
0x42574c LDR X2, [SP, #120] |
0x425750 LDR W12, [X18] |
0x425754 LDR X0, [SP, #328] |
0x425758 UBFM X11, X2, #61, #60 |
0x42575c LDR W26, [X17] |
0x425760 ADD X3, X0, W26,SXTW |
0x425764 MADD X4, X16, X2, X3 |
0x425768 ADD W13, W12, #5 |
0x42576c LDR X30, [X25, #72] |
0x425770 UBFM X5, X4, #61, #60 |
0x425774 ADD W4, W12, #3 |
0x425778 LDR X2, [X25, #112] |
0x42577c SUB X8, X5, #16 |
0x425780 SUB W17, W26, #2 |
0x425784 CMP W17, W4 |
0x425788 ADD X15, X30, X8 |
0x42578c CSEL W8, W17, W4, #10 |
(195) 0x425790 CMP W17, W4 |
(195) 0x425794 B.LT 4262f0 |
(195) 0x425798 ADD W6, W6, #1 |
(195) 0x42579c ADD X15, X15, X11 |
(195) 0x4257a0 B.LE 42641c |
(195) 0x4257a4 CMP W7, W6 |
(195) 0x4257a8 B.GT 425790 |
0x4257ac CBNZ W9, 4261c4 |
0x4257b0 STR W1, [SP, #108] |
0x4257b4 BL 4103a0 |
0x4257b8 LDP X9, X10, [X25, #16] |
0x4257bc LDR W1, [SP, #108] |
0x4257c0 LDR W11, [X9] |
0x4257c4 LDR W26, [X10] |
0x4257c8 SUB W18, W11, #2 |
0x4257cc ADD W2, W26, #3 |
0x4257d0 SUB W0, W2, W18 |
0x4257d4 SDIV W3, W0, W1 |
0x4257d8 MSUB W4, W3, W1, W0 |
0x4257dc CMP W27, W4 |
0x4257e0 B.LT 4263bc |
0x4257e4 MADD W16, W3, W27, W4 |
0x4257e8 ADD W17, W3, W16 |
0x4257ec CMP W16, W17 |
0x4257f0 B.GE 42586c |
0x4257f4 LDR X8, [SP, #128] |
0x4257f8 ADD W6, W18, W16 |
0x4257fc ADD W7, W18, W17 |
0x425800 LDP X5, X12, [X25] |
0x425804 SBFM X30, X6, #0, #31 |
0x425808 MOVZ W10, #0 |
0x42580c LDR X13, [X25, #64] |
0x425810 UBFM X11, X8, #61, #60 |
0x425814 LDR X15, [SP, #336] |
0x425818 LDR W14, [X5] |
0x42581c ADD X18, X15, W14,SXTW |
0x425820 MADD X26, X30, X8, X18 |
0x425824 LDR W4, [X12] |
0x425828 UBFM X2, X26, #61, #60 |
0x42582c SUB X0, X2, #16 |
0x425830 ADD X30, X13, X0 |
0x425834 LDR X13, [X25, #104] |
0x425838 SUB W9, W14, #2 |
0x42583c ADD W3, W4, #5 |
0x425840 ADD W8, W4, #3 |
0x425844 CMP W9, W8 |
0x425848 CSEL W16, W9, W8, #10 |
(192) 0x42584c CMP W9, W8 |
(192) 0x425850 B.LT 426350 |
(192) 0x425854 ADD W6, W6, #1 |
(192) 0x425858 ADD X30, X30, X11 |
(192) 0x42585c B.LE 4263f4 |
(192) 0x425860 CMP W7, W6 |
(192) 0x425864 B.GT 42584c |
0x425868 CBNZ W10, 4261d4 |
0x42586c STR W1, [SP, #108] |
0x425870 BL 4103a0 |
0x425874 LDP X14, X15, [X25, #16] |
0x425878 LDR W1, [SP, #108] |
0x42587c LDR W18, [X14] |
0x425880 LDR W2, [X15] |
0x425884 SUB W26, W18, #2 |
0x425888 ADD W0, W2, #3 |
0x42588c SUB W4, W0, W26 |
0x425890 SDIV W3, W4, W1 |
0x425894 MSUB W6, W3, W1, W4 |
0x425898 CMP W27, W6 |
0x42589c B.LT 4263d4 |
0x4258a0 MADD W16, W3, W27, W6 |
0x4258a4 ADD W17, W3, W16 |
0x4258a8 CMP W16, W17 |
0x4258ac B.GE 425924 |
0x4258b0 LDP X12, X13, [X25] |
0x4258b4 ADD W6, W26, W16 |
0x4258b8 ADD W7, W26, W17 |
0x4258bc SBFM X30, X6, #0, #31 |
0x4258c0 MOVZ W10, #0 |
0x4258c4 UBFM X11, X24, #61, #60 |
0x4258c8 LDR X14, [X25, #80] |
0x4258cc LDR W8, [X13] |
0x4258d0 LDR X15, [SP, #312] |
0x4258d4 LDR W5, [X12] |
0x4258d8 ADD X18, X15, W5,SXTW |
0x4258dc MADD X26, X30, X24, X18 |
0x4258e0 ADD W3, W8, #5 |
0x4258e4 LDR X4, [X25, #120] |
0x4258e8 UBFM X2, X26, #61, #60 |
0x4258ec SUB X0, X2, #16 |
0x4258f0 SUB W9, W5, #2 |
0x4258f4 ADD X30, X14, X0 |
0x4258f8 ADD W14, W8, #3 |
0x4258fc CMP W14, W9 |
0x425900 CSEL W16, W14, W9, #10 |
(189) 0x425904 CMP W14, W9 |
(189) 0x425908 B.GT 426290 |
(189) 0x42590c ADD W6, W6, #1 |
(189) 0x425910 ADD X30, X30, X11 |
(189) 0x425914 B.GE 426408 |
(189) 0x425918 CMP W7, W6 |
(189) 0x42591c B.GT 425904 |
0x425920 CBNZ W10, 4261e4 |
0x425924 STR W1, [SP, #108] |
0x425928 BL 4103a0 |
0x42592c LDP X10, X1, [X25, #16] |
0x425930 LDR W23, [SP, #108] |
0x425934 LDR W8, [X10] |
0x425938 LDR W15, [X1] |
0x42593c SUB W5, W8, #2 |
0x425940 ADD W18, W15, #3 |
0x425944 SUB W26, W18, W5 |
0x425948 SDIV W2, W26, W23 |
0x42594c MSUB W0, W2, W23, W26 |
0x425950 CMP W27, W0 |
0x425954 B.LT 4263c8 |
0x425958 MADD W3, W2, W27, W0 |
0x42595c ADD W16, W2, W3 |
0x425960 CMP W3, W16 |
0x425964 B.GE 4259dc |
0x425968 LDP X30, X12, [X25] |
0x42596c ADD W6, W5, W3 |
0x425970 ADD W7, W5, W16 |
0x425974 SBFM X17, X6, #0, #31 |
0x425978 MOVZ W10, #0 |
0x42597c UBFM X11, X28, #61, #60 |
0x425980 LDR X13, [X25, #88] |
0x425984 LDR X8, [SP, #304] |
0x425988 LDR W14, [X12] |
0x42598c LDR W1, [X30] |
0x425990 ADD X5, X8, W1,SXTW |
0x425994 MADD X15, X17, X28, X5 |
0x425998 LDR X4, [X25, #128] |
0x42599c UBFM X18, X15, #61, #60 |
0x4259a0 ADD W0, W14, #5 |
0x4259a4 SUB X26, X18, #16 |
0x4259a8 ADD W12, W14, #3 |
0x4259ac ADD X2, X13, X26 |
0x4259b0 SUB W9, W1, #2 |
0x4259b4 CMP W12, W9 |
0x4259b8 CSEL W16, W12, W9, #10 |
(186) 0x4259bc CMP W12, W9 |
(186) 0x4259c0 B.GT 42622c |
(186) 0x4259c4 ADD W6, W6, #1 |
(186) 0x4259c8 ADD X2, X2, X11 |
(186) 0x4259cc B.GE 4263e0 |
(186) 0x4259d0 CMP W7, W6 |
(186) 0x4259d4 B.GT 4259bc |
0x4259d8 CBNZ W10, 4261f0 |
0x4259dc STR W23, [SP, #108] |
0x4259e0 BL 4103a0 |
0x4259e4 LDR X22, [X25, #96] |
0x4259e8 LDR W23, [X22] |
0x4259ec CMP W23, #1 |
0x4259f0 B.LE 425de0 |
0x4259f4 LDR X13, [SP, #304] |
0x4259f8 UBFM X21, X21, #61, #60 |
0x4259fc UBFM X15, X19, #61, #60 |
0x425a00 STR W27, [SP, #288] |
0x425a04 ORR X27, XZR, X24 |
0x425a08 ORR W10, WZR, W23 |
0x425a0c LDR X8, [SP, #320] |
0x425a10 MOVZ X26, #1 |
0x425a14 STR X10, [SP, #280] |
0x425a18 LDR W24, [SP, #108] |
0x425a1c SUB X14, XZR, X13,LSL #3 |
0x425a20 SUB X1, X13, #1 |
0x425a24 STR X15, [SP, #352] |
0x425a28 SUB X5, X21, X8,LSL #3 |
0x425a2c STR X1, [SP, #256] |
0x425a30 ADD X20, X14, X20,LSL #3 |
0x425a34 ADD X19, X14, X19,LSL #3 |
0x425a38 STR W24, [SP, #292] |
0x425a3c STR X5, [SP, #360] |
0x425a40 STP X19, X20, [SP, #240] |
0x425a44 B 425a5c |
(177) 0x425a48 BL 4103a0 |
(177) 0x425a4c LDR X13, [SP, #280] |
(177) 0x425a50 ADD X26, X26, #1 |
(177) 0x425a54 CMP X26, X13 |
(177) 0x425a58 B.EQ 425de0 |
(177) 0x425a5c LDP X18, X0, [X25, #16] |
(177) 0x425a60 LDR W4, [SP, #292] |
(177) 0x425a64 LDR W16, [X0] |
(177) 0x425a68 LDR W6, [X18] |
(177) 0x425a6c LDR X10, [X25, #136] |
(177) 0x425a70 ADD W17, W16, #3 |
(177) 0x425a74 LDR X30, [X25, #152] |
(177) 0x425a78 SUB W2, W6, #2 |
(177) 0x425a7c SUB W3, W17, W2 |
(177) 0x425a80 LDR D27, [X10, X26,LSL #3] |
(177) 0x425a84 SDIV W12, W3, W4 |
(177) 0x425a88 LDR D26, [X30, X26,LSL #3] |
(177) 0x425a8c STP D26, D27, [X25, #304] |
(177) 0x425a90 LDR W7, [SP, #288] |
(177) 0x425a94 STR X30, [SP, #264] |
(177) 0x425a98 MSUB W9, W12, W4, W3 |
(177) 0x425a9c CMP W7, W9 |
(177) 0x425aa0 B.LT 425ff0 |
(177) 0x425aa4 LDR W11, [SP, #288] |
(177) 0x425aa8 MADD W22, W12, W11, W9 |
(177) 0x425aac ADD W23, W12, W22 |
(177) 0x425ab0 CMP W22, W23 |
(177) 0x425ab4 B.GE 425a48 |
(177) 0x425ab8 LDR X3, [X25, #8] |
(177) 0x425abc ADD W13, W2, W23 |
(177) 0x425ac0 ADD W24, W2, W22 |
(177) 0x425ac4 LDP X1, X8, [SP, #320] |
(177) 0x425ac8 SBFM X21, X24, #0, #31 |
(177) 0x425acc MOVZ W0, #0 |
(177) 0x425ad0 UBFM X19, X26, #61, #31 |
(177) 0x425ad4 STR W13, [SP, #172] |
(177) 0x425ad8 LDR X14, [X25] |
(177) 0x425adc LDP X2, X7, [SP, #304] |
(177) 0x425ae0 ADD X15, X21, X1 |
(177) 0x425ae4 LDR W4, [X3] |
(177) 0x425ae8 MADD X11, X21, X27, X7 |
(177) 0x425aec LDR W20, [X14] |
(177) 0x425af0 LDR X6, [SP, #128] |
(177) 0x425af4 ADD W23, W4, #4 |
(177) 0x425af8 ADD W9, W4, #3 |
(177) 0x425afc LDR X18, [SP, #336] |
(177) 0x425b00 SUB W13, W23, W20 |
(177) 0x425b04 ADD X14, X13, W20,SXTW |
(177) 0x425b08 SUB W12, W20, #2 |
(177) 0x425b0c LDR X5, [SP, #120] |
(177) 0x425b10 SBFM X17, X12, #0, #31 |
(177) 0x425b14 SUB W20, W20, #1 |
(177) 0x425b18 ADD X7, X17, X7 |
(177) 0x425b1c STR X14, [SP, #232] |
(177) 0x425b20 LDR X13, [SP, #360] |
(177) 0x425b24 MADD X22, X21, X6, X18 |
(177) 0x425b28 STR X7, [SP, #216] |
(177) 0x425b2c LDR X18, [X25, #56] |
(177) 0x425b30 MADD X8, X21, X5, X8 |
(177) 0x425b34 STR W20, [SP, #296] |
(177) 0x425b38 LDR X16, [X25, #32] |
(177) 0x425b3c MADD X21, X21, X28, X2 |
(177) 0x425b40 ADD X2, X17, X2 |
(177) 0x425b44 LDR X5, [X25, #48] |
(177) 0x425b48 ADD X14, X18, X13 |
(177) 0x425b4c STR X2, [SP, #224] |
(177) 0x425b50 LDR X4, [X25, #144] |
(177) 0x425b54 STR X14, [SP, #160] |
(177) 0x425b58 LDR X6, [X25, #176] |
(177) 0x425b5c STR X16, [SP, #200] |
(177) 0x425b60 LDR X3, [X25, #184] |
(177) 0x425b64 STR X5, [SP, #208] |
(177) 0x425b68 LDR X23, [X25, #192] |
(177) 0x425b6c STR X6, [SP, #176] |
(177) 0x425b70 LDR X1, [SP, #352] |
(177) 0x425b74 STR X3, [SP, #184] |
(177) 0x425b78 STR X4, [SP, #272] |
(177) 0x425b7c LDR X30, [X25, #168] |
(177) 0x425b80 STR X23, [SP, #192] |
(177) 0x425b84 LDR X20, [X25, #200] |
(177) 0x425b88 ADD X16, X16, X1 |
(177) 0x425b8c STR W9, [SP, #108] |
(183) 0x425b90 LDR W9, [SP, #108] |
(183) 0x425b94 ADD W24, W24, #1 |
(183) 0x425b98 CMP W12, W9 |
(183) 0x425b9c B.GE 425d94 |
(178) 0x425ba0 LDR X0, [SP, #176] |
(178) 0x425ba4 LDR X7, [SP, #184] |
(178) 0x425ba8 LDR W6, [X0, X26,LSL #2] |
(178) 0x425bac LDR W3, [X7] |
(178) 0x425bb0 CMP W6, W3 |
(178) 0x425bb4 B.EQ 425eac |
(180) 0x425bb8 LDR X14, [SP, #216] |
(180) 0x425bbc SBFM X7, X24, #0, #31 |
(180) 0x425bc0 ADD X3, X17, X8 |
(180) 0x425bc4 ADD X2, X17, X22 |
(180) 0x425bc8 ADD X5, X17, X11 |
(180) 0x425bcc STR X8, [SP, #152] |
(180) 0x425bd0 LDR X9, [SP, #240] |
(180) 0x425bd4 MUL X18, X7, X28 |
(180) 0x425bd8 ADD X4, X17, X21 |
(180) 0x425bdc STR W24, [SP, #168] |
(180) 0x425be0 LDR X0, [SP, #256] |
(180) 0x425be4 MADD X1, X7, X27, X14 |
(180) 0x425be8 LDR X23, [SP, #192] |
(180) 0x425bec SUB X7, X9, X18,LSL #3 |
(180) 0x425bf0 LDR X9, [SP, #224] |
(180) 0x425bf4 ADD X14, X0, X18 |
(180) 0x425bf8 LDR X13, [SP, #248] |
(180) 0x425bfc LDR W23, [X23] |
(180) 0x425c00 ADD X0, X9, X18 |
(180) 0x425c04 STP X28, X27, [SP, #136] |
(180) 0x425c08 SUB X18, X13, X18,LSL #3 |
(180) 0x425c0c LDR X9, [SP, #200] |
(180) 0x425c10 LDR X27, [SP, #208] |
(180) 0x425c14 LDR X13, [SP, #232] |
(180) 0x425c18 ADD X7, X9, X7 |
(180) 0x425c1c ADD X8, X27, X18 |
(180) 0x425c20 STR X7, [SP, #112] |
(180) 0x425c24 ADD X14, X13, X14 |
(180) 0x425c28 B 425c68 |
(181) 0x425c2c LDR W28, [X20] |
(181) 0x425c30 CMP W6, W28 |
(181) 0x425c34 B.EQ 425dfc |
(181) 0x425c38 ADD X18, X5, #1 |
(181) 0x425c3c ADD X13, X4, #1 |
(181) 0x425c40 ADD X9, X1, #1 |
(181) 0x425c44 ADD X7, X0, #1 |
(181) 0x425c48 ADD X3, X3, #1 |
(181) 0x425c4c ADD X2, X2, #1 |
(181) 0x425c50 ORR X5, XZR, X18 |
(181) 0x425c54 ORR X4, XZR, X13 |
(181) 0x425c58 ORR X1, XZR, X9 |
(181) 0x425c5c ORR X0, XZR, X7 |
(181) 0x425c60 CMP X7, X14 |
(181) 0x425c64 B.EQ 425d40 |
(181) 0x425c68 CMP W6, W23 |
(181) 0x425c6c B.NE 425c2c |
(181) 0x425c70 LDR X24, [SP, #160] |
(181) 0x425c74 LDR D31, [X8, X0,LSL #3] |
(181) 0x425c78 LDR D30, [X30, X26,LSL #3] |
(181) 0x425c7c LDR D29, [X24, X15,LSL #3] |
(181) 0x425c80 FSUB D28, D31, S27 |
(181) 0x425c84 FSUB D6, D29, S26 |
(181) 0x425c88 FMUL D7, D6, D6 |
(181) 0x425c8c FMADD D5, D28, D28, D7 |
(181) 0x425c90 FSQRT D4, D5 |
(181) 0x425c94 FCMPE D30, D4 |
(181) 0x425c98 B.GE 425ca0 |
(181) 0x425c9c B 425c38 |
(181) 0x425ca0 LDP X27, X7, [X25, #104] |
(181) 0x425ca4 ADD X18, X5, #1 |
(181) 0x425ca8 ADD X13, X4, #1 |
(181) 0x425cac ADD X9, X1, #1 |
(181) 0x425cb0 LDR X24, [X25, #72] |
(181) 0x425cb4 LDR D3, [X7, X26,LSL #3] |
(181) 0x425cb8 ADD X7, X0, #1 |
(181) 0x425cbc LDR X28, [X25, #120] |
(181) 0x425cc0 STR D3, [X24, X3,LSL #3] |
(181) 0x425cc4 ADD X3, X3, #1 |
(181) 0x425cc8 LDR D2, [X27, X26,LSL #3] |
(181) 0x425ccc LDR X24, [X25, #64] |
(181) 0x425cd0 LDR X27, [X25, #80] |
(181) 0x425cd4 STR D2, [X24, X2,LSL #3] |
(181) 0x425cd8 ADD X2, X2, #1 |
(181) 0x425cdc LDR D1, [X28, X19] |
(181) 0x425ce0 LDR X24, [X25, #128] |
(181) 0x425ce4 STR D1, [X27, X5,LSL #3] |
(181) 0x425ce8 LDR D0, [X24, X19] |
(181) 0x425cec LDR X5, [X25, #88] |
(181) 0x425cf0 STR D0, [X5, X4,LSL #3] |
(181) 0x425cf4 ORR X4, XZR, X13 |
(181) 0x425cf8 LDR D16, [X28, X19] |
(181) 0x425cfc STR D16, [X27, X18,LSL #3] |
(181) 0x425d00 LDR D17, [X24, X19] |
(181) 0x425d04 STR D17, [X5, X13,LSL #3] |
(181) 0x425d08 LDR D18, [X28, X19] |
(181) 0x425d0c STR D18, [X27, X1,LSL #3] |
(181) 0x425d10 ORR X1, XZR, X9 |
(181) 0x425d14 LDR D19, [X24, X19] |
(181) 0x425d18 STR D19, [X5, X0,LSL #3] |
(181) 0x425d1c ORR X0, XZR, X7 |
(181) 0x425d20 LDR D20, [X28, X19] |
(181) 0x425d24 STR D20, [X27, X9,LSL #3] |
(181) 0x425d28 LDR D21, [X24, X19] |
(181) 0x425d2c STR D21, [X5, X7,LSL #3] |
(181) 0x425d30 ORR X5, XZR, X18 |
(181) 0x425d34 CMP X7, X14 |
(181) 0x425d38 B.NE 425c68 |
(180) 0x425d3c HINT #0 |
(180) 0x425d40 LDR X8, [SP, #152] |
(180) 0x425d44 LDP X28, X27, [SP, #136] |
(180) 0x425d48 LDR W24, [SP, #168] |
(180) 0x425d4c ADD X18, X15, #1 |
(178) 0x425d50 LDR X6, [SP, #120] |
(178) 0x425d54 ORR X15, XZR, X18 |
(178) 0x425d58 ADD X11, X11, X27 |
(178) 0x425d5c ADD X21, X21, X28 |
(178) 0x425d60 LDR X23, [SP, #128] |
(178) 0x425d64 LDR W14, [SP, #172] |
(178) 0x425d68 ADD X8, X8, X6 |
(178) 0x425d6c ADD X22, X22, X23 |
(178) 0x425d70 CMP W14, W24 |
(178) 0x425d74 B.LE 426030 |
(178) 0x425d78 LDR W9, [SP, #108] |
(178) 0x425d7c MOVZ W0, #1 |
(178) 0x425d80 ADD W24, W24, #1 |
(178) 0x425d84 STR W9, [SP, #300] |
(178) 0x425d88 LDR W9, [SP, #108] |
(178) 0x425d8c CMP W12, W9 |
(178) 0x425d90 B.LT 425ba0 |
(182) 0x425d94 B.EQ 425d4c |
(183) 0x425d98 LDR X1, [SP, #120] |
(183) 0x425d9c ADD X15, X15, #1 |
(183) 0x425da0 ADD X11, X11, X27 |
(183) 0x425da4 ADD X21, X21, X28 |
(183) 0x425da8 LDR X18, [SP, #128] |
(183) 0x425dac LDR W5, [SP, #172] |
(183) 0x425db0 ADD X8, X8, X1 |
(183) 0x425db4 ADD X22, X22, X18 |
(183) 0x425db8 CMP W5, W24 |
(183) 0x425dbc B.GT 425b90 |
(177) 0x425dc0 CBZ W0, 425a48 |
(177) 0x425dc4 LDR W18, [SP, #300] |
(177) 0x425dc8 STR W18, [X25, #320] |
(177) 0x425dcc BL 4103a0 |
(177) 0x425dd0 LDR X13, [SP, #280] |
(177) 0x425dd4 ADD X26, X26, #1 |
(177) 0x425dd8 CMP X26, X13 |
(177) 0x425ddc B.NE 425a5c |
0x425de0 LDP X19, X20, [SP, #16] |
0x425de4 LDP X21, X22, [SP, #32] |
0x425de8 LDP X23, X24, [SP, #48] |
0x425dec LDP X25, X26, [SP, #64] |
0x425df0 LDP X27, X28, [SP, #80] |
0x425df4 LDP X29, X30, [SP], #368 |
0x425df8 RET |
(181) 0x425dfc LDR X24, [SP, #112] |
(181) 0x425e00 LDR D1, [X24, X0,LSL #3] |
(181) 0x425e04 FCMP D27, D1 |
(181) 0x425e08 B.NE 425c38 |
(181) 0x425e0c LDR X18, [X25, #40] |
(181) 0x425e10 LDR D0, [X18, X15,LSL #3] |
(181) 0x425e14 FCMP D26, D0 |
(181) 0x425e18 B.NE 425c38 |
(181) 0x425e1c LDP X28, X7, [X25, #104] |
(181) 0x425e20 UBFM X24, X26, #61, #31 |
(181) 0x425e24 ADD X18, X5, #1 |
(181) 0x425e28 ADD X13, X4, #1 |
(181) 0x425e2c ADD X9, X1, #1 |
(181) 0x425e30 LDR X27, [X25, #72] |
(181) 0x425e34 LDR D16, [X7, X26,LSL #3] |
(181) 0x425e38 ADD X7, X0, #1 |
(181) 0x425e3c STR D16, [X27, X3,LSL #3] |
(181) 0x425e40 LDR D17, [X28, X26,LSL #3] |
(181) 0x425e44 LDR X27, [X25, #64] |
(181) 0x425e48 LDR X28, [X25, #120] |
(181) 0x425e4c STR D17, [X27, X2,LSL #3] |
(181) 0x425e50 LDR X27, [X25, #128] |
(181) 0x425e54 LDR D18, [X28, X24] |
(181) 0x425e58 STR X27, [SP, #344] |
(181) 0x425e5c LDR X27, [X25, #80] |
(181) 0x425e60 STR D18, [X27, X5,LSL #3] |
(181) 0x425e64 LDR X27, [SP, #344] |
(181) 0x425e68 LDR X5, [X25, #88] |
(181) 0x425e6c LDR D19, [X27, X24] |
(181) 0x425e70 STR D19, [X5, X4,LSL #3] |
(181) 0x425e74 LDR D20, [X28, X24] |
(181) 0x425e78 LDR X4, [X25, #80] |
(181) 0x425e7c STR D20, [X4, X18,LSL #3] |
(181) 0x425e80 LDR D21, [X27, X24] |
(181) 0x425e84 STR D21, [X5, X13,LSL #3] |
(181) 0x425e88 LDR D22, [X28, X24] |
(181) 0x425e8c STR D22, [X4, X1,LSL #3] |
(181) 0x425e90 LDR D23, [X27, X24] |
(181) 0x425e94 STR D23, [X5, X0,LSL #3] |
(181) 0x425e98 LDR D24, [X28, X24] |
(181) 0x425e9c STR D24, [X4, X9,LSL #3] |
(181) 0x425ea0 LDR D25, [X27, X24] |
(181) 0x425ea4 STR D25, [X5, X7,LSL #3] |
(181) 0x425ea8 B 425c48 |
(178) 0x425eac LDR W4, [SP, #296] |
(178) 0x425eb0 ORN W2, WZR, W12 |
(178) 0x425eb4 SBFM X0, X12, #0, #31 |
(178) 0x425eb8 ADD X18, X15, #1 |
(178) 0x425ebc LDR D6, [X10, X26,LSL #3] |
(178) 0x425ec0 LDR W23, [SP, #108] |
(178) 0x425ec4 SBFM X1, X4, #0, #31 |
(178) 0x425ec8 LDR D7, [X16, W4,SXTW #3] |
(178) 0x425ecc ADD W13, W23, W2 |
(178) 0x425ed0 AND W2, W13, #0x1 |
(178) 0x425ed4 FCMPE D7, D6 |
(178) 0x425ed8 B.GE 425ffc |
(178) 0x425edc LDR W6, [SP, #108] |
(178) 0x425ee0 ADD X0, X0, #1 |
(178) 0x425ee4 ADD X1, X1, #1 |
(178) 0x425ee8 CMP W6, W0 |
(178) 0x425eec B.LE 425d50 |
(178) 0x425ef0 CBZ W2, 425f18 |
(178) 0x425ef4 LDR D31, [X16, X1,LSL #3] |
(178) 0x425ef8 LDR D30, [X10, X26,LSL #3] |
(178) 0x425efc FCMPE D31, D30 |
(178) 0x425f00 B.GE 4261f8 |
(178) 0x425f04 LDR W2, [SP, #108] |
(178) 0x425f08 ADD X0, X0, #1 |
(178) 0x425f0c ADD X1, X1, #1 |
(178) 0x425f10 CMP W2, W0 |
(178) 0x425f14 B.LE 425d50 |
(178) 0x425f18 LDR W2, [SP, #108] |
(179) 0x425f1c LDR D22, [X16, X1,LSL #3] |
(179) 0x425f20 LDR D23, [X10, X26,LSL #3] |
(179) 0x425f24 FCMPE D22, D23 |
(179) 0x425f28 B.GE 425f58 |
(179) 0x425f2c FMOV D18, D23 |
(179) 0x425f30 ADD X1, X1, #1 |
(179) 0x425f34 ADD X0, X0, #1 |
(179) 0x425f38 LDR D19, [X16, X1,LSL #3] |
(179) 0x425f3c FCMPE D19, D18 |
(179) 0x425f40 B.GE 425fa4 |
(179) 0x425f44 ADD X0, X0, #1 |
(179) 0x425f48 ADD X1, X1, #1 |
(179) 0x425f4c CMP W2, W0 |
(179) 0x425f50 B.GT 425f1c |
(178) 0x425f54 B 425d50 |
(179) 0x425f58 LDR X6, [SP, #272] |
(179) 0x425f5c LDR D24, [X16, X0,LSL #3] |
(179) 0x425f60 LDR D25, [X6, X26,LSL #3] |
(179) 0x425f64 FCMPE D24, D25 |
(179) 0x425f68 B.MI 425f70 |
(179) 0x425f6c B 425f2c |
(179) 0x425f70 LDR X14, [X25, #40] |
(179) 0x425f74 LDR X4, [SP, #264] |
(179) 0x425f78 LDR D31, [X14, X18,LSL #3] |
(179) 0x425f7c LDR D30, [X4, X26,LSL #3] |
(179) 0x425f80 FCMPE D31, D30 |
(179) 0x425f84 B.GE 425f8c |
(179) 0x425f88 B 425f2c |
(179) 0x425f8c LDR X23, [X25, #160] |
(179) 0x425f90 LDR D28, [X14, X15,LSL #3] |
(179) 0x425f94 LDR D29, [X23, X26,LSL #3] |
(179) 0x425f98 FCMPE D28, D29 |
(179) 0x425f9c B.MI 426054 |
(179) 0x425fa0 B 425f2c |
(179) 0x425fa4 LDR X7, [SP, #272] |
(179) 0x425fa8 LDR D20, [X16, X0,LSL #3] |
(179) 0x425fac LDR D21, [X7, X26,LSL #3] |
(179) 0x425fb0 FCMPE D20, D21 |
(179) 0x425fb4 B.MI 425fbc |
(179) 0x425fb8 B 425f44 |
(179) 0x425fbc LDR X5, [X25, #40] |
(179) 0x425fc0 LDR X23, [SP, #264] |
(179) 0x425fc4 LDR D22, [X5, X18,LSL #3] |
(179) 0x425fc8 LDR D23, [X23, X26,LSL #3] |
(179) 0x425fcc FCMPE D22, D23 |
(179) 0x425fd0 B.GE 425fd8 |
(179) 0x425fd4 B 425f44 |
(179) 0x425fd8 LDR X13, [X25, #160] |
(179) 0x425fdc LDR D24, [X5, X15,LSL #3] |
(179) 0x425fe0 LDR D25, [X13, X26,LSL #3] |
(179) 0x425fe4 FCMPE D24, D25 |
(179) 0x425fe8 B.MI 42610c |
(179) 0x425fec B 425f44 |
(177) 0x425ff0 ADD W12, W12, #1 |
(177) 0x425ff4 MOVZ W9, #0 |
(177) 0x425ff8 B 425aa4 |
(178) 0x425ffc LDR X14, [SP, #272] |
(178) 0x426000 LDR D5, [X16, W12,SXTW #3] |
(178) 0x426004 LDR D4, [X14, X26,LSL #3] |
(178) 0x426008 FCMPE D5, D4 |
(178) 0x42600c B.MI 426014 |
(178) 0x426010 B 425edc |
(178) 0x426014 LDR X9, [X25, #40] |
(178) 0x426018 LDR X5, [SP, #264] |
(178) 0x42601c LDR D3, [X9, X18,LSL #3] |
(178) 0x426020 LDR D2, [X5, X26,LSL #3] |
(178) 0x426024 FCMPE D3, D2 |
(178) 0x426028 B.GE 42603c |
(178) 0x42602c B 425edc |
(177) 0x426030 LDR W18, [SP, #108] |
(177) 0x426034 STR W18, [X25, #320] |
(177) 0x426038 B 425dcc |
(178) 0x42603c LDR X6, [X25, #160] |
(178) 0x426040 LDR D1, [X9, X15,LSL #3] |
(178) 0x426044 LDR D0, [X6, X26,LSL #3] |
(178) 0x426048 FCMPE D1, D0 |
(178) 0x42604c B.MI 426448 |
(178) 0x426050 B 425edc |
(179) 0x426054 LDP X14, X6, [X25, #104] |
(179) 0x426058 ADD X13, X0, X8 |
(179) 0x42605c ADD X5, X0, X22 |
(179) 0x426060 SBFM X4, X24, #0, #31 |
(179) 0x426064 UBFM X3, X26, #61, #31 |
(179) 0x426068 ADD X9, X0, X21 |
(179) 0x42606c LDR X7, [X25, #72] |
(179) 0x426070 LDR D6, [X6, X26,LSL #3] |
(179) 0x426074 LDR X23, [X25, #64] |
(179) 0x426078 STR D6, [X7, X13,LSL #3] |
(179) 0x42607c LDR D7, [X14, X26,LSL #3] |
(179) 0x426080 LDR X7, [X25, #120] |
(179) 0x426084 STR D7, [X23, X5,LSL #3] |
(179) 0x426088 LDP X13, X14, [SP, #304] |
(179) 0x42608c LDR D5, [X7, X3] |
(179) 0x426090 MADD X6, X4, X27, X14 |
(179) 0x426094 MADD X4, X4, X28, X13 |
(179) 0x426098 LDR X5, [X25, #128] |
(179) 0x42609c ADD X23, X6, X0 |
(179) 0x4260a0 ADD X13, X6, X1 |
(179) 0x4260a4 LDR X6, [X25, #80] |
(179) 0x4260a8 ADD X14, X0, X4 |
(179) 0x4260ac ADD X4, X1, X4 |
(179) 0x4260b0 STR X4, [SP, #112] |
(179) 0x4260b4 ADD X4, X0, X11 |
(179) 0x4260b8 STR D5, [X6, X4,LSL #3] |
(179) 0x4260bc LDR D4, [X5, X3] |
(179) 0x4260c0 LDR X4, [X25, #88] |
(179) 0x4260c4 STR D4, [X4, X9,LSL #3] |
(179) 0x4260c8 ADD X9, X1, X11 |
(179) 0x4260cc LDR D3, [X7, X3] |
(179) 0x4260d0 STR D3, [X6, X9,LSL #3] |
(179) 0x4260d4 ADD X9, X1, X21 |
(179) 0x4260d8 LDR D2, [X5, X3] |
(179) 0x4260dc STR D2, [X4, X9,LSL #3] |
(179) 0x4260e0 LDR D1, [X7, X3] |
(179) 0x4260e4 STR D1, [X6, X23,LSL #3] |
(179) 0x4260e8 LDR D0, [X5, X3] |
(179) 0x4260ec STR D0, [X4, X14,LSL #3] |
(179) 0x4260f0 LDR D16, [X7, X3] |
(179) 0x4260f4 STR D16, [X6, X13,LSL #3] |
(179) 0x4260f8 LDR D17, [X5, X3] |
(179) 0x4260fc LDR X3, [SP, #112] |
(179) 0x426100 STR D17, [X4, X3,LSL #3] |
(179) 0x426104 LDR D18, [X10, X26,LSL #3] |
(179) 0x426108 B 425f30 |
(179) 0x42610c LDP X23, X6, [X25, #104] |
(179) 0x426110 ADD X7, X0, X8 |
(179) 0x426114 ADD X5, X0, X22 |
(179) 0x426118 SBFM X4, X24, #0, #31 |
(179) 0x42611c UBFM X3, X26, #61, #31 |
(179) 0x426120 ADD X9, X0, X21 |
(179) 0x426124 LDR X14, [X25, #72] |
(179) 0x426128 LDR D31, [X6, X26,LSL #3] |
(179) 0x42612c LDR X13, [X25, #64] |
(179) 0x426130 STR D31, [X14, X7,LSL #3] |
(179) 0x426134 LDR D30, [X23, X26,LSL #3] |
(179) 0x426138 LDR X7, [X25, #120] |
(179) 0x42613c STR D30, [X13, X5,LSL #3] |
(179) 0x426140 LDP X14, X23, [SP, #304] |
(179) 0x426144 LDR D28, [X7, X3] |
(179) 0x426148 MADD X6, X4, X27, X23 |
(179) 0x42614c MADD X4, X4, X28, X14 |
(179) 0x426150 LDR X5, [X25, #128] |
(179) 0x426154 ADD X23, X6, X0 |
(179) 0x426158 ADD X13, X6, X1 |
(179) 0x42615c LDR X6, [X25, #80] |
(179) 0x426160 ADD X14, X0, X4 |
(179) 0x426164 ADD X4, X1, X4 |
(179) 0x426168 STR X4, [SP, #112] |
(179) 0x42616c ADD X4, X0, X11 |
(179) 0x426170 STR D28, [X6, X4,LSL #3] |
(179) 0x426174 LDR D29, [X5, X3] |
(179) 0x426178 LDR X4, [X25, #88] |
(179) 0x42617c STR D29, [X4, X9,LSL #3] |
(179) 0x426180 ADD X9, X1, X11 |
(179) 0x426184 LDR D6, [X7, X3] |
(179) 0x426188 STR D6, [X6, X9,LSL #3] |
(179) 0x42618c ADD X9, X1, X21 |
(179) 0x426190 LDR D7, [X5, X3] |
(179) 0x426194 STR D7, [X4, X9,LSL #3] |
(179) 0x426198 LDR D5, [X7, X3] |
(179) 0x42619c STR D5, [X6, X23,LSL #3] |
(179) 0x4261a0 LDR D4, [X5, X3] |
(179) 0x4261a4 STR D4, [X4, X14,LSL #3] |
(179) 0x4261a8 LDR D3, [X7, X3] |
(179) 0x4261ac STR D3, [X6, X13,LSL #3] |
(179) 0x4261b0 LDR D2, [X5, X3] |
(179) 0x4261b4 LDR X3, [SP, #112] |
(179) 0x4261b8 STR D2, [X4, X3,LSL #3] |
(179) 0x4261bc B 425f44 |
0x4261c0 STR W8, [SP, #168] |
0x4261c4 LDR W7, [SP, #168] |
0x4261c8 STR W7, [X25, #320] |
0x4261cc B 4257b0 |
0x4261d0 STR W16, [SP, #112] |
0x4261d4 LDR W10, [SP, #112] |
0x4261d8 STR W10, [X25, #320] |
0x4261dc B 42586c |
0x4261e0 ORR W23, WZR, W16 |
0x4261e4 STR W23, [X25, #320] |
0x4261e8 B 425924 |
0x4261ec ORR W22, WZR, W16 |
0x4261f0 STR W22, [X25, #320] |
0x4261f4 B 4259dc |
(178) 0x4261f8 LDR X2, [SP, #272] |
(178) 0x4261fc LDR D28, [X16, X0,LSL #3] |
(178) 0x426200 LDR D29, [X2, X26,LSL #3] |
(178) 0x426204 FCMPE D28, D29 |
(178) 0x426208 B.MI 426210 |
(178) 0x42620c B 425f04 |
(178) 0x426210 LDR X9, [X25, #40] |
(178) 0x426214 LDR X13, [SP, #264] |
(178) 0x426218 LDR D6, [X9, X18,LSL #3] |
(178) 0x42621c LDR D7, [X13, X26,LSL #3] |
(178) 0x426220 FCMPE D6, D7 |
(178) 0x426224 B.GE 426430 |
(178) 0x426228 B 425f04 |
0x42622c CNTD X30, ALL |
0x426230 SUB W3, W0, W1 |
0x426234 PTRUE P5.B, ALL |
0x426238 WHILELO P8.D, XZR, X3 |
0x42623c HINT #0 |
(185) 0x426240 MOVZ X17, #0 |
(185) 0x426244 ORR P4.B, P8/Z, P8.B, P8.B |
(184) 0x426248 LD1RD {Z28.D}, P5/Z, [X4] |
(184) 0x42624c ST1D {Z28.D}, P4, [X2, X17,LSL #3] |
(184) 0x426250 ADD X17, X17, X30 |
(184) 0x426254 WHILELO P4.D, X17, X3 |
(184) 0x426258 B.NE 426248 |
(185) 0x42625c ADD W6, W6, #1 |
(185) 0x426260 ADD X2, X2, X11 |
(185) 0x426264 CMP W12, W9 |
(185) 0x426268 B.GE 42627c |
(185) 0x42626c CMP W7, W6 |
(185) 0x426270 B.GT 426240 |
0x426274 CBZ W10, 4259dc |
0x426278 B 4261f0 |
(185) 0x42627c CMP W7, W6 |
(185) 0x426280 B.LE 4261ec |
(185) 0x426284 ORR W22, WZR, W16 |
(185) 0x426288 MOVZ W10, #1 |
(185) 0x42628c B 426240 |
0x426290 CNTD X13, ALL |
0x426294 SUB W12, W3, W5 |
0x426298 PTRUE P2.B, ALL |
0x42629c WHILELO P3.D, XZR, X12 |
(188) 0x4262a0 MOVZ X17, #0 |
(188) 0x4262a4 ORR P1.B, P3/Z, P3.B, P3.B |
(187) 0x4262a8 LD1RD {Z29.D}, P2/Z, [X4] |
(187) 0x4262ac ST1D {Z29.D}, P1, [X30, X17,LSL #3] |
(187) 0x4262b0 ADD X17, X17, X13 |
(187) 0x4262b4 WHILELO P1.D, X17, X12 |
(187) 0x4262b8 B.NE 4262a8 |
(188) 0x4262bc ADD W6, W6, #1 |
(188) 0x4262c0 ADD X30, X30, X11 |
(188) 0x4262c4 CMP W14, W9 |
(188) 0x4262c8 B.GE 4262dc |
(188) 0x4262cc CMP W7, W6 |
(188) 0x4262d0 B.GT 4262a0 |
0x4262d4 CBZ W10, 425924 |
0x4262d8 B 4261e4 |
(188) 0x4262dc CMP W7, W6 |
(188) 0x4262e0 B.LE 4261e0 |
(188) 0x4262e4 ORR W23, WZR, W16 |
(188) 0x4262e8 MOVZ W10, #1 |
(188) 0x4262ec B 4262a0 |
0x4262f0 CNTD X5, ALL |
0x4262f4 SUB W3, W13, W26 |
0x4262f8 PTRUE P0.B, ALL |
0x4262fc WHILELO P9.D, XZR, X3 |
(194) 0x426300 MOVZ X14, #0 |
(194) 0x426304 ORR P7.B, P9/Z, P9.B, P9.B |
(193) 0x426308 LD1RD {Z31.D}, P0/Z, [X2] |
(193) 0x42630c ST1D {Z31.D}, P7, [X15, X14,LSL #3] |
(193) 0x426310 ADD X14, X14, X5 |
(193) 0x426314 WHILELO P7.D, X14, X3 |
(193) 0x426318 B.NE 426308 |
(194) 0x42631c ADD W6, W6, #1 |
(194) 0x426320 ADD X15, X15, X11 |
(194) 0x426324 CMP W17, W4 |
(194) 0x426328 B.LE 42633c |
(194) 0x42632c CMP W7, W6 |
(194) 0x426330 B.GT 426300 |
0x426334 CBZ W9, 4257b0 |
0x426338 B 4261c4 |
(194) 0x42633c CMP W7, W6 |
(194) 0x426340 B.LE 4261c0 |
(194) 0x426344 MOVZ W9, #1 |
(194) 0x426348 STR W8, [SP, #168] |
(194) 0x42634c B 426300 |
0x426350 CNTD X5, ALL |
0x426354 SUB W12, W3, W14 |
0x426358 PTRUE P6.B, ALL |
0x42635c WHILELO P15.D, XZR, X12 |
(191) 0x426360 MOVZ X17, #0 |
(191) 0x426364 ORR P0.B, P15/Z, P15.B, P15.B |
(190) 0x426368 LD1RD {Z30.D}, P6/Z, [X13] |
(190) 0x42636c ST1D {Z30.D}, P0, [X30, X17,LSL #3] |
(190) 0x426370 ADD X17, X17, X5 |
(190) 0x426374 WHILELO P0.D, X17, X12 |
(190) 0x426378 B.NE 426368 |
(191) 0x42637c ADD W6, W6, #1 |
(191) 0x426380 ADD X30, X30, X11 |
(191) 0x426384 CMP W9, W8 |
(191) 0x426388 B.LE 42639c |
(191) 0x42638c CMP W7, W6 |
(191) 0x426390 B.GT 426360 |
0x426394 CBZ W10, 42586c |
0x426398 B 4261d4 |
(191) 0x42639c CMP W7, W6 |
(191) 0x4263a0 B.LE 4261d0 |
(191) 0x4263a4 MOVZ W10, #1 |
(191) 0x4263a8 STR W16, [SP, #112] |
(191) 0x4263ac B 426360 |
0x4263b0 ADD W12, W12, #1 |
0x4263b4 MOVZ W13, #0 |
0x4263b8 B 425728 |
0x4263bc ADD W3, W3, #1 |
0x4263c0 MOVZ W4, #0 |
0x4263c4 B 4257e4 |
0x4263c8 ADD W2, W2, #1 |
0x4263cc MOVZ W0, #0 |
0x4263d0 B 425958 |
0x4263d4 ADD W3, W3, #1 |
0x4263d8 MOVZ W6, #0 |
0x4263dc B 4258a0 |
(186) 0x4263e0 CMP W7, W6 |
(186) 0x4263e4 B.LE 4261ec |
(186) 0x4263e8 ORR W22, WZR, W16 |
(186) 0x4263ec MOVZ W10, #1 |
(186) 0x4263f0 B 4259bc |
(192) 0x4263f4 CMP W7, W6 |
(192) 0x4263f8 B.LE 4261d0 |
(192) 0x4263fc MOVZ W10, #1 |
(192) 0x426400 STR W16, [SP, #112] |
(192) 0x426404 B 42584c |
(189) 0x426408 CMP W7, W6 |
(189) 0x42640c B.LE 4261e0 |
(189) 0x426410 ORR W23, WZR, W16 |
(189) 0x426414 MOVZ W10, #1 |
(189) 0x426418 B 425904 |
(195) 0x42641c CMP W7, W6 |
(195) 0x426420 B.LE 4261c0 |
(195) 0x426424 MOVZ W9, #1 |
(195) 0x426428 STR W8, [SP, #168] |
(195) 0x42642c B 425790 |
(178) 0x426430 LDR X23, [X25, #160] |
(178) 0x426434 LDR D5, [X9, X15,LSL #3] |
(178) 0x426438 LDR D4, [X23, X26,LSL #3] |
(178) 0x42643c FCMPE D5, D4 |
(178) 0x426440 B.MI 4264fc |
(178) 0x426444 B 425f04 |
(178) 0x426448 LDP X23, X4, [X25, #104] |
(178) 0x42644c ADD X13, X0, X8 |
(178) 0x426450 SBFM X7, X24, #0, #31 |
(178) 0x426454 UBFM X3, X26, #61, #31 |
(178) 0x426458 ADD X5, X0, X22 |
(178) 0x42645c ADD X14, X0, X11 |
(178) 0x426460 LDR X9, [X25, #72] |
(178) 0x426464 LDR D16, [X4, X26,LSL #3] |
(178) 0x426468 LDR X6, [X25, #120] |
(178) 0x42646c STR D16, [X9, X13,LSL #3] |
(178) 0x426470 LDP X13, X9, [SP, #304] |
(178) 0x426474 LDR D17, [X23, X26,LSL #3] |
(178) 0x426478 MADD X4, X7, X27, X9 |
(178) 0x42647c LDR X23, [X25, #64] |
(178) 0x426480 MADD X7, X7, X28, X13 |
(178) 0x426484 ADD X9, X4, X0 |
(178) 0x426488 ADD X13, X4, X1 |
(178) 0x42648c LDR X4, [X25, #128] |
(178) 0x426490 STR D17, [X23, X5,LSL #3] |
(178) 0x426494 ADD X23, X0, X7 |
(178) 0x426498 ADD X7, X1, X7 |
(178) 0x42649c LDR D18, [X6, X3] |
(178) 0x4264a0 STR X7, [SP, #112] |
(178) 0x4264a4 ADD X7, X0, X21 |
(178) 0x4264a8 LDR X5, [X25, #80] |
(178) 0x4264ac STR D18, [X5, X14,LSL #3] |
(178) 0x4264b0 LDR D19, [X4, X3] |
(178) 0x4264b4 LDR X14, [X25, #88] |
(178) 0x4264b8 STR D19, [X14, X7,LSL #3] |
(178) 0x4264bc ADD X7, X1, X11 |
(178) 0x4264c0 LDR D20, [X6, X3] |
(178) 0x4264c4 STR D20, [X5, X7,LSL #3] |
(178) 0x4264c8 ADD X7, X1, X21 |
(178) 0x4264cc LDR D21, [X4, X3] |
(178) 0x4264d0 STR D21, [X14, X7,LSL #3] |
(178) 0x4264d4 LDR D22, [X6, X3] |
(178) 0x4264d8 STR D22, [X5, X9,LSL #3] |
(178) 0x4264dc LDR D23, [X4, X3] |
(178) 0x4264e0 STR D23, [X14, X23,LSL #3] |
(178) 0x4264e4 LDR D24, [X6, X3] |
(178) 0x4264e8 STR D24, [X5, X13,LSL #3] |
(178) 0x4264ec LDR D25, [X4, X3] |
(178) 0x4264f0 LDR X3, [SP, #112] |
(178) 0x4264f4 STR D25, [X14, X3,LSL #3] |
(178) 0x4264f8 B 425edc |
(178) 0x4264fc LDP X9, X5, [X25, #104] |
(178) 0x426500 ADD X6, X0, X8 |
(178) 0x426504 ADD X4, X0, X22 |
(178) 0x426508 UBFM X2, X26, #61, #31 |
(178) 0x42650c SBFM X3, X24, #0, #31 |
(178) 0x426510 ADD X7, X0, X21 |
(178) 0x426514 LDR X14, [X25, #72] |
(178) 0x426518 LDR D3, [X5, X26,LSL #3] |
(178) 0x42651c LDR X13, [X25, #64] |
(178) 0x426520 LDR X5, [X25, #80] |
(178) 0x426524 STR D3, [X14, X6,LSL #3] |
(178) 0x426528 LDR D2, [X9, X26,LSL #3] |
(178) 0x42652c LDR X6, [X25, #120] |
(178) 0x426530 STR D2, [X13, X4,LSL #3] |
(178) 0x426534 LDP X23, X14, [SP, #304] |
(178) 0x426538 LDR D1, [X6, X2] |
(178) 0x42653c MADD X9, X3, X27, X14 |
(178) 0x426540 LDR X4, [X25, #128] |
(178) 0x426544 MADD X3, X3, X28, X23 |
(178) 0x426548 ADD X14, X9, X0 |
(178) 0x42654c ADD X23, X9, X1 |
(178) 0x426550 ADD X13, X1, X3 |
(178) 0x426554 ADD X9, X0, X3 |
(178) 0x426558 ADD X3, X0, X11 |
(178) 0x42655c STR D1, [X5, X3,LSL #3] |
(178) 0x426560 LDR D0, [X4, X2] |
(178) 0x426564 LDR X3, [X25, #88] |
(178) 0x426568 STR D0, [X3, X7,LSL #3] |
(178) 0x42656c ADD X7, X1, X11 |
(178) 0x426570 LDR D16, [X6, X2] |
(178) 0x426574 STR D16, [X5, X7,LSL #3] |
(178) 0x426578 ADD X7, X1, X21 |
(178) 0x42657c LDR D17, [X4, X2] |
(178) 0x426580 STR D17, [X3, X7,LSL #3] |
(178) 0x426584 LDR D18, [X6, X2] |
(178) 0x426588 STR D18, [X5, X14,LSL #3] |
(178) 0x42658c LDR D19, [X4, X2] |
(178) 0x426590 STR D19, [X3, X9,LSL #3] |
(178) 0x426594 LDR D20, [X6, X2] |
(178) 0x426598 STR D20, [X5, X23,LSL #3] |
(178) 0x42659c LDR D21, [X4, X2] |
(178) 0x4265a0 STR D21, [X3, X13,LSL #3] |
(178) 0x4265a4 B 425f04 |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.17+ | omp_fulfill_event | libgomp.so.1.0.0 | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 | |
| ►1.83+ | GOMP_parallel | libgomp.so.1.0.0 | |
| ○ | generate_chunk_kernel | generate_chunk_kernel.f90:174 | exec |
| ○ | generate_chunk | generate_chunk.f90:75 | exec |
| ○ | start | start.f90:104 | exec |
| ○ | initialise | initialise.f90:141 | exec |
| ○ | main | clover_leaf.f90:72 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | clover_leaf.f90:41 | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run gcc_0
| Source file and lines | generate_chunk_kernel.f90:85-161 |
| Module | exec |
| nb instructions | 272 |
| nb uops | 271 |
| loop length | 1088 |
| used w registers | 25 |
| used x registers | 32 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 1 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 48 |
| micro-operation queue | 33.88 cycles |
| front end | 33.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 18.50 | 18.50 | 35.75 | 35.75 | 35.75 | 35.75 | 0.00 | 0.00 | 0.00 | 0.00 | 32.83 | 32.50 | 32.67 | 15.50 | 15.50 |
| cycles | 18.50 | 18.50 | 35.75 | 35.75 | 35.75 | 35.75 | 0.00 | 0.00 | 0.00 | 0.00 | 32.83 | 32.50 | 32.67 | 15.50 | 15.50 |
| Cycles executing div or sqrt instructions | 20.00-50.00 |
| Front-end | 33.88 |
| Dispatch | 35.75 |
| DIV/SQRT | 20.00-50.00 |
| Overall L1 | 35.75-50.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 23% |
| load | 24% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 15% |
| fma | 17% |
| div/sqrt | 12% |
| other | 28% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STP X29, X30, [SP, #656]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ORR X25, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDR X0, [X0, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X20, X21, [X25, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDR X1, [X25, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X2, [X25, #232] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X3, [X25, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR X1, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X4, [X25, #248] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X2, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X5, [X25, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR X3, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X6, [X25, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X4, [SP, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X7, [X25, #296] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X5, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR W26, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| STR X6, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X19, [X25, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X7, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| BL 4103b0 <@plt_start@+0x390> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W0, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| SUB W26, W26, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 410330 <@plt_start@+0x310> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X8, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR W27, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| LDR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X24, [X25, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR W9, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X28, [X25, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| ADD W10, W9, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W11, W10, W26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SDIV W12, W11, W1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 5-12.50 | N/A |
| MSUB W13, W12, W1, W11 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| CMP W0, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LT 4263b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd30> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MADD W14, W12, W27, W13 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| ADD W15, W12, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W14, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.GE 4257b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X17, X18, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADD W6, W26, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W7, W26, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X16, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (100.0%) |
| MOVZ W9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X2, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR W12, [X18] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X0, [SP, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X11, X2, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR W26, [X17] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| ADD X3, X0, W26,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| MADD X4, X16, X2, X3 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| ADD W13, W12, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X30, [X25, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X5, X4, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W4, W12, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| LDR X2, [X25, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| SUB X8, X5, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W17, W26, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W17, W4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| ADD X15, X30, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CSEL W8, W17, W4, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBNZ W9, 4261c4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb44> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| BL 4103a0 <@plt_start@+0x380> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X9, X10, [X25, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W11, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| LDR W26, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUB W18, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W2, W26, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SUB W0, W2, W18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SDIV W3, W0, W1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 5-12.50 | N/A |
| MSUB W4, W3, W1, W0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| CMP W27, W4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LT 4263bc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd3c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MADD W16, W3, W27, W4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| ADD W17, W3, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W16, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.GE 42586c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X8, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD W6, W18, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W7, W18, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| LDP X5, X12, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| SBFM X30, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X13, [X25, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X11, X8, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X15, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W14, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X18, X15, W14,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| MADD X26, X30, X8, X18 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| LDR W4, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| UBFM X2, X26, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X0, X2, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X30, X13, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X13, [X25, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| SUB W9, W14, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W3, W4, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W8, W4, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSEL W16, W9, W8, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| CBNZ W10, 4261d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb54> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| BL 4103a0 <@plt_start@+0x380> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X14, X15, [X25, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W18, [X14] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W2, [X15] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUB W26, W18, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W0, W2, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W4, W0, W26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SDIV W3, W4, W1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 5-12.50 | N/A |
| MSUB W6, W3, W1, W4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| CMP W27, W6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LT 4263d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd54> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MADD W16, W3, W27, W6 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| ADD W17, W3, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W16, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.GE 425924 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X12, X13, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADD W6, W26, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W7, W26, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X30, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| UBFM X11, X24, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X14, [X25, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W8, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X15, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W5, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X18, X15, W5,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| MADD X26, X30, X24, X18 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| ADD W3, W8, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X4, [X25, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| UBFM X2, X26, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X0, X2, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W9, W5, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X30, X14, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W14, W8, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W14, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSEL W16, W14, W9, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| CBNZ W10, 4261e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb64> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| BL 4103a0 <@plt_start@+0x380> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X10, X1, [X25, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W23, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| LDR W8, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W15, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| SUB W5, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W18, W15, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W26, W18, W5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SDIV W2, W26, W23 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 5-12.50 | scal (12.5%) |
| MSUB W0, W2, W23, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| CMP W27, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LT 4263c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd48> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MADD W3, W2, W27, W0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| ADD W16, W2, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| CMP W3, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.GE 4259dc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X30, X12, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADD W6, W5, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W7, W5, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X17, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| UBFM X11, X28, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X13, [X25, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X8, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W14, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W1, [X30] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X5, X8, W1,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| MADD X15, X17, X28, X5 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| LDR X4, [X25, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| UBFM X18, X15, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W0, W14, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X26, X18, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD W12, W14, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X2, X13, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB W9, W1, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W12, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSEL W16, W12, W9, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| CBNZ W10, 4261f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb70> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W23, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| BL 4103a0 <@plt_start@+0x380> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X22, [X25, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W23, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| CMP W23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LE 425de0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x760> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X13, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X21, X21, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| UBFM X15, X19, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR W27, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ORR X27, XZR, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ORR W10, WZR, W23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MOVZ X26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR X10, [SP, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR W24, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUB X14, XZR, X13,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X1, X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR X15, [SP, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| SUB X5, X21, X8,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR X1, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| ADD X20, X14, X20,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X19, X14, X19,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR W24, [SP, #292] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| STR X5, [SP, #360] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| STP X19, X20, [SP, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| B 425a5c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3dc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X29, X30, [SP], #368 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W8, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR W7, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| STR W7, [X25, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 4257b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W16, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR W10, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR W10, [X25, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 42586c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR W23, WZR, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| STR W23, [X25, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 425924 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR W22, WZR, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR W22, [X25, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 4259dc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTD X30, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| SUB W3, W0, W1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| PTRUE P5.B, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| WHILELO P8.D, XZR, X3 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| CBZ W10, 4259dc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4261f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb70> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTD X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| SUB W12, W3, W5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| PTRUE P2.B, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| WHILELO P3.D, XZR, X12 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| CBZ W10, 425924 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4261e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb64> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTD X5, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| SUB W3, W13, W26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| PTRUE P0.B, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| WHILELO P9.D, XZR, X3 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| CBZ W9, 4257b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4261c4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb44> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTD X5, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| SUB W12, W3, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| PTRUE P6.B, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| WHILELO P15.D, XZR, X12 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| CBZ W10, 42586c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4261d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb54> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W13, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B 425728 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W3, W3, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W4, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| B 4257e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x164> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W2, W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| MOVZ W0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B 425958 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2d8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W3, W3, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W6, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| B 4258a0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run gcc_0
| Source file and lines | generate_chunk_kernel.f90:85-161 |
| Module | exec |
| nb instructions | 272 |
| nb uops | 271 |
| loop length | 1088 |
| used w registers | 25 |
| used x registers | 32 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 1 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 0 |
| nb stack references | 48 |
| micro-operation queue | 33.88 cycles |
| front end | 33.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 18.50 | 18.50 | 35.75 | 35.75 | 35.75 | 35.75 | 0.00 | 0.00 | 0.00 | 0.00 | 32.83 | 32.50 | 32.67 | 15.50 | 15.50 |
| cycles | 18.50 | 18.50 | 35.75 | 35.75 | 35.75 | 35.75 | 0.00 | 0.00 | 0.00 | 0.00 | 32.83 | 32.50 | 32.67 | 15.50 | 15.50 |
| Cycles executing div or sqrt instructions | 20.00-50.00 |
| Front-end | 33.88 |
| Dispatch | 35.75 |
| DIV/SQRT | 20.00-50.00 |
| Overall L1 | 35.75-50.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| all | 23% |
| load | 24% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 15% |
| fma | 17% |
| div/sqrt | 12% |
| other | 28% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STP X29, X30, [SP, #656]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| ORR X25, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| STP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| LDR X0, [X0, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDP X20, X21, [X25, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDR X1, [X25, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X2, [X25, #232] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR X3, [X25, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR X1, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X4, [X25, #248] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X2, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X5, [X25, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR X3, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X6, [X25, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X4, [SP, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X7, [X25, #296] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X5, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR W26, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| STR X6, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR X19, [X25, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| STR X7, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| BL 4103b0 <@plt_start@+0x390> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W0, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| SUB W26, W26, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| BL 410330 <@plt_start@+0x310> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X8, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR W27, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| LDR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X24, [X25, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR W9, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X28, [X25, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| ADD W10, W9, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W11, W10, W26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SDIV W12, W11, W1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 5-12.50 | N/A |
| MSUB W13, W12, W1, W11 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| CMP W0, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LT 4263b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd30> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MADD W14, W12, W27, W13 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| ADD W15, W12, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W14, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.GE 4257b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X17, X18, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADD W6, W26, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W7, W26, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X16, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (100.0%) |
| MOVZ W9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X2, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| LDR W12, [X18] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X0, [SP, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X11, X2, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR W26, [X17] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| ADD X3, X0, W26,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| MADD X4, X16, X2, X3 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| ADD W13, W12, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X30, [X25, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X5, X4, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W4, W12, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| LDR X2, [X25, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| SUB X8, X5, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W17, W26, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W17, W4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| ADD X15, X30, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CSEL W8, W17, W4, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CBNZ W9, 4261c4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb44> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| BL 4103a0 <@plt_start@+0x380> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X9, X10, [X25, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W11, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| LDR W26, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUB W18, W11, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W2, W26, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SUB W0, W2, W18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SDIV W3, W0, W1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 5-12.50 | N/A |
| MSUB W4, W3, W1, W0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| CMP W27, W4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LT 4263bc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd3c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MADD W16, W3, W27, W4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| ADD W17, W3, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W16, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.GE 42586c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X8, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD W6, W18, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W7, W18, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| LDP X5, X12, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| SBFM X30, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X13, [X25, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X11, X8, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X15, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W14, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X18, X15, W14,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| MADD X26, X30, X8, X18 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| LDR W4, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| UBFM X2, X26, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X0, X2, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X30, X13, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X13, [X25, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| SUB W9, W14, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W3, W4, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W8, W4, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSEL W16, W9, W8, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| CBNZ W10, 4261d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb54> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| BL 4103a0 <@plt_start@+0x380> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X14, X15, [X25, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W18, [X14] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W2, [X15] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUB W26, W18, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W0, W2, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W4, W0, W26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SDIV W3, W4, W1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 5-12.50 | N/A |
| MSUB W6, W3, W1, W4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| CMP W27, W6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LT 4263d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd54> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MADD W16, W3, W27, W6 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| ADD W17, W3, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W16, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.GE 425924 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X12, X13, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADD W6, W26, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W7, W26, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X30, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| UBFM X11, X24, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X14, [X25, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W8, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X15, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W5, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X18, X15, W5,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| MADD X26, X30, X24, X18 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| ADD W3, W8, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X4, [X25, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| UBFM X2, X26, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB X0, X2, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W9, W5, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X30, X14, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W14, W8, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W14, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSEL W16, W14, W9, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| CBNZ W10, 4261e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb64> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W1, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| BL 4103a0 <@plt_start@+0x380> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X10, X1, [X25, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDR W23, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| LDR W8, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W15, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| SUB W5, W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W18, W15, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB W26, W18, W5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SDIV W2, W26, W23 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 5-12.50 | scal (12.5%) |
| MSUB W0, W2, W23, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| CMP W27, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LT 4263c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd48> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| MADD W3, W2, W27, W0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| ADD W16, W2, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| CMP W3, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.GE 4259dc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X30, X12, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| ADD W6, W5, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD W7, W5, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SBFM X17, X6, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| UBFM X11, X28, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| LDR X13, [X25, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR X8, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W14, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W1, [X30] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ADD X5, X8, W1,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| MADD X15, X17, X28, X5 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| LDR X4, [X25, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (25.0%) |
| UBFM X18, X15, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W0, W14, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X26, X18, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD W12, W14, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X2, X13, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| SUB W9, W1, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W12, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| CSEL W16, W12, W9, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| CBNZ W10, 4261f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb70> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W23, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| BL 4103a0 <@plt_start@+0x380> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X22, [X25, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| LDR W23, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| CMP W23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LE 425de0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x760> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR X13, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| UBFM X21, X21, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| UBFM X15, X19, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR W27, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| ORR X27, XZR, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ORR W10, WZR, W23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MOVZ X26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR X10, [SP, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| LDR W24, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| SUB X14, XZR, X13,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X1, X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR X15, [SP, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| SUB X5, X21, X8,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR X1, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| ADD X20, X14, X20,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD X19, X14, X19,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| STR W24, [SP, #292] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| STR X5, [SP, #360] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (25.0%) |
| STP X19, X20, [SP, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (50.0%) |
| B 425a5c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3dc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| LDP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | scal (50.0%) |
| LDP X29, X30, [SP], #368 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W8, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR W7, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | scal (12.5%) |
| STR W7, [X25, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 4257b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| STR W16, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| LDR W10, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| STR W10, [X25, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 42586c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR W23, WZR, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| STR W23, [X25, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 425924 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ORR W22, WZR, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| STR W22, [X25, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| B 4259dc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTD X30, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| SUB W3, W0, W1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| PTRUE P5.B, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| WHILELO P8.D, XZR, X3 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| HINT #0 | N/A | ||||||||||||||||||
| CBZ W10, 4259dc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4261f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb70> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTD X13, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| SUB W12, W3, W5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| PTRUE P2.B, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| WHILELO P3.D, XZR, X12 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| CBZ W10, 425924 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4261e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb64> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTD X5, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| SUB W3, W13, W26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| PTRUE P0.B, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| WHILELO P9.D, XZR, X3 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| CBZ W9, 4257b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4261c4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb44> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| CNTD X5, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| SUB W12, W3, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| PTRUE P6.B, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (100.0%) |
| WHILELO P15.D, XZR, X12 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| CBZ W10, 42586c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 4261d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb54> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W13, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B 425728 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W3, W3, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W4, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| B 4257e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x164> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W2, W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| MOVZ W0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B 425958 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2d8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W3, W3, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| MOVZ W6, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| B 4258a0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0– | 0.03 | 0.04 |
| ▼Loop 194 - generate_chunk_kernel.f90:90-90 - exec– | 0.00 | 0.00 |
| ○Loop 193 - generate_chunk_kernel.f90:90-90 - exec | 0.00 | 0.00 |
| ▼Loop 185 - generate_chunk_kernel.f90:114-114 - exec– | 0.00 | 0.00 |
| ○Loop 184 - generate_chunk_kernel.f90:114-114 - exec | 0.00 | 0.00 |
| ○Loop 192 - generate_chunk_kernel.f90:96-114 - exec | 0.00 | 0.00 |
| ○Loop 195 - generate_chunk_kernel.f90:88-106 - exec | 0.00 | 0.00 |
| ▼Loop 188 - generate_chunk_kernel.f90:106-106 - exec– | 0.00 | 0.00 |
| ○Loop 187 - generate_chunk_kernel.f90:106-106 - exec | 0.00 | 0.00 |
| ▼Loop 177 - generate_chunk_kernel.f90:119-161 - exec– | 0.00 | 0.00 |
| ○Loop 182 - generate_chunk_kernel.f90:130-130 - exec | 0.00 | 0.00 |
| ○Loop 183 - generate_chunk_kernel.f90:130-154 - exec | 0.00 | 0.00 |
| ▼Loop 178 - generate_chunk_kernel.f90:129-150 - exec– | 0.00 | 0.00 |
| ○Loop 179 - generate_chunk_kernel.f90:130-137 - exec | 0.00 | 0.02 |
| ▼Loop 180 - generate_chunk_kernel.f90:129-161 - exec– | 0.00 | 0.00 |
| ○Loop 181 - generate_chunk_kernel.f90:142-161 - exec | 0.00 | 0.00 |
| ○Loop 186 - generate_chunk_kernel.f90:102-114 - exec | 0.00 | 0.00 |
| ○Loop 189 - generate_chunk_kernel.f90:98-106 - exec | 0.00 | 0.00 |
| ▼Loop 191 - generate_chunk_kernel.f90:98-98 - exec– | 0.00 | 0.00 |
| ○Loop 190 - generate_chunk_kernel.f90:98-98 - exec | 0.00 | 0.00 |