OV - exec - Function __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp

	Function: __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0	Module: exec	Source: ideal_gas_kernel.f90:45-55	Coverage (incl. loops): 4.33% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 45 - 55

--------------------------------------------------------------------------------

45:     !$OMP PARALLEL

46:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

47:     DO k=y_min,y_max

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

0x427020 STP	X29, X30, [SP, #976]!

0x427024 ADD	X29, SP, #0

0x427028 STP	X19, X20, [SP, #16]

0x42702c ORR	X20, XZR, X0

0x427030 STP	X21, X22, [SP, #32]

0x427034 LDR	X0, [X0, #16]

0x427038 LDR	W22, [X0]

0x42703c BL	4103b0

0x427040 ORR	W21, WZR, W0

0x427044 BL	410330

0x427048 LDR	X1, [X20, #24]

0x42704c ORR	W8, WZR, W0

0x427050 LDR	W2, [X1]

0x427054 ADD	W3, W2, #1

0x427058 SUB	W4, W3, W22

0x42705c SDIV	W5, W4, W21

0x427060 MSUB	W6, W5, W21, W4

0x427064 CMP	W0, W6

0x427068 B.LT	4271b4

0x42706c MADD	W7, W5, W8, W6

0x427070 ADD	W9, W5, W7

0x427074 CMP	W7, W9

0x427078 B.GE	4271a4

0x42707c LDP	X18, X30, [X20]

0x427080 ADD	W8, W22, W7

0x427084 ADD	W0, W22, W9

0x427088 SBFM	X17, X8, #0, #31

0x42708c LDP	X11, X22, [X20, #64]

0x427090 LDP	X16, X15, [X20, #32]

0x427094 LDP	X10, X21, [X20, #80]

0x427098 LDP	X12, X1, [X20, #96]

0x42709c LDP	X13, X5, [X20, #112]

0x4270a0 LDR	W7, [X18]

0x4270a4 LDR	W30, [X30]

0x4270a8 LDR	X14, [X20, #48]

0x4270ac SBFM	X2, X7, #0, #31

0x4270b0 ADD	X3, X2, X22

0x4270b4 ADD	X6, X2, X21

0x4270b8 ADD	X4, X2, X1

0x4270bc ADD	X9, X2, X5

0x4270c0 MADD	X18, X17, X11, X3

0x4270c4 CMP	W7, W30

0x4270c8 UBFM	X11, X11, #61, #60

0x4270cc MADD	X22, X17, X10, X6

0x4270d0 UBFM	X10, X10, #61, #60

0x4270d4 MADD	X21, X17, X12, X4

0x4270d8 UBFM	X12, X12, #61, #60

0x4270dc ADD	X3, X16, X18,LSL #3

0x4270e0 LDR	X16, [X20, #56]

0x4270e4 MADD	X17, X17, X13, X9

0x4270e8 UBFM	X13, X13, #61, #60

0x4270ec ADD	X6, X15, X22,LSL #3

0x4270f0 ADD	W15, W30, #1

0x4270f4 ADD	X4, X14, X21,LSL #3

0x4270f8 CSINC	W14, W7, W30, #12

0x4270fc ADD	X2, X16, X17,LSL #3

0x427100 B.GT	4271c0

0x427104 CNTD	X9, ALL

0x427108 ADRP	X19,

0x42710c PTRUE	P6.B, ALL

0x427110 SUB	W5, W15, W7

0x427114 FDUP	Z31.D, #112

0x427118 ADD	X7, X19, #2080

0x42711c WHILELO	P15.D, XZR, X5

0x427120 LD1RD	{Z30.D}, P6/Z, [X7]

(209) 0x427124 MOVZ	X18, #0

(209) 0x427128 ORR	P7.B, P15/Z, P15.B, P15.B

  (208) 0x42712c LD1D	{Z29.D}, P7/Z, [X3, X18,LSL #3]

  (208) 0x427130 LD1D	{Z0.D}, P7/Z, [X6, X18,LSL #3]

  (208) 0x427134 MOVPRFX	Z28, Z31

  (208) 0x427138 FDIV	Z28.D, P7/M, Z28.D, Z29.D

  (208) 0x42713c FMUL	Z29.D, P7/M, Z29.D, Z30.D

  (208) 0x427140 MOVPRFX	Z24, Z28

  (208) 0x427144 FMUL	Z24.D, P7/M, Z24.D, Z28.D

  (208) 0x427148 FMUL	Z29.D, P7/M, Z29.D, Z0.D

  (208) 0x42714c ST1D	{Z29.D}, P7, [X4, X18,LSL #3]

  (208) 0x427150 LD1D	{Z26.D}, P7/Z, [X3, X18,LSL #3]

  (208) 0x427154 MOVPRFX	Z25, Z26

  (208) 0x427158 FMUL	Z25.D, P7/M, Z25.D, Z30.D

  (208) 0x42715c MOVPRFX	Z27, Z29

  (208) 0x427160 FMUL	Z27.D, P7/M, Z27.D, Z26.D

  (208) 0x427164 FMLA	Z27.D, P7/M, Z29.D, Z25.D

  (208) 0x427168 FMUL	Z24.D, P7/M, Z24.D, Z27.D

  (208) 0x42716c FSQRT	Z24.D, P6/M, Z24.D

  (208) 0x427170 ST1D	{Z24.D}, P7, [X2, X18,LSL #3]

  (208) 0x427174 ADD	X18, X18, X9

  (208) 0x427178 WHILELO	P7.D, X18, X5

  (208) 0x42717c B.NE	42712c

(209) 0x427180 ADD	W8, W8, #1

(209) 0x427184 ADD	X3, X3, X11

(209) 0x427188 ADD	X6, X6, X10

(209) 0x42718c ADD	X4, X4, X12

(209) 0x427190 ADD	X2, X2, X13

(209) 0x427194 CMP	W0, W8

(209) 0x427198 B.GT	427124

0x42719c ORR	W19, WZR, W14

0x4271a0 STR	W19, [X20, #128]

0x4271a4 LDP	X19, X20, [SP, #16]

0x4271a8 LDP	X21, X22, [SP, #32]

0x4271ac LDP	X29, X30, [SP], #48

0x4271b0 RET

0x4271b4 ADD	W5, W5, #1

0x4271b8 MOVZ	W6, #0

0x4271bc B	42706c

0x4271c0 MOVZ	W1, #0

(207) 0x4271c4 ADD	W8, W8, #1

(207) 0x4271c8 CMP	W15, W14

(207) 0x4271cc B.EQ	4271ec

(207) 0x4271d0 CMP	W0, W8

(207) 0x4271d4 B.GT	4271c4

0x4271d8 CBNZ	W1, 4271a0

0x4271dc LDP	X19, X20, [SP, #16]

0x4271e0 LDP	X21, X22, [SP, #32]

0x4271e4 LDP	X29, X30, [SP], #48

0x4271e8 RET

(207) 0x4271ec CMP	W0, W8

(207) 0x4271f0 B.LE	42719c

(207) 0x4271f4 ORR	W19, WZR, W15

(207) 0x4271f8 MOVZ	W1, #1

(207) 0x4271fc B	4271c4

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 11.75 cycles (1.06x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	80
nb uops	80
loop length	320
used w registers	17
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	2
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.00 cycles
front end	10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	12.00	12.00	12.00	12.00	0.50	0.50	0.00	0.00	8.50	8.17	8.33	2.00	2.00
cycles	4.50	4.50	12.00	12.00	12.00	12.00	0.50	0.50	0.00	0.00	8.50	8.17	8.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	10.00
Dispatch	12.00
DIV/SQRT	5.00-12.50
Overall L1	12.00-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	35%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	21%
other	32%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	28%
load	35%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (0.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 427020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W22, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W5, W4, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W6, W5, W21, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4271b4 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W7, W5, W8, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W9, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4271a4 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X18, X30, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W8, W22, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X17, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDP X11, X22, [X20, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X16, X15, [X20, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X21, [X20, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X1, [X20, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X5, [X20, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W7, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W30, [X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X2, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X3, X2, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X2, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X2, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X18, X17, X11, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP W7, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X22, X17, X10, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X21, X17, X12, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X16, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X20, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X17, X17, X13, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X13, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X15, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W15, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X4, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W14, W7, W30, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X2, X16, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GT 4271c0 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X19, <464108>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB W5, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z31.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
ADD X7, X19, #2080	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LD1RD {Z30.D}, P6/Z, [X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W19, [X20, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42706c <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CBNZ W1, 4271a0 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 11.75 cycles (1.06x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	80
nb uops	80
loop length	320
used w registers	17
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	2
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.00 cycles
front end	10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	12.00	12.00	12.00	12.00	0.50	0.50	0.00	0.00	8.50	8.17	8.33	2.00	2.00
cycles	4.50	4.50	12.00	12.00	12.00	12.00	0.50	0.50	0.00	0.00	8.50	8.17	8.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	10.00
Dispatch	12.00
DIV/SQRT	5.00-12.50
Overall L1	12.00-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	35%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	21%
other	32%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	28%
load	35%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (0.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 427020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W22, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W5, W4, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W6, W5, W21, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4271b4 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W7, W5, W8, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W9, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4271a4 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X18, X30, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W8, W22, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X17, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDP X11, X22, [X20, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X16, X15, [X20, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X21, [X20, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X1, [X20, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X5, [X20, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W7, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W30, [X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X2, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X3, X2, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X2, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X2, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X18, X17, X11, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP W7, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X22, X17, X10, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X21, X17, X12, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X16, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X20, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X17, X17, X13, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X13, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X15, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W15, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X4, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W14, W7, W30, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X2, X16, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GT 4271c0 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X19, <464108>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB W5, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z31.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
ADD X7, X19, #2080	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LD1RD {Z30.D}, P6/Z, [X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W19, [X20, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42706c <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CBNZ W1, 4271a0 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0–	4.33	5.74
▼Loop 209 - ideal_gas_kernel.f90:48-55 - exec–	0.00	0.02
○Loop 208 - ideal_gas_kernel.f90:50-55 - exec	4.32	5.70
○Loop 207 - ideal_gas_kernel.f90:45-48 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code