OV - exec - Function __initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp

	Function: __initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0	Module: exec	Source: initialise_chunk_kernel.f90:58-129	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90: 58 - 129

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58:     !$OMP PARALLEL

59:     !$OMP DO

60:     DO j=x_min-2,x_max+3

61:       vertexx(j)=xmin+dx*float(j-x_min)

62:     ENDDO

63:     !$OMP END DO

64:

65:     !$OMP DO

66:     DO j=x_min-2,x_max+3

67:       vertexdx(j)=dx

68:     ENDDO

69:     !$OMP END DO

70:

71:     !$OMP DO

72:     DO k=y_min-2,y_max+3

73:       vertexy(k)=ymin+dy*float(k-y_min)

74:     ENDDO

75:     !$OMP END DO

76:

77:     !$OMP DO

78:     DO k=y_min-2,y_max+3

79:       vertexdy(k)=dy

80:     ENDDO

81:     !$OMP END DO

82:

83:     !$OMP DO

84:     DO j=x_min-2,x_max+2

85:       cellx(j)=0.5*(vertexx(j)+vertexx(j+1))

86:     ENDDO

87:     !$OMP END DO

88:

89:     !$OMP DO

90:     DO j=x_min-2,x_max+2

91:       celldx(j)=dx

92:     ENDDO

93:     !$OMP END DO

94:

95:     !$OMP DO

96:     DO k=y_min-2,y_max+2

97:       celly(k)=0.5*(vertexy(k)+vertexy(k+1))

98:     ENDDO

99:     !$OMP END DO

100:

101:     !$OMP DO

102:     DO k=y_min-2,y_max+2

103:       celldy(k)=dy

104:     ENDDO

105:     !$OMP END DO

106:

107:     !$OMP DO PRIVATE(j)

108:     DO k=y_min-2,y_max+2

109:     !$OMP SIMD

110:       DO j=x_min-2,x_max+2

111:         volume(j,k)=dx*dy

112:       ENDDO

113:     ENDDO

114:     !$OMP END DO

115:

116:     !$OMP DO PRIVATE(j)

117:     DO k=y_min-2,y_max+2

118:     !$OMP SIMD

119:       DO j=x_min-2,x_max+2

120:         xarea(j,k)=celldy(k)

121:       ENDDO

122:     ENDDO

123:     !$OMP END DO

124:

125:     !$OMP DO PRIVATE(j)

126:     DO k=y_min-2,y_max+2

127:     !$OMP SIMD

128:       DO j=x_min-2,x_max+2

129:         yarea(j,k)=celldx(j)

0x427480 STP	X29, X30, [SP, #848]!

0x427484 ADD	X29, SP, #0

0x427488 STP	X25, X26, [SP, #64]

0x42748c ORR	X26, XZR, X0

0x427490 STP	X19, X20, [SP, #16]

0x427494 STP	X21, X22, [SP, #32]

0x427498 STP	X23, X24, [SP, #48]

0x42749c STP	X27, X28, [SP, #80]

0x4274a0 LDR	X0, [X0]

0x4274a4 LDP	X24, X1, [X26, #168]

0x4274a8 LDP	X22, X21, [X26, #152]

0x4274ac LDP	X20, X19, [X26, #200]

0x4274b0 STR	X1, [SP, #120]

0x4274b4 LDR	X2, [X26, #184]

0x4274b8 LDR	X3, [X26, #192]

0x4274bc LDR	X4, [X26, #216]

0x4274c0 STR	X2, [SP, #112]

0x4274c4 LDR	X5, [X26, #224]

0x4274c8 STR	X3, [SP, #104]

0x4274cc LDR	X6, [X26, #232]

0x4274d0 STR	X4, [SP, #168]

0x4274d4 LDR	X7, [X26, #240]

0x4274d8 STR	X5, [SP, #160]

0x4274dc LDR	X8, [X26, #248]

0x4274e0 STR	X6, [SP, #152]

0x4274e4 LDR	W27, [X0]

0x4274e8 STR	X7, [SP, #144]

0x4274ec STR	X8, [SP, #136]

0x4274f0 LDR	X9, [X26, #256]

0x4274f4 SUB	W23, W27, #2

0x4274f8 STR	X9, [SP, #128]

0x4274fc BL	4103b0

0x427500 ORR	W28, WZR, W0

0x427504 BL	410330

0x427508 LDR	X10, [X26, #8]

0x42750c ORR	W25, WZR, W0

0x427510 LDR	W11, [X10]

0x427514 ADD	W12, W11, #4

0x427518 SUB	W13, W12, W23

0x42751c SDIV	W14, W13, W28

0x427520 MSUB	W15, W14, W28, W13

0x427524 CMP	W0, W15

0x427528 B.LT	427fcc

0x42752c MUL	W16, W14, W25

0x427530 ADD	W17, W15, W16

0x427534 ADD	W18, W14, W17

0x427538 CMP	W17, W18

0x42753c B.GE	427614

0x427540 LDR	X10, [X26, #32]

0x427544 SBFM	X30, X16, #0, #31

0x427548 ADD	X0, X20, W27,SXTW

0x42754c ADD	X1, X30, W15,SXTW

0x427550 ADD	X2, X0, X1

0x427554 ORR	W5, WZR, W14

0x427558 LDR	X9, [X26, #64]

0x42755c UBFM	X3, X2, #61, #60

0x427560 ADD	W4, W23, W17

0x427564 SUB	X6, X3, #16

0x427568 ADD	X7, X6, W14,UXTW #3

0x42756c LDR	X12, [X26, #48]

0x427570 ADD	X11, X10, #8

0x427574 ADD	X15, X9, X6

0x427578 ADD	X8, X9, X7

0x42757c CMP	X11, X15

0x427580 CCMP	X10, X8, #2, #8

0x427584 ADD	X14, X12, #8

0x427588 CSINC	W13, WZR, WZR, #3

0x42758c CMP	X15, X14

0x427590 CCMP	X12, X8, #2, #3

0x427594 CSINC	W16, WZR, WZR, #3

0x427598 ANDS	WZR, W13, W16

0x42759c B.EQ	428b38

0x4275a0 MOVZ	X30, #0

0x4275a4 ADDVL	X23, X15, #1

0x4275a8 PTRUE	P5.B, ALL

0x4275ac CNTW	X17, ALL

0x4275b0 ORR	X18, XZR, X5

0x4275b4 INDEX	Z31.S, W4, #1

0x4275b8 UQDECD	X18, ALL

0x4275bc LD1RD	{Z30.D}, P5/Z, [X10]

0x4275c0 LD1RD	{Z29.D}, P5/Z, [X12]

0x4275c4 DUP	Z28.S, W27

0x4275c8 WHILELO	P6.D, XZR, X18

0x4275cc WHILELO	P7.D, XZR, X5

(237) 0x4275d0 SUB	Z1.S, Z31.S, Z28.S

(237) 0x4275d4 SCVTF	Z1.S, P5/M, Z1.S

(237) 0x4275d8 ZIP1	Z26.S, Z1.S, Z1.S

(237) 0x4275dc ZIP2	Z2.S, Z1.S, Z1.S

(237) 0x4275e0 FCVT	Z26.D, P5/M, Z26.S

(237) 0x4275e4 FCVT	Z2.D, P5/M, Z2.S

(237) 0x4275e8 MOVPRFX	Z27, Z30

(237) 0x4275ec FMLA	Z27.D, P6/M, Z29.D, Z26.D

(237) 0x4275f0 MOVPRFX	Z25, Z30

(237) 0x4275f4 FMLA	Z25.D, P7/M, Z29.D, Z2.D

(237) 0x4275f8 ST1D	{Z25.D}, P7, [X15, X30,LSL #3]

(237) 0x4275fc ST1D	{Z27.D}, P6, [X23, X30,LSL #3]

(237) 0x427600 ADD	X30, X30, X17

(237) 0x427604 WHILELO	P6.D, X30, X18

(237) 0x427608 INCW	Z31.S, ALL

(237) 0x42760c WHILELO	P7.D, X30, X5

(237) 0x427610 B.NE	4275d0

0x427614 BL	4103a0

0x427618 LDP	X10, X12, [X26]

0x42761c LDR	W1, [X10]

0x427620 LDR	W0, [X12]

0x427624 SUB	W4, W1, #2

0x427628 ADD	W6, W0, #4

0x42762c SUB	W3, W6, W4

0x427630 SDIV	W15, W3, W28

0x427634 MSUB	W9, W15, W28, W3

0x427638 CMP	W25, W9

0x42763c B.LT	428020

0x427640 MUL	W11, W15, W25

0x427644 ADD	W7, W9, W11

0x427648 ADD	W16, W15, W7

0x42764c CMP	W7, W16

0x427650 B.GE	427718

0x427654 LDR	X23, [X26, #72]

0x427658 SBFM	X8, X11, #0, #31

0x42765c ADD	X13, X8, W9,SXTW

0x427660 LDR	X14, [X26, #48]

0x427664 LDR	X17, [SP, #112]

0x427668 ADD	X18, X17, W1,SXTW

0x42766c ADD	X30, X18, X13

0x427670 UBFM	X27, X30, #61, #60

0x427674 SUB	X5, X27, #16

0x427678 ADD	X2, X5, W15,UXTW #3

0x42767c ADD	X10, X23, X2

0x427680 ADD	X1, X23, X5

0x427684 CMP	X14, X10

0x427688 ADD	X12, X14, #8

0x42768c CCMP	X12, X1, #0, #3

0x427690 B.HI	4283c4

0x427694 CNTW	X4, ALL

0x427698 SUB	W0, W15, #1

0x42769c SUB	W6, W4, #1

0x4276a0 MOVZ	W11, #0

0x4276a4 CMP	W0, W6

0x4276a8 B.CC	4276e0

0x4276ac SUB	W3, W15, W4

0x4276b0 CNTB	X9, ALL, MUL #2

0x4276b4 PTRUE	P0.B, ALL

0x4276b8 LD1RD	{Z5.D}, P0/Z, [X14]

0x4276bc HINT	#0

(235) 0x4276c0 ST1D	{Z5.D}, P0, [X1, #1, MUL VL]

(235) 0x4276c4 ADD	W11, W11, W4

(235) 0x4276c8 ST1D	{Z5.D}, P0, [X1, MUL VL]

(235) 0x4276cc ADD	X1, X1, X9

(235) 0x4276d0 CMP	W3, W11

(235) 0x4276d4 B.CS	4276c0

0x4276d8 CMP	W15, W11

0x4276dc B.EQ	427718

0x4276e0 ADD	X7, X18, W11,UXTW

0x4276e4 ADD	X16, X7, X13

0x4276e8 PTRUE	P1.B, ALL

0x4276ec ADD	X8, X23, X16,LSL #3

0x4276f0 LD1RD	{Z19.D}, P1/Z, [X14]

0x4276f4 MOVZ	X17, #0

0x4276f8 CNTD	X13, ALL

0x4276fc SUB	W15, W15, W11

0x427700 WHILELO	P2.D, XZR, X15

0x427704 SUB	X14, X8, #16

(234) 0x427708 ST1D	{Z19.D}, P2, [X14, X17,LSL #3]

(234) 0x42770c ADD	X17, X17, X13

(234) 0x427710 WHILELO	P2.D, X17, X15

(234) 0x427714 B.NE	427708

0x427718 BL	4103a0

0x42771c LDP	X7, X8, [X26, #16]

0x427720 LDR	W13, [X8]

0x427724 LDR	W18, [X7]

0x427728 ADD	W15, W13, #4

0x42772c SUB	W23, W18, #2

0x427730 SUB	W14, W15, W23

0x427734 SDIV	W27, W14, W28

0x427738 MSUB	W5, W27, W28, W14

0x42773c CMP	W25, W5

0x427740 B.LT	427fa8

0x427744 MUL	W16, W27, W25

0x427748 ADD	W17, W5, W16

0x42774c ADD	W30, W27, W17

0x427750 CMP	W17, W30

0x427754 B.GE	42782c

0x427758 LDR	X8, [X26, #40]

0x42775c SBFM	X10, X16, #0, #31

0x427760 ADD	X12, X19, W18,SXTW

0x427764 ADD	X2, X10, W5,SXTW

0x427768 ADD	X4, X12, X2

0x42776c ORR	W11, WZR, W27

0x427770 LDR	X1, [X26, #80]

0x427774 UBFM	X9, X4, #61, #60

0x427778 ADD	W0, W23, W17

0x42777c SUB	X6, X9, #16

0x427780 ADD	X3, X6, W27,UXTW #3

0x427784 LDR	X27, [X26, #56]

0x427788 ADD	X7, X8, #8

0x42778c ADD	X15, X1, X6

0x427790 ADD	X5, X1, X3

0x427794 CMP	X7, X15

0x427798 CCMP	X8, X5, #2, #8

0x42779c ADD	X14, X27, #8

0x4277a0 CSINC	W13, WZR, WZR, #3

0x4277a4 CMP	X15, X14

0x4277a8 CCMP	X27, X5, #2, #3

0x4277ac CSINC	W16, WZR, WZR, #3

0x4277b0 ANDS	WZR, W13, W16

0x4277b4 B.EQ	428158

0x4277b8 MOVZ	X10, #0

0x4277bc ADDVL	X23, X15, #1

0x4277c0 PTRUE	P3.B, ALL

0x4277c4 CNTW	X17, ALL

0x4277c8 ORR	X30, XZR, X11

0x4277cc INDEX	Z23.S, W0, #1

0x4277d0 UQDECD	X30, ALL

0x4277d4 LD1RD	{Z4.D}, P3/Z, [X8]

0x4277d8 LD1RD	{Z21.D}, P3/Z, [X27]

0x4277dc DUP	Z24.S, W18

0x4277e0 WHILELO	P4.D, XZR, X30

0x4277e4 WHILELO	P5.D, XZR, X11

(232) 0x4277e8 SUB	Z7.S, Z23.S, Z24.S

(232) 0x4277ec SCVTF	Z7.S, P3/M, Z7.S

(232) 0x4277f0 ZIP1	Z19.S, Z7.S, Z7.S

(232) 0x4277f4 ZIP2	Z5.S, Z7.S, Z7.S

(232) 0x4277f8 FCVT	Z19.D, P3/M, Z19.S

(232) 0x4277fc FCVT	Z5.D, P3/M, Z5.S

(232) 0x427800 MOVPRFX	Z20, Z4

(232) 0x427804 FMLA	Z20.D, P4/M, Z21.D, Z19.D

(232) 0x427808 MOVPRFX	Z6, Z4

(232) 0x42780c FMLA	Z6.D, P5/M, Z21.D, Z5.D

(232) 0x427810 ST1D	{Z6.D}, P5, [X15, X10,LSL #3]

(232) 0x427814 ST1D	{Z20.D}, P4, [X23, X10,LSL #3]

(232) 0x427818 ADD	X10, X10, X17

(232) 0x42781c WHILELO	P4.D, X10, X30

(232) 0x427820 INCW	Z23.S, ALL

(232) 0x427824 WHILELO	P5.D, X10, X11

(232) 0x427828 B.NE	4277e8

0x42782c BL	4103a0

0x427830 LDP	X8, X27, [X26, #16]

0x427834 LDR	W4, [X8]

0x427838 LDR	W12, [X27]

0x42783c SUB	W11, W4, #2

0x427840 ADD	W0, W12, #4

0x427844 SUB	W1, W0, W11

0x427848 SDIV	W7, W1, W28

0x42784c MSUB	W15, W7, W28, W1

0x427850 CMP	W25, W15

0x427854 B.LT	428014

0x427858 MUL	W6, W7, W25

0x42785c ADD	W5, W15, W6

0x427860 ADD	W16, W7, W5

0x427864 CMP	W5, W16

0x427868 B.GE	427938

0x42786c LDR	X23, [X26, #88]

0x427870 SBFM	X3, X6, #0, #31

0x427874 ADD	X13, X3, W15,SXTW

0x427878 LDR	X14, [X26, #56]

0x42787c LDR	X17, [SP, #104]

0x427880 ADD	X30, X17, W4,SXTW

0x427884 ADD	X10, X30, X13

0x427888 UBFM	X18, X10, #61, #60

0x42788c SUB	X9, X18, #16

0x427890 ADD	X2, X9, W7,UXTW #3

0x427894 ADD	X8, X23, X2

0x427898 ADD	X1, X23, X9

0x42789c CMP	X14, X8

0x4278a0 ADD	X27, X14, #8

0x4278a4 CCMP	X27, X1, #0, #3

0x4278a8 B.HI	42802c

0x4278ac CNTW	X4, ALL

0x4278b0 SUB	W12, W7, #1

0x4278b4 SUB	W11, W4, #1

0x4278b8 MOVZ	W5, #0

0x4278bc CMP	W12, W11

0x4278c0 B.CC	427900

0x4278c4 SUB	W0, W7, W4

0x4278c8 CNTB	X15, ALL, MUL #2

0x4278cc PTRUE	P6.B, ALL

0x4278d0 LD1RD	{Z1.D}, P6/Z, [X14]

0x4278d4 HINT	#0

0x4278d8 HINT	#0

0x4278dc HINT	#0

(230) 0x4278e0 ST1D	{Z1.D}, P6, [X1, #1, MUL VL]

(230) 0x4278e4 ADD	W5, W5, W4

(230) 0x4278e8 ST1D	{Z1.D}, P6, [X1, MUL VL]

(230) 0x4278ec ADD	X1, X1, X15

(230) 0x4278f0 CMP	W0, W5

(230) 0x4278f4 B.CS	4278e0

0x4278f8 CMP	W7, W5

0x4278fc B.EQ	427938

0x427900 ADD	X6, X30, W5,UXTW

0x427904 ADD	X16, X6, X13

0x427908 PTRUE	P0.B, ALL

0x42790c ADD	X3, X23, X16,LSL #3

0x427910 LD1RD	{Z26.D}, P0/Z, [X14]

0x427914 MOVZ	X17, #0

0x427918 CNTD	X13, ALL

0x42791c SUB	W7, W7, W5

0x427920 WHILELO	P7.D, XZR, X7

0x427924 SUB	X14, X3, #16

(229) 0x427928 ST1D	{Z26.D}, P7, [X14, X17,LSL #3]

(229) 0x42792c ADD	X17, X17, X13

(229) 0x427930 WHILELO	P7.D, X17, X7

(229) 0x427934 B.NE	427928

0x427938 BL	4103a0

0x42793c LDP	X6, X3, [X26]

0x427940 LDR	W13, [X6]

0x427944 LDR	W7, [X3]

0x427948 SUB	W23, W13, #2

0x42794c ADD	W14, W7, #3

0x427950 SUB	W10, W14, W23

0x427954 SDIV	W18, W10, W28

0x427958 MSUB	W9, W18, W28, W10

0x42795c CMP	W25, W9

0x427960 B.LT	427fe4

0x427964 MUL	W16, W18, W25

0x427968 ADD	W17, W9, W16

0x42796c ADD	W30, W18, W17

0x427970 CMP	W17, W30

0x427974 B.GE	427a20

0x427978 LDR	X14, [X26, #64]

0x42797c SBFM	X27, X13, #0, #31

0x427980 SBFM	X2, X9, #0, #31

0x427984 SBFM	X4, X16, #0, #31

0x427988 ADD	X8, X27, X24

0x42798c LDR	X7, [X26, #96]

0x427990 ADD	X12, X2, X4

0x427994 ADD	X11, X27, X20

0x427998 ADD	X0, X8, X12

0x42799c ADD	X15, X11, X12

0x4279a0 CNTB	X5, ALL

0x4279a4 ADD	X3, X14, X15,LSL #3

0x4279a8 SUB	X6, X5, #8

0x4279ac ADD	X1, X7, X0,LSL #3

0x4279b0 SUB	X13, X1, X3

0x4279b4 SUB	X10, X13, #8

0x4279b8 CMP	X10, X6

0x4279bc B.LS	428814

0x4279c0 ADD	X23, X27, X2

0x4279c4 MOVZ	X11, #0

0x4279c8 ADD	X16, X23, X4

0x4279cc CNTD	X9, ALL

0x4279d0 ADD	X20, X20, X16

0x4279d4 ADD	X24, X24, X16

0x4279d8 UBFM	X17, X20, #61, #60

0x4279dc ADD	X30, X7, X24,LSL #3

0x4279e0 ORR	W18, WZR, W18

0x4279e4 SUB	X27, X17, #16

0x4279e8 SUB	X4, X17, #8

0x4279ec WHILELO	P1.D, XZR, X18

0x4279f0 SUB	X2, X30, #16

0x4279f4 ADD	X8, X14, X27

0x4279f8 ADD	X12, X14, X4

0x4279fc HINT	#0

(227) 0x427a00 LD1D	{Z28.D}, P1/Z, [X8, X11,LSL #3]

(227) 0x427a04 LD1D	{Z30.D}, P1/Z, [X12, X11,LSL #3]

(227) 0x427a08 FADD	Z28.D, P1/M, Z28.D, Z30.D

(227) 0x427a0c FMUL	Z28.D, P1/M, Z28.D, #0.0000000

(227) 0x427a10 ST1D	{Z28.D}, P1, [X2, X11,LSL #3]

(227) 0x427a14 ADD	X11, X11, X9

(227) 0x427a18 WHILELO	P1.D, X11, X18

(227) 0x427a1c B.NE	427a00

0x427a20 BL	4103a0

0x427a24 LDP	X27, X4, [X26]

0x427a28 LDR	W0, [X27]

0x427a2c LDR	W2, [X4]

0x427a30 SUB	W11, W0, #2

0x427a34 ADD	W8, W2, #3

0x427a38 SUB	W12, W8, W11

0x427a3c SDIV	W15, W12, W28

0x427a40 MSUB	W5, W15, W28, W12

0x427a44 CMP	W25, W5

0x427a48 B.LT	427fc0

0x427a4c MUL	W30, W15, W25

0x427a50 ADD	W7, W5, W30

0x427a54 ADD	W23, W15, W7

0x427a58 CMP	W7, W23

0x427a5c B.GE	427b1c

0x427a60 LDR	X20, [X26, #104]

0x427a64 SBFM	X6, X30, #0, #31

0x427a68 ADD	X3, X22, W0,SXTW

0x427a6c ADD	X14, X6, W5,SXTW

0x427a70 ADD	X1, X3, X14

0x427a74 LDR	X9, [X26, #48]

0x427a78 UBFM	X18, X1, #61, #60

0x427a7c SUB	X16, X18, #16

0x427a80 ADD	X13, X16, W15,UXTW #3

0x427a84 ADD	X24, X20, X13

0x427a88 ADD	X8, X20, X16

0x427a8c CMP	X9, X24

0x427a90 ADD	X10, X9, #8

0x427a94 CCMP	X10, X8, #0, #3

0x427a98 B.HI	4286e8

0x427a9c CNTW	X17, ALL

0x427aa0 SUB	W27, W15, #1

0x427aa4 SUB	W4, W17, #1

0x427aa8 MOVZ	W2, #0

0x427aac CMP	W27, W4

0x427ab0 B.CC	427ae4

0x427ab4 SUB	W0, W15, W17

0x427ab8 CNTB	X11, ALL, MUL #2

0x427abc PTRUE	P2.B, ALL

0x427ac0 LD1RD	{Z3.D}, P2/Z, [X9]

(225) 0x427ac4 ST1D	{Z3.D}, P2, [X8, #1, MUL VL]

(225) 0x427ac8 ADD	W2, W2, W17

(225) 0x427acc ST1D	{Z3.D}, P2, [X8, MUL VL]

(225) 0x427ad0 ADD	X8, X8, X11

(225) 0x427ad4 CMP	W0, W2

(225) 0x427ad8 B.CS	427ac4

0x427adc CMP	W15, W2

0x427ae0 B.EQ	427b1c

0x427ae4 ADD	X12, X3, W2,UXTW

0x427ae8 ADD	X5, X12, X14

0x427aec MOVZ	X6, #0

0x427af0 ADD	X30, X20, X5,LSL #3

0x427af4 CNTD	X7, ALL

0x427af8 SUB	W15, W15, W2

0x427afc PTRUE	P3.B, ALL

0x427b00 WHILELO	P4.D, XZR, X15

0x427b04 LD1RD	{Z6.D}, P3/Z, [X9]

0x427b08 SUB	X23, X30, #16

(224) 0x427b0c ST1D	{Z6.D}, P4, [X23, X6,LSL #3]

(224) 0x427b10 ADD	X6, X6, X7

(224) 0x427b14 WHILELO	P4.D, X6, X15

(224) 0x427b18 B.NE	427b0c

0x427b1c BL	4103a0

0x427b20 LDP	X9, X8, [X26, #16]

0x427b24 LDR	W5, [X9]

0x427b28 LDR	W12, [X8]

0x427b2c SUB	W15, W5, #2

0x427b30 ADD	W7, W12, #3

0x427b34 SUB	W23, W7, W15

0x427b38 SDIV	W6, W23, W28

0x427b3c MSUB	W14, W6, W28, W23

0x427b40 CMP	W25, W14

0x427b44 B.LT	427fb4

0x427b48 MUL	W30, W6, W25

0x427b4c ADD	W18, W14, W30

0x427b50 ADD	W16, W6, W18

0x427b54 CMP	W18, W16

0x427b58 B.GE	427c04

0x427b5c LDR	X0, [SP, #120]

0x427b60 SBFM	X20, X5, #0, #31

0x427b64 SBFM	X3, X14, #0, #31

0x427b68 SBFM	X24, X30, #0, #31

0x427b6c ADD	X1, X20, X19

0x427b70 LDR	X17, [X26, #80]

0x427b74 ADD	X10, X3, X24

0x427b78 CNTB	X9, ALL

0x427b7c ADD	X13, X1, X10

0x427b80 SUB	X8, X9, #8

0x427b84 LDR	X27, [X26, #112]

0x427b88 ADD	X11, X20, X0

0x427b8c ADD	X2, X11, X10

0x427b90 ADD	X4, X17, X13,LSL #3

0x427b94 ADD	X5, X27, X2,LSL #3

0x427b98 SUB	X12, X5, X4

0x427b9c SUB	X7, X12, #8

0x427ba0 CMP	X7, X8

0x427ba4 B.LS	4284f0

0x427ba8 ADD	X15, X20, X3

0x427bac ORR	W30, WZR, W6

0x427bb0 WHILELO	P5.D, XZR, X30

0x427bb4 ADD	X14, X15, X24

0x427bb8 MOVZ	X1, #0

0x427bbc ADD	X19, X19, X14

0x427bc0 ADD	X18, X0, X14

0x427bc4 UBFM	X6, X19, #61, #60

0x427bc8 ADD	X16, X27, X18,LSL #3

0x427bcc CNTD	X23, ALL

0x427bd0 SUB	X20, X6, #16

0x427bd4 SUB	X3, X6, #8

0x427bd8 SUB	X24, X16, #16

0x427bdc ADD	X10, X17, X20

0x427be0 ADD	X13, X17, X3

(222) 0x427be4 LD1D	{Z18.D}, P5/Z, [X10, X1,LSL #3]

(222) 0x427be8 LD1D	{Z24.D}, P5/Z, [X13, X1,LSL #3]

(222) 0x427bec FADD	Z18.D, P5/M, Z18.D, Z24.D

(222) 0x427bf0 FMUL	Z18.D, P5/M, Z18.D, #0.0000000

(222) 0x427bf4 ST1D	{Z18.D}, P5, [X24, X1,LSL #3]

(222) 0x427bf8 ADD	X1, X1, X23

(222) 0x427bfc WHILELO	P5.D, X1, X30

(222) 0x427c00 B.NE	427be4

0x427c04 BL	4103a0

0x427c08 LDP	X6, X20, [X26, #16]

0x427c0c LDR	W3, [X6]

0x427c10 LDR	W10, [X20]

0x427c14 SUB	W24, W3, #2

0x427c18 ADD	W13, W10, #3

0x427c1c SUB	W1, W13, W24

0x427c20 SDIV	W4, W1, W28

0x427c24 MSUB	W27, W4, W28, W1

0x427c28 CMP	W25, W27

0x427c2c B.LT	427ff0

0x427c30 MUL	W16, W4, W25

0x427c34 ADD	W17, W27, W16

0x427c38 ADD	W11, W4, W17

0x427c3c CMP	W17, W11

0x427c40 B.GE	427d00

0x427c44 LDR	X14, [X26, #120]

0x427c48 SBFM	X0, X27, #0, #31

0x427c4c ADD	X5, X21, W3,SXTW

0x427c50 ADD	X15, X0, W16,SXTW

0x427c54 ADD	X9, X15, X5

0x427c58 LDR	X8, [X26, #56]

0x427c5c UBFM	X2, X9, #61, #60

0x427c60 SUB	X7, X2, #16

0x427c64 ADD	X23, X7, W4,UXTW #3

0x427c68 ADD	X12, X14, X23

0x427c6c ADD	X10, X14, X7

0x427c70 CMP	X8, X12

0x427c74 ADD	X30, X8, #8

0x427c78 CCMP	X10, X30, #2, #3

0x427c7c B.CC	428a0c

0x427c80 CNTW	X19, ALL

0x427c84 SUB	W18, W4, #1

0x427c88 SUB	W6, W19, #1

0x427c8c MOVZ	W24, #0

0x427c90 CMP	W18, W6

0x427c94 B.CC	427cc8

0x427c98 SUB	W20, W4, W19

0x427c9c CNTB	X3, ALL, MUL #2

0x427ca0 PTRUE	P6.B, ALL

0x427ca4 LD1RD	{Z27.D}, P6/Z, [X8]

(220) 0x427ca8 ST1D	{Z27.D}, P6, [X10, #1, MUL VL]

(220) 0x427cac ADD	W24, W24, W19

(220) 0x427cb0 ST1D	{Z27.D}, P6, [X10, MUL VL]

(220) 0x427cb4 ADD	X10, X10, X3

(220) 0x427cb8 CMP	W24, W20

(220) 0x427cbc B.LS	427ca8

0x427cc0 CMP	W24, W4

0x427cc4 B.EQ	427d00

0x427cc8 ADD	X13, X5, W24,UXTW

0x427ccc ADD	X27, X13, X15

0x427cd0 MOVZ	X1, #0

0x427cd4 ADD	X16, X14, X27,LSL #3

0x427cd8 CNTD	X17, ALL

0x427cdc SUB	W4, W4, W24

0x427ce0 PTRUE	P0.B, ALL

0x427ce4 WHILELO	P7.D, XZR, X4

0x427ce8 LD1RD	{Z23.D}, P0/Z, [X8]

0x427cec SUB	X11, X16, #16

(219) 0x427cf0 ST1D	{Z23.D}, P7, [X11, X1,LSL #3]

(219) 0x427cf4 ADD	X1, X1, X17

(219) 0x427cf8 WHILELO	P7.D, X1, X4

(219) 0x427cfc B.NE	427cf0

0x427d00 BL	4103a0

0x427d04 LDP	X8, X24, [X26, #16]

0x427d08 LDR	W10, [X24]

0x427d0c LDR	W27, [X8]

0x427d10 ADD	W13, W10, #3

0x427d14 SUB	W4, W27, #2

0x427d18 SUB	W11, W13, W4

0x427d1c SDIV	W0, W11, W28

0x427d20 MSUB	W1, W0, W28, W11

0x427d24 CMP	W25, W1

0x427d28 B.LT	427fd8

0x427d2c MADD	W16, W0, W25, W1

0x427d30 ADD	W17, W0, W16

0x427d34 CMP	W16, W17

0x427d38 B.GE	427dd4

0x427d3c LDP	X15, X2, [X26]

0x427d40 ADD	W9, W4, W16

0x427d44 ADD	W5, W4, W17

0x427d48 LDR	X23, [X26, #48]

0x427d4c LDR	W30, [X2]

0x427d50 LDR	W19, [X15]

0x427d54 LDR	X7, [X26, #56]

0x427d58 ADD	W12, W30, #3

0x427d5c LDR	X14, [X26, #128]

0x427d60 SUB	W18, W19, #2

0x427d64 CMP	W18, W12

0x427d68 B.GE	427dd4

0x427d6c LDR	X13, [SP, #168]

0x427d70 SBFM	X20, X9, #0, #31

0x427d74 CNTD	X6, ALL

0x427d78 ADD	W3, W30, #5

0x427d7c PTRUE	P1.B, ALL

0x427d80 LDR	X8, [SP, #160]

0x427d84 ADD	X24, X8, W19,SXTW

0x427d88 SUB	W10, W3, W19

0x427d8c WHILELO	P15.D, XZR, X10

0x427d90 MADD	X4, X20, X13, X24

0x427d94 UBFM	X27, X13, #61, #60

0x427d98 ADD	X11, X14, X4,LSL #3

0x427d9c SUB	X1, X11, #16

(217) 0x427da0 MOVZ	X0, #0

(217) 0x427da4 ORR	P2.B, P15/Z, P15.B, P15.B

  (216) 0x427da8 LD1RD	{Z31.D}, P1/Z, [X23]

  (216) 0x427dac LD1RD	{Z25.D}, P1/Z, [X7]

  (216) 0x427db0 FMUL	Z31.D, P2/M, Z31.D, Z25.D

  (216) 0x427db4 ST1D	{Z31.D}, P2, [X1, X0,LSL #3]

  (216) 0x427db8 ADD	X0, X0, X6

  (216) 0x427dbc WHILELO	P2.D, X0, X10

  (216) 0x427dc0 B.NE	427da8

(217) 0x427dc4 ADD	W9, W9, #1

(217) 0x427dc8 ADD	X1, X1, X27

(217) 0x427dcc CMP	W5, W9

(217) 0x427dd0 B.GT	427da0

0x427dd4 BL	4103a0

0x427dd8 LDP	X5, X15, [X26, #16]

0x427ddc LDR	W2, [X15]

0x427de0 LDR	W14, [X5]

0x427de4 ADD	W23, W2, #3

0x427de8 SUB	W12, W14, #2

0x427dec SUB	W19, W23, W12

0x427df0 SDIV	W18, W19, W28

0x427df4 MSUB	W7, W18, W28, W19

0x427df8 CMP	W25, W7

0x427dfc B.LT	428008

0x427e00 MADD	W16, W18, W25, W7

0x427e04 ADD	W17, W18, W16

0x427e08 CMP	W16, W17

0x427e0c B.GE	427eb0

0x427e10 LDP	X3, X6, [X26]

0x427e14 ADD	W30, W12, W16

0x427e18 ADD	W20, W12, W17

0x427e1c LDR	X24, [X26, #120]

0x427e20 LDR	W27, [X6]

0x427e24 LDR	W4, [X3]

0x427e28 LDR	X13, [X26, #136]

0x427e2c ADD	W8, W27, #3

0x427e30 SUB	W10, W4, #2

0x427e34 CMP	W10, W8

0x427e38 B.GE	427eb0

0x427e3c LDR	X15, [SP, #152]

0x427e40 SBFM	X18, X30, #0, #31

0x427e44 ADD	X21, X24, X21,LSL #3

0x427e48 CNTD	X9, ALL

0x427e4c ADD	W11, W27, #5

0x427e50 PTRUE	P3.B, ALL

0x427e54 LDR	X0, [SP, #144]

0x427e58 ADD	X1, X0, W4,SXTW

0x427e5c SUB	W5, W11, W4

0x427e60 WHILELO	P8.D, XZR, X5

0x427e64 MADD	X2, X18, X15, X1

0x427e68 UBFM	X23, X15, #61, #60

0x427e6c ADD	X14, X13, X2,LSL #3

0x427e70 SUB	X7, X14, #16

0x427e74 HINT	#0

0x427e78 HINT	#0

0x427e7c HINT	#0

(215) 0x427e80 ADD	X12, X21, X18,LSL #3

(215) 0x427e84 MOVZ	X19, #0

(215) 0x427e88 ORR	P4.B, P8/Z, P8.B, P8.B

  (214) 0x427e8c LD1RD	{Z1.D}, P3/Z, [X12]

  (214) 0x427e90 ST1D	{Z1.D}, P4, [X7, X19,LSL #3]

  (214) 0x427e94 ADD	X19, X19, X9

  (214) 0x427e98 WHILELO	P4.D, X19, X5

  (214) 0x427e9c B.NE	427e8c

(215) 0x427ea0 ADD	X18, X18, #1

(215) 0x427ea4 ADD	X7, X7, X23

(215) 0x427ea8 CMP	W20, W18

(215) 0x427eac B.GT	427e80

0x427eb0 BL	4103a0

0x427eb4 LDP	X20, X3, [X26, #16]

0x427eb8 LDR	W6, [X3]

0x427ebc LDR	W13, [X20]

0x427ec0 ADD	W24, W6, #3

0x427ec4 SUB	W27, W13, #2

0x427ec8 SUB	W8, W24, W27

0x427ecc SDIV	W4, W8, W28

0x427ed0 MSUB	W28, W4, W28, W8

0x427ed4 CMP	W25, W28

0x427ed8 B.LT	427ffc

0x427edc MADD	W25, W4, W25, W28

0x427ee0 ADD	W16, W4, W25

0x427ee4 CMP	W25, W16

0x427ee8 B.GE	427f8c

0x427eec LDP	X30, X10, [X26]

0x427ef0 ADD	W5, W27, W25

0x427ef4 ADD	W17, W27, W16

0x427ef8 LDR	X21, [X26, #104]

0x427efc LDR	W9, [X10]

0x427f00 LDR	W15, [X30]

0x427f04 LDR	X26, [X26, #144]

0x427f08 ADD	W11, W9, #3

0x427f0c SUB	W0, W15, #2

0x427f10 CMP	W0, W11

0x427f14 B.GE	427f8c

0x427f18 LDR	X19, [SP, #128]

0x427f1c SBFM	X23, X15, #0, #31

0x427f20 SBFM	X1, X5, #0, #31

0x427f24 ADD	X22, X22, X23

0x427f28 CNTD	X14, ALL

0x427f2c LDR	X3, [SP, #136]

0x427f30 ADD	X7, X21, X22,LSL #3

0x427f34 ADD	W2, W9, #5

0x427f38 SUB	W12, W2, W15

0x427f3c WHILELO	P9.D, XZR, X12

0x427f40 SUB	X20, X7, #16

0x427f44 ADD	X18, X19, X23

0x427f48 MADD	X24, X1, X3, X18

0x427f4c UBFM	X6, X3, #61, #60

0x427f50 ADD	X13, X26, X24,LSL #3

0x427f54 SUB	X8, X13, #16

0x427f58 HINT	#0

0x427f5c HINT	#0

(213) 0x427f60 MOVZ	X27, #0

(213) 0x427f64 ORR	P5.B, P9/Z, P9.B, P9.B

  (212) 0x427f68 LD1D	{Z26.D}, P5/Z, [X20, X27,LSL #3]

  (212) 0x427f6c ST1D	{Z26.D}, P5, [X8, X27,LSL #3]

  (212) 0x427f70 ADD	X27, X27, X14

  (212) 0x427f74 WHILELO	P5.D, X27, X12

  (212) 0x427f78 B.NE	427f68

(213) 0x427f7c ADD	W5, W5, #1

(213) 0x427f80 ADD	X8, X8, X6

(213) 0x427f84 CMP	W17, W5

(213) 0x427f88 B.GT	427f60

0x427f8c LDP	X19, X20, [SP, #16]

0x427f90 LDP	X21, X22, [SP, #32]

0x427f94 LDP	X23, X24, [SP, #48]

0x427f98 LDP	X25, X26, [SP, #64]

0x427f9c LDP	X27, X28, [SP, #80]

0x427fa0 LDP	X29, X30, [SP], #176

0x427fa4 RET

0x427fa8 ADD	W27, W27, #1

0x427fac MOVZ	W5, #0

0x427fb0 B	427744

0x427fb4 ADD	W6, W6, #1

0x427fb8 MOVZ	W14, #0

0x427fbc B	427b48

0x427fc0 ADD	W15, W15, #1

0x427fc4 MOVZ	W5, #0

0x427fc8 B	427a4c

0x427fcc ADD	W14, W14, #1

0x427fd0 MOVZ	W15, #0

0x427fd4 B	42752c

0x427fd8 ADD	W0, W0, #1

0x427fdc MOVZ	W1, #0

0x427fe0 B	427d2c

0x427fe4 ADD	W18, W18, #1

0x427fe8 MOVZ	W9, #0

0x427fec B	427964

0x427ff0 ADD	W4, W4, #1

0x427ff4 MOVZ	W27, #0

0x427ff8 B	427c30

0x427ffc ADD	W4, W4, #1

0x428000 MOVZ	W28, #0

0x428004 B	427edc

0x428008 ADD	W18, W18, #1

0x42800c MOVZ	W7, #0

0x428010 B	427e00

0x428014 ADD	W7, W7, #1

0x428018 MOVZ	W15, #0

0x42801c B	427858

0x428020 ADD	W15, W15, #1

0x428024 MOVZ	W9, #0

0x428028 B	427640

0x42802c LDR	D27, [X14]

0x428030 ADD	W30, W11, W5

0x428034 ADD	X23, X23, X17,LSL #3

0x428038 SBFM	X10, X30, #0, #31

0x42803c ADD	W18, W11, W16

0x428040 ORN	W9, WZR, W30

0x428044 ADD	X2, X10, #1

0x428048 ADD	W8, W18, W9

0x42804c AND	W27, W8, #0x7

0x428050 STR	D27, [X23, X10,LSL #3]

0x428054 CMP	W18, W2

0x428058 B.LE	427938

0x42805c CBZ	W27, 4280ec

0x428060 CMP	W27, #1

0x428064 B.EQ	4280d8

0x428068 CMP	W27, #2

0x42806c B.EQ	4280cc

0x428070 CMP	W27, #3

0x428074 B.EQ	4280c0

0x428078 CMP	W27, #4

0x42807c B.EQ	4280b4

0x428080 CMP	W27, #5

0x428084 B.EQ	4280a8

0x428088 CMP	W27, #6

0x42808c B.EQ	42809c

0x428090 LDR	D2, [X14]

0x428094 STR	D2, [X23, X2,LSL #3]

0x428098 ADD	X2, X2, #1

0x42809c LDR	D3, [X14]

0x4280a0 STR	D3, [X23, X2,LSL #3]

0x4280a4 ADD	X2, X2, #1

0x4280a8 LDR	D22, [X14]

0x4280ac STR	D22, [X23, X2,LSL #3]

0x4280b0 ADD	X2, X2, #1

0x4280b4 LDR	D23, [X14]

0x4280b8 STR	D23, [X23, X2,LSL #3]

0x4280bc ADD	X2, X2, #1

0x4280c0 LDR	D4, [X14]

0x4280c4 STR	D4, [X23, X2,LSL #3]

0x4280c8 ADD	X2, X2, #1

0x4280cc LDR	D21, [X14]

0x4280d0 STR	D21, [X23, X2,LSL #3]

0x4280d4 ADD	X2, X2, #1

0x4280d8 LDR	D18, [X14]

0x4280dc STR	D18, [X23, X2,LSL #3]

0x4280e0 ADD	X2, X2, #1

0x4280e4 CMP	W18, W2

0x4280e8 B.LE	427938

(228) 0x4280ec LDR	D24, [X14]

(228) 0x4280f0 ADD	X4, X2, #1

(228) 0x4280f4 ADD	X11, X2, #2

(228) 0x4280f8 ADD	X12, X2, #3

(228) 0x4280fc ADD	X0, X2, #4

(228) 0x428100 ADD	X15, X2, #5

(228) 0x428104 ADD	X5, X2, #6

(228) 0x428108 ADD	X1, X2, #7

(228) 0x42810c STR	D24, [X23, X2,LSL #3]

(228) 0x428110 ADD	X2, X2, #8

(228) 0x428114 LDR	D7, [X14]

(228) 0x428118 STR	D7, [X23, X4,LSL #3]

(228) 0x42811c LDR	D19, [X14]

(228) 0x428120 STR	D19, [X23, X11,LSL #3]

(228) 0x428124 LDR	D5, [X14]

(228) 0x428128 STR	D5, [X23, X12,LSL #3]

(228) 0x42812c LDR	D20, [X14]

(228) 0x428130 STR	D20, [X23, X0,LSL #3]

(228) 0x428134 LDR	D6, [X14]

(228) 0x428138 STR	D6, [X23, X15,LSL #3]

(228) 0x42813c LDR	D17, [X14]

(228) 0x428140 STR	D17, [X23, X5,LSL #3]

(228) 0x428144 LDR	D29, [X14]

(228) 0x428148 STR	D29, [X23, X1,LSL #3]

(228) 0x42814c CMP	W18, W2

(228) 0x428150 B.GT	4280ec

0x428154 B	427938

0x428158 SUB	W18, W0, W18

0x42815c LDR	D31, [X8]

0x428160 ADD	X12, X1, X19,LSL #3

0x428164 SBFM	X9, X0, #0, #31

0x428168 ADD	W4, W23, W30

0x42816c SCVTF	S16, W18

0x428170 LDR	D30, [X27]

0x428174 ORN	W2, WZR, W0

0x428178 ADD	W0, W4, W2

0x42817c ADD	X6, X9, #1

0x428180 ADD	W1, W18, #1

0x428184 AND	W11, W0, #0x7

0x428188 FCVT	D17, S16

0x42818c FMADD	D28, D30, D17, D31

0x428190 STR	D28, [X12, X9,LSL #3]

0x428194 CMP	W4, W6

0x428198 B.LE	42782c

0x42819c CBZ	W11, 4282b8

0x4281a0 CMP	W11, #1

0x4281a4 B.EQ	428290

0x4281a8 CMP	W11, #2

0x4281ac B.EQ	428270

0x4281b0 CMP	W11, #3

0x4281b4 B.EQ	428250

0x4281b8 CMP	W11, #4

0x4281bc B.EQ	428230

0x4281c0 CMP	W11, #5

0x4281c4 B.EQ	428210

0x4281c8 CMP	W11, #6

0x4281cc B.EQ	4281f0

0x4281d0 SCVTF	S29, W1

0x4281d4 LDR	D1, [X8]

0x4281d8 ADD	W1, W1, #1

0x4281dc LDR	D26, [X27]

0x4281e0 FCVT	D0, S29

0x4281e4 FMADD	D27, D26, D0, D1

0x4281e8 STR	D27, [X12, X6,LSL #3]

0x4281ec ADD	X6, X6, #1

0x4281f0 SCVTF	S2, W1

0x4281f4 LDR	D3, [X8]

0x4281f8 ADD	W1, W1, #1

0x4281fc LDR	D22, [X27]

0x428200 FCVT	D25, S2

0x428204 FMADD	D23, D22, D25, D3

0x428208 STR	D23, [X12, X6,LSL #3]

0x42820c ADD	X6, X6, #1

0x428210 SCVTF	S4, W1

0x428214 LDR	D24, [X8]

0x428218 ADD	W1, W1, #1

0x42821c LDR	D18, [X27]

0x428220 FCVT	D21, S4

0x428224 FMADD	D7, D18, D21, D24

0x428228 STR	D7, [X12, X6,LSL #3]

0x42822c ADD	X6, X6, #1

0x428230 SCVTF	S19, W1

0x428234 LDR	D20, [X8]

0x428238 ADD	W1, W1, #1

0x42823c LDR	D6, [X27]

0x428240 FCVT	D5, S19

0x428244 FMADD	D16, D6, D5, D20

0x428248 STR	D16, [X12, X6,LSL #3]

0x42824c ADD	X6, X6, #1

0x428250 SCVTF	S17, W1

0x428254 LDR	D30, [X8]

0x428258 ADD	W1, W1, #1

0x42825c LDR	D28, [X27]

0x428260 FCVT	D31, S17

0x428264 FMADD	D29, D28, D31, D30

0x428268 STR	D29, [X12, X6,LSL #3]

0x42826c ADD	X6, X6, #1

0x428270 SCVTF	S0, W1

0x428274 LDR	D26, [X8]

0x428278 ADD	W1, W1, #1

0x42827c LDR	D27, [X27]

0x428280 FCVT	D1, S0

0x428284 FMADD	D2, D27, D1, D26

0x428288 STR	D2, [X12, X6,LSL #3]

0x42828c ADD	X6, X6, #1

0x428290 SCVTF	S25, W1

0x428294 LDR	D22, [X8]

0x428298 ADD	W1, W1, #1

0x42829c LDR	D23, [X27]

0x4282a0 FCVT	D3, S25

0x4282a4 FMADD	D4, D23, D3, D22

0x4282a8 STR	D4, [X12, X6,LSL #3]

0x4282ac ADD	X6, X6, #1

0x4282b0 CMP	W4, W6

0x4282b4 B.LE	42782c

(231) 0x4282b8 SCVTF	S21, W1

(231) 0x4282bc LDR	D1, [X8]

(231) 0x4282c0 ADD	W7, W1, #1

(231) 0x4282c4 ADD	W15, W7, #1

(231) 0x4282c8 ADD	X3, X6, #1

(231) 0x4282cc LDR	D26, [X27]

(231) 0x4282d0 SCVTF	S24, W7

(231) 0x4282d4 ADD	W5, W1, #3

(231) 0x4282d8 SCVTF	S18, W15

(231) 0x4282dc ADD	X16, X6, #2

(231) 0x4282e0 ADD	W13, W1, #4

(231) 0x4282e4 SCVTF	S7, W5

(231) 0x4282e8 ADD	X14, X6, #3

(231) 0x4282ec ADD	W23, W1, #5

(231) 0x4282f0 SCVTF	S5, W13

(231) 0x4282f4 ADD	X17, X6, #4

(231) 0x4282f8 ADD	W30, W1, #6

(231) 0x4282fc FCVT	D19, S21

(231) 0x428300 SCVTF	S6, W23

(231) 0x428304 ADD	X10, X6, #5

(231) 0x428308 SCVTF	S16, W30

(231) 0x42830c ADD	W18, W1, #7

(231) 0x428310 ADD	X9, X6, #6

(231) 0x428314 FCVT	D20, S24

(231) 0x428318 ADD	X2, X6, #7

(231) 0x42831c ADD	W1, W1, #8

(231) 0x428320 FCVT	D17, S18

(231) 0x428324 SCVTF	S0, W18

(231) 0x428328 FCVT	D29, S7

(231) 0x42832c FCVT	D28, S5

(231) 0x428330 FMADD	D27, D26, D19, D1

(231) 0x428334 FCVT	D30, S6

(231) 0x428338 FCVT	D31, S16

(231) 0x42833c FCVT	D25, S0

(231) 0x428340 STR	D27, [X12, X6,LSL #3]

(231) 0x428344 ADD	X6, X6, #8

(231) 0x428348 LDR	D2, [X8]

(231) 0x42834c LDR	D3, [X27]

(231) 0x428350 FMADD	D22, D3, D20, D2

(231) 0x428354 STR	D22, [X12, X3,LSL #3]

(231) 0x428358 LDR	D23, [X8]

(231) 0x42835c LDR	D4, [X27]

(231) 0x428360 FMADD	D21, D4, D17, D23

(231) 0x428364 STR	D21, [X12, X16,LSL #3]

(231) 0x428368 LDR	D18, [X8]

(231) 0x42836c LDR	D24, [X27]

(231) 0x428370 FMADD	D7, D24, D29, D18

(231) 0x428374 STR	D7, [X12, X14,LSL #3]

(231) 0x428378 LDR	D19, [X8]

(231) 0x42837c LDR	D5, [X27]

(231) 0x428380 FMADD	D20, D5, D28, D19

(231) 0x428384 STR	D20, [X12, X17,LSL #3]

(231) 0x428388 LDR	D6, [X8]

(231) 0x42838c LDR	D17, [X27]

(231) 0x428390 FMADD	D29, D17, D30, D6

(231) 0x428394 STR	D29, [X12, X10,LSL #3]

(231) 0x428398 LDR	D28, [X8]

(231) 0x42839c LDR	D30, [X27]

(231) 0x4283a0 FMADD	D16, D30, D31, D28

(231) 0x4283a4 STR	D16, [X12, X9,LSL #3]

(231) 0x4283a8 LDR	D0, [X8]

(231) 0x4283ac LDR	D31, [X27]

(231) 0x4283b0 FMADD	D25, D31, D25, D0

(231) 0x4283b4 STR	D25, [X12, X2,LSL #3]

(231) 0x4283b8 CMP	W4, W6

(231) 0x4283bc B.GT	4282b8

0x4283c0 B	42782c

0x4283c4 LDR	D20, [X14]

0x4283c8 ADD	W18, W4, W7

0x4283cc ADD	X23, X23, X17,LSL #3

0x4283d0 SBFM	X30, X18, #0, #31

0x4283d4 ADD	W27, W4, W16

0x4283d8 ORN	W5, WZR, W18

0x4283dc ADD	X2, X30, #1

0x4283e0 ADD	W10, W27, W5

0x4283e4 AND	W12, W10, #0x7

0x4283e8 STR	D20, [X23, X30,LSL #3]

0x4283ec CMP	W27, W2

0x4283f0 B.LE	427718

0x4283f4 CBZ	W12, 428484

0x4283f8 CMP	W12, #1

0x4283fc B.EQ	428470

0x428400 CMP	W12, #2

0x428404 B.EQ	428464

0x428408 CMP	W12, #3

0x42840c B.EQ	428458

0x428410 CMP	W12, #4

0x428414 B.EQ	42844c

0x428418 CMP	W12, #5

0x42841c B.EQ	428440

0x428420 CMP	W12, #6

0x428424 B.EQ	428434

0x428428 LDR	D6, [X14]

0x42842c STR	D6, [X23, X2,LSL #3]

0x428430 ADD	X2, X2, #1

0x428434 LDR	D16, [X14]

0x428438 STR	D16, [X23, X2,LSL #3]

0x42843c ADD	X2, X2, #1

0x428440 LDR	D17, [X14]

0x428444 STR	D17, [X23, X2,LSL #3]

0x428448 ADD	X2, X2, #1

0x42844c LDR	D31, [X14]

0x428450 STR	D31, [X23, X2,LSL #3]

0x428454 ADD	X2, X2, #1

0x428458 LDR	D30, [X14]

0x42845c STR	D30, [X23, X2,LSL #3]

0x428460 ADD	X2, X2, #1

0x428464 LDR	D28, [X14]

0x428468 STR	D28, [X23, X2,LSL #3]

0x42846c ADD	X2, X2, #1

0x428470 LDR	D29, [X14]

0x428474 STR	D29, [X23, X2,LSL #3]

0x428478 ADD	X2, X2, #1

0x42847c CMP	W27, W2

0x428480 B.LE	427718

(233) 0x428484 LDR	D0, [X14]

(233) 0x428488 ADD	X4, X2, #1

(233) 0x42848c ADD	X9, X2, #2

(233) 0x428490 ADD	X0, X2, #3

(233) 0x428494 ADD	X11, X2, #4

(233) 0x428498 ADD	X1, X2, #5

(233) 0x42849c ADD	X6, X2, #6

(233) 0x4284a0 ADD	X3, X2, #7

(233) 0x4284a4 STR	D0, [X23, X2,LSL #3]

(233) 0x4284a8 ADD	X2, X2, #8

(233) 0x4284ac LDR	D1, [X14]

(233) 0x4284b0 STR	D1, [X23, X4,LSL #3]

(233) 0x4284b4 LDR	D26, [X14]

(233) 0x4284b8 STR	D26, [X23, X9,LSL #3]

(233) 0x4284bc LDR	D27, [X14]

(233) 0x4284c0 STR	D27, [X23, X0,LSL #3]

(233) 0x4284c4 LDR	D2, [X14]

(233) 0x4284c8 STR	D2, [X23, X11,LSL #3]

(233) 0x4284cc LDR	D25, [X14]

(233) 0x4284d0 STR	D25, [X23, X1,LSL #3]

(233) 0x4284d4 LDR	D3, [X14]

(233) 0x4284d8 STR	D3, [X23, X6,LSL #3]

(233) 0x4284dc LDR	D22, [X14]

(233) 0x4284e0 STR	D22, [X23, X3,LSL #3]

(233) 0x4284e4 CMP	W27, W2

(233) 0x4284e8 B.GT	428484

0x4284ec B	427718

0x4284f0 ADD	X17, X17, X19,LSL #3

0x4284f4 ADD	W4, W15, W18

0x4284f8 FMOV	D27, #0.5000000

0x4284fc SBFM	X11, X4, #0, #31

0x428500 ADD	X27, X27, X0,LSL #3

0x428504 ORN	W2, WZR, W4

0x428508 ADD	X9, X17, #8

0x42850c ADD	W0, W15, W16

0x428510 LDR	D7, [X17, X11,LSL #3]

0x428514 ADD	W8, W0, W2

0x428518 ADD	X7, X11, #1

0x42851c AND	W5, W8, #0x7

0x428520 LDR	D19, [X9, X11,LSL #3]

0x428524 FADD	D5, D7, D19

0x428528 FMUL	D20, D5, D27

0x42852c STR	D20, [X27, X11,LSL #3]

0x428530 CMP	W0, W7

0x428534 B.LE	427c04

0x428538 CBZ	W5, 42861c

0x42853c CMP	W5, #1

0x428540 B.EQ	4285fc

0x428544 CMP	W5, #2

0x428548 B.EQ	4285e4

0x42854c CMP	W5, #3

0x428550 B.EQ	4285cc

0x428554 CMP	W5, #4

0x428558 B.EQ	4285b4

0x42855c CMP	W5, #5

0x428560 B.EQ	42859c

0x428564 CMP	W5, #6

0x428568 B.EQ	428584

0x42856c LDR	D6, [X17, X7,LSL #3]

0x428570 LDR	D3, [X9, X7,LSL #3]

0x428574 FADD	D17, D6, D3

0x428578 FMUL	D29, D17, D27

0x42857c STR	D29, [X27, X7,LSL #3]

0x428580 ADD	X7, X7, #1

0x428584 LDR	D28, [X17, X7,LSL #3]

0x428588 LDR	D30, [X9, X7,LSL #3]

0x42858c FADD	D16, D28, D30

0x428590 FMUL	D0, D16, D27

0x428594 STR	D0, [X27, X7,LSL #3]

0x428598 ADD	X7, X7, #1

0x42859c LDR	D31, [X17, X7,LSL #3]

0x4285a0 LDR	D25, [X9, X7,LSL #3]

0x4285a4 FADD	D1, D31, D25

0x4285a8 FMUL	D26, D1, D27

0x4285ac STR	D26, [X27, X7,LSL #3]

0x4285b0 ADD	X7, X7, #1

0x4285b4 LDR	D2, [X17, X7,LSL #3]

0x4285b8 LDR	D22, [X9, X7,LSL #3]

0x4285bc FADD	D23, D2, D22

0x4285c0 FMUL	D4, D23, D27

0x4285c4 STR	D4, [X27, X7,LSL #3]

0x4285c8 ADD	X7, X7, #1

0x4285cc LDR	D21, [X17, X7,LSL #3]

0x4285d0 LDR	D18, [X9, X7,LSL #3]

0x4285d4 FADD	D24, D21, D18

0x4285d8 FMUL	D7, D24, D27

0x4285dc STR	D7, [X27, X7,LSL #3]

0x4285e0 ADD	X7, X7, #1

0x4285e4 LDR	D19, [X17, X7,LSL #3]

0x4285e8 LDR	D5, [X9, X7,LSL #3]

0x4285ec FADD	D20, D19, D5

0x4285f0 FMUL	D6, D20, D27

0x4285f4 STR	D6, [X27, X7,LSL #3]

0x4285f8 ADD	X7, X7, #1

0x4285fc LDR	D3, [X17, X7,LSL #3]

0x428600 LDR	D17, [X9, X7,LSL #3]

0x428604 FADD	D29, D3, D17

0x428608 FMUL	D28, D29, D27

0x42860c STR	D28, [X27, X7,LSL #3]

0x428610 ADD	X7, X7, #1

0x428614 CMP	W0, W7

0x428618 B.LE	427c04

(221) 0x42861c LDR	D30, [X17, X7,LSL #3]

(221) 0x428620 ADD	X15, X7, #1

(221) 0x428624 ADD	X14, X7, #2

(221) 0x428628 ADD	X23, X7, #3

(221) 0x42862c ADD	X12, X7, #4

(221) 0x428630 LDR	D16, [X9, X7,LSL #3]

(221) 0x428634 ADD	X30, X7, #5

(221) 0x428638 ADD	X19, X7, #6

(221) 0x42863c ADD	X18, X7, #7

(221) 0x428640 FADD	D0, D30, D16

(221) 0x428644 FMUL	D31, D0, D27

(221) 0x428648 STR	D31, [X27, X7,LSL #3]

(221) 0x42864c ADD	X7, X7, #8

(221) 0x428650 LDR	D25, [X17, X15,LSL #3]

(221) 0x428654 LDR	D1, [X9, X15,LSL #3]

(221) 0x428658 FADD	D26, D25, D1

(221) 0x42865c FMUL	D2, D26, D27

(221) 0x428660 STR	D2, [X27, X15,LSL #3]

(221) 0x428664 LDR	D22, [X17, X14,LSL #3]

(221) 0x428668 LDR	D23, [X9, X14,LSL #3]

(221) 0x42866c FADD	D4, D22, D23

(221) 0x428670 FMUL	D21, D4, D27

(221) 0x428674 STR	D21, [X27, X14,LSL #3]

(221) 0x428678 LDR	D18, [X17, X23,LSL #3]

(221) 0x42867c LDR	D24, [X9, X23,LSL #3]

(221) 0x428680 FADD	D7, D18, D24

(221) 0x428684 FMUL	D19, D7, D27

(221) 0x428688 STR	D19, [X27, X23,LSL #3]

(221) 0x42868c LDR	D5, [X17, X12,LSL #3]

(221) 0x428690 LDR	D20, [X9, X12,LSL #3]

(221) 0x428694 FADD	D6, D5, D20

(221) 0x428698 FMUL	D3, D6, D27

(221) 0x42869c STR	D3, [X27, X12,LSL #3]

(221) 0x4286a0 LDR	D17, [X17, X30,LSL #3]

(221) 0x4286a4 LDR	D29, [X9, X30,LSL #3]

(221) 0x4286a8 FADD	D28, D17, D29

(221) 0x4286ac FMUL	D30, D28, D27

(221) 0x4286b0 STR	D30, [X27, X30,LSL #3]

(221) 0x4286b4 LDR	D16, [X17, X19,LSL #3]

(221) 0x4286b8 LDR	D0, [X9, X19,LSL #3]

(221) 0x4286bc FADD	D31, D16, D0

(221) 0x4286c0 FMUL	D25, D31, D27

(221) 0x4286c4 STR	D25, [X27, X19,LSL #3]

(221) 0x4286c8 LDR	D1, [X17, X18,LSL #3]

(221) 0x4286cc LDR	D26, [X9, X18,LSL #3]

(221) 0x4286d0 FADD	D2, D1, D26

(221) 0x4286d4 FMUL	D22, D2, D27

(221) 0x4286d8 STR	D22, [X27, X18,LSL #3]

(221) 0x4286dc CMP	W0, W7

(221) 0x4286e0 B.GT	42861c

0x4286e4 B	427c04

0x4286e8 LDR	D17, [X9]

0x4286ec ADD	X18, X20, X22,LSL #3

0x4286f0 ADD	W14, W11, W7

0x4286f4 SBFM	X3, X14, #0, #31

0x4286f8 ADD	W16, W11, W23

0x4286fc ORN	W1, WZR, W14

0x428700 ADD	X24, X3, #1

0x428704 ADD	W13, W16, W1

0x428708 AND	W20, W13, #0x7

0x42870c STR	D17, [X18, X3,LSL #3]

0x428710 CMP	W16, W24

0x428714 B.LE	427b1c

0x428718 CBZ	W20, 4287a8

0x42871c CMP	W20, #1

0x428720 B.EQ	428794

0x428724 CMP	W20, #2

0x428728 B.EQ	428788

0x42872c CMP	W20, #3

0x428730 B.EQ	42877c

0x428734 CMP	W20, #4

0x428738 B.EQ	428770

0x42873c CMP	W20, #5

0x428740 B.EQ	428764

0x428744 CMP	W20, #6

0x428748 B.EQ	428758

0x42874c LDR	D29, [X9]

0x428750 STR	D29, [X18, X24,LSL #3]

0x428754 ADD	X24, X24, #1

0x428758 LDR	D28, [X9]

0x42875c STR	D28, [X18, X24,LSL #3]

0x428760 ADD	X24, X24, #1

0x428764 LDR	D30, [X9]

0x428768 STR	D30, [X18, X24,LSL #3]

0x42876c ADD	X24, X24, #1

0x428770 LDR	D16, [X9]

0x428774 STR	D16, [X18, X24,LSL #3]

0x428778 ADD	X24, X24, #1

0x42877c LDR	D0, [X9]

0x428780 STR	D0, [X18, X24,LSL #3]

0x428784 ADD	X24, X24, #1

0x428788 LDR	D31, [X9]

0x42878c STR	D31, [X18, X24,LSL #3]

0x428790 ADD	X24, X24, #1

0x428794 LDR	D25, [X9]

0x428798 STR	D25, [X18, X24,LSL #3]

0x42879c ADD	X24, X24, #1

0x4287a0 CMP	W16, W24

0x4287a4 B.LE	427b1c

(223) 0x4287a8 LDR	D1, [X9]

(223) 0x4287ac ADD	X10, X24, #1

(223) 0x4287b0 ADD	X27, X24, #2

(223) 0x4287b4 ADD	X17, X24, #3

(223) 0x4287b8 ADD	X4, X24, #4

(223) 0x4287bc ADD	X0, X24, #5

(223) 0x4287c0 ADD	X11, X24, #6

(223) 0x4287c4 ADD	X2, X24, #7

(223) 0x4287c8 STR	D1, [X18, X24,LSL #3]

(223) 0x4287cc ADD	X24, X24, #8

(223) 0x4287d0 LDR	D26, [X9]

(223) 0x4287d4 STR	D26, [X18, X10,LSL #3]

(223) 0x4287d8 LDR	D27, [X9]

(223) 0x4287dc STR	D27, [X18, X27,LSL #3]

(223) 0x4287e0 LDR	D2, [X9]

(223) 0x4287e4 STR	D2, [X18, X17,LSL #3]

(223) 0x4287e8 LDR	D22, [X9]

(223) 0x4287ec STR	D22, [X18, X4,LSL #3]

(223) 0x4287f0 LDR	D23, [X9]

(223) 0x4287f4 STR	D23, [X18, X0,LSL #3]

(223) 0x4287f8 LDR	D4, [X9]

(223) 0x4287fc STR	D4, [X18, X11,LSL #3]

(223) 0x428800 LDR	D21, [X9]

(223) 0x428804 STR	D21, [X18, X2,LSL #3]

(223) 0x428808 CMP	W16, W24

(223) 0x42880c B.GT	4287a8

0x428810 B	427b1c

0x428814 ADD	X0, X14, X20,LSL #3

0x428818 ADD	W15, W23, W17

0x42881c FMOV	D3, #0.5000000

0x428820 SBFM	X5, X15, #0, #31

0x428824 ADD	X7, X7, X24,LSL #3

0x428828 ADD	W23, W23, W30

0x42882c ADD	X3, X0, #8

0x428830 ORN	W6, WZR, W15

0x428834 LDR	D16, [X0, X5,LSL #3]

0x428838 ADD	W14, W23, W6

0x42883c ADD	X18, X5, #1

0x428840 AND	W1, W14, #0x7

0x428844 LDR	D0, [X3, X5,LSL #3]

0x428848 FADD	D31, D16, D0

0x42884c FMUL	D25, D31, D3

0x428850 STR	D25, [X7, X5,LSL #3]

0x428854 CMP	W23, W18

0x428858 B.LE	427a20

0x42885c CBZ	W1, 428940

0x428860 CMP	W1, #1

0x428864 B.EQ	428920

0x428868 CMP	W1, #2

0x42886c B.EQ	428908

0x428870 CMP	W1, #3

0x428874 B.EQ	4288f0

0x428878 CMP	W1, #4

0x42887c B.EQ	4288d8

0x428880 CMP	W1, #5

0x428884 B.EQ	4288c0

0x428888 CMP	W1, #6

0x42888c B.EQ	4288a8

0x428890 LDR	D1, [X0, X18,LSL #3]

0x428894 LDR	D26, [X3, X18,LSL #3]

0x428898 FADD	D27, D1, D26

0x42889c FMUL	D2, D27, D3

0x4288a0 STR	D2, [X7, X18,LSL #3]

0x4288a4 ADD	X18, X18, #1

0x4288a8 LDR	D22, [X0, X18,LSL #3]

0x4288ac LDR	D23, [X3, X18,LSL #3]

0x4288b0 FADD	D4, D22, D23

0x4288b4 FMUL	D21, D4, D3

0x4288b8 STR	D21, [X7, X18,LSL #3]

0x4288bc ADD	X18, X18, #1

0x4288c0 LDR	D18, [X0, X18,LSL #3]

0x4288c4 LDR	D24, [X3, X18,LSL #3]

0x4288c8 FADD	D7, D18, D24

0x4288cc FMUL	D19, D7, D3

0x4288d0 STR	D19, [X7, X18,LSL #3]

0x4288d4 ADD	X18, X18, #1

0x4288d8 LDR	D5, [X0, X18,LSL #3]

0x4288dc LDR	D20, [X3, X18,LSL #3]

0x4288e0 FADD	D6, D5, D20

0x4288e4 FMUL	D17, D6, D3

0x4288e8 STR	D17, [X7, X18,LSL #3]

0x4288ec ADD	X18, X18, #1

0x4288f0 LDR	D29, [X0, X18,LSL #3]

0x4288f4 LDR	D28, [X3, X18,LSL #3]

0x4288f8 FADD	D30, D29, D28

0x4288fc FMUL	D16, D30, D3

0x428900 STR	D16, [X7, X18,LSL #3]

0x428904 ADD	X18, X18, #1

0x428908 LDR	D0, [X0, X18,LSL #3]

0x42890c LDR	D31, [X3, X18,LSL #3]

0x428910 FADD	D25, D0, D31

0x428914 FMUL	D1, D25, D3

0x428918 STR	D1, [X7, X18,LSL #3]

0x42891c ADD	X18, X18, #1

0x428920 LDR	D26, [X0, X18,LSL #3]

0x428924 LDR	D27, [X3, X18,LSL #3]

0x428928 FADD	D2, D26, D27

0x42892c FMUL	D22, D2, D3

0x428930 STR	D22, [X7, X18,LSL #3]

0x428934 ADD	X18, X18, #1

0x428938 CMP	W23, W18

0x42893c B.LE	427a20

(226) 0x428940 LDR	D23, [X0, X18,LSL #3]

(226) 0x428944 ADD	X16, X18, #1

(226) 0x428948 ADD	X9, X18, #2

(226) 0x42894c ADD	X13, X18, #3

(226) 0x428950 ADD	X20, X18, #4

(226) 0x428954 LDR	D4, [X3, X18,LSL #3]

(226) 0x428958 ADD	X24, X18, #5

(226) 0x42895c ADD	X10, X18, #6

(226) 0x428960 ADD	X17, X18, #7

(226) 0x428964 FADD	D21, D23, D4

(226) 0x428968 FMUL	D18, D21, D3

(226) 0x42896c STR	D18, [X7, X18,LSL #3]

(226) 0x428970 ADD	X18, X18, #8

(226) 0x428974 LDR	D24, [X0, X16,LSL #3]

(226) 0x428978 LDR	D7, [X3, X16,LSL #3]

(226) 0x42897c FADD	D19, D24, D7

(226) 0x428980 FMUL	D5, D19, D3

(226) 0x428984 STR	D5, [X7, X16,LSL #3]

(226) 0x428988 LDR	D20, [X0, X9,LSL #3]

(226) 0x42898c LDR	D6, [X3, X9,LSL #3]

(226) 0x428990 FADD	D17, D20, D6

(226) 0x428994 FMUL	D29, D17, D3

(226) 0x428998 STR	D29, [X7, X9,LSL #3]

(226) 0x42899c LDR	D28, [X0, X13,LSL #3]

(226) 0x4289a0 LDR	D30, [X3, X13,LSL #3]

(226) 0x4289a4 FADD	D16, D28, D30

(226) 0x4289a8 FMUL	D0, D16, D3

(226) 0x4289ac STR	D0, [X7, X13,LSL #3]

(226) 0x4289b0 LDR	D31, [X0, X20,LSL #3]

(226) 0x4289b4 LDR	D25, [X3, X20,LSL #3]

(226) 0x4289b8 FADD	D1, D31, D25

(226) 0x4289bc FMUL	D26, D1, D3

(226) 0x4289c0 STR	D26, [X7, X20,LSL #3]

(226) 0x4289c4 LDR	D27, [X0, X24,LSL #3]

(226) 0x4289c8 LDR	D2, [X3, X24,LSL #3]

(226) 0x4289cc FADD	D22, D27, D2

(226) 0x4289d0 FMUL	D23, D22, D3

(226) 0x4289d4 STR	D23, [X7, X24,LSL #3]

(226) 0x4289d8 LDR	D4, [X0, X10,LSL #3]

(226) 0x4289dc LDR	D21, [X3, X10,LSL #3]

(226) 0x4289e0 FADD	D18, D4, D21

(226) 0x4289e4 FMUL	D24, D18, D3

(226) 0x4289e8 STR	D24, [X7, X10,LSL #3]

(226) 0x4289ec LDR	D7, [X0, X17,LSL #3]

(226) 0x4289f0 LDR	D19, [X3, X17,LSL #3]

(226) 0x4289f4 FADD	D5, D7, D19

(226) 0x4289f8 FMUL	D20, D5, D3

(226) 0x4289fc STR	D20, [X7, X17,LSL #3]

(226) 0x428a00 CMP	W23, W18

(226) 0x428a04 B.GT	428940

0x428a08 B	427a20

0x428a0c LDR	D4, [X8]

0x428a10 ADD	X5, X14, X21,LSL #3

0x428a14 ADD	W0, W24, W17

0x428a18 SBFM	X15, X0, #0, #31

0x428a1c ADD	W9, W24, W11

0x428a20 ORN	W2, WZR, W0

0x428a24 ADD	X14, X15, #1

0x428a28 ADD	W7, W9, W2

0x428a2c AND	W23, W7, #0x7

0x428a30 STR	D4, [X5, X15,LSL #3]

0x428a34 CMP	W9, W14

0x428a38 B.LE	427d00

0x428a3c CBZ	W23, 428acc

0x428a40 CMP	W23, #1

0x428a44 B.EQ	428ab8

0x428a48 CMP	W23, #2

0x428a4c B.EQ	428aac

0x428a50 CMP	W23, #3

0x428a54 B.EQ	428aa0

0x428a58 CMP	W23, #4

0x428a5c B.EQ	428a94

0x428a60 CMP	W23, #5

0x428a64 B.EQ	428a88

0x428a68 CMP	W23, #6

0x428a6c B.EQ	428a7c

0x428a70 LDR	D21, [X8]

0x428a74 STR	D21, [X5, X14,LSL #3]

0x428a78 ADD	X14, X14, #1

0x428a7c LDR	D18, [X8]

0x428a80 STR	D18, [X5, X14,LSL #3]

0x428a84 ADD	X14, X14, #1

0x428a88 LDR	D24, [X8]

0x428a8c STR	D24, [X5, X14,LSL #3]

0x428a90 ADD	X14, X14, #1

0x428a94 LDR	D7, [X8]

0x428a98 STR	D7, [X5, X14,LSL #3]

0x428a9c ADD	X14, X14, #1

0x428aa0 LDR	D19, [X8]

0x428aa4 STR	D19, [X5, X14,LSL #3]

0x428aa8 ADD	X14, X14, #1

0x428aac LDR	D5, [X8]

0x428ab0 STR	D5, [X5, X14,LSL #3]

0x428ab4 ADD	X14, X14, #1

0x428ab8 LDR	D20, [X8]

0x428abc STR	D20, [X5, X14,LSL #3]

0x428ac0 ADD	X14, X14, #1

0x428ac4 CMP	W9, W14

0x428ac8 B.LE	427d00

(218) 0x428acc LDR	D6, [X8]

(218) 0x428ad0 ADD	X30, X14, #1

(218) 0x428ad4 ADD	X19, X14, #2

(218) 0x428ad8 ADD	X12, X14, #3

(218) 0x428adc ADD	X18, X14, #4

(218) 0x428ae0 ADD	X20, X14, #5

(218) 0x428ae4 ADD	X3, X14, #6

(218) 0x428ae8 ADD	X6, X14, #7

(218) 0x428aec STR	D6, [X5, X14,LSL #3]

(218) 0x428af0 ADD	X14, X14, #8

(218) 0x428af4 LDR	D3, [X8]

(218) 0x428af8 STR	D3, [X5, X30,LSL #3]

(218) 0x428afc LDR	D17, [X8]

(218) 0x428b00 STR	D17, [X5, X19,LSL #3]

(218) 0x428b04 LDR	D29, [X8]

(218) 0x428b08 STR	D29, [X5, X12,LSL #3]

(218) 0x428b0c LDR	D28, [X8]

(218) 0x428b10 STR	D28, [X5, X18,LSL #3]

(218) 0x428b14 LDR	D30, [X8]

(218) 0x428b18 STR	D30, [X5, X20,LSL #3]

(218) 0x428b1c LDR	D16, [X8]

(218) 0x428b20 STR	D16, [X5, X3,LSL #3]

(218) 0x428b24 LDR	D0, [X8]

(218) 0x428b28 STR	D0, [X5, X6,LSL #3]

(218) 0x428b2c CMP	W9, W14

(218) 0x428b30 B.GT	428acc

0x428b34 B	427d00

0x428b38 SUB	W27, W4, W27

0x428b3c LDR	D22, [X10]

0x428b40 ADD	X0, X9, X20,LSL #3

0x428b44 SBFM	X5, X4, #0, #31

0x428b48 ADD	W1, W23, W18

0x428b4c SCVTF	S24, W27

0x428b50 LDR	D23, [X12]

0x428b54 ORN	W2, WZR, W4

0x428b58 ADD	W4, W1, W2

0x428b5c ADD	X9, X5, #1

0x428b60 ADD	W3, W27, #1

0x428b64 AND	W6, W4, #0x7

0x428b68 FCVT	D3, S24

0x428b6c FMADD	D4, D23, D3, D22

0x428b70 STR	D4, [X0, X5,LSL #3]

0x428b74 CMP	W1, W9

0x428b78 B.LE	427614

0x428b7c CBZ	W6, 428c98

0x428b80 CMP	W6, #1

0x428b84 B.EQ	428c70

0x428b88 CMP	W6, #2

0x428b8c B.EQ	428c50

0x428b90 CMP	W6, #3

0x428b94 B.EQ	428c30

0x428b98 CMP	W6, #4

0x428b9c B.EQ	428c10

0x428ba0 CMP	W6, #5

0x428ba4 B.EQ	428bf0

0x428ba8 CMP	W6, #6

0x428bac B.EQ	428bd0

0x428bb0 SCVTF	S21, W3

0x428bb4 LDR	D19, [X10]

0x428bb8 ADD	W3, W3, #1

0x428bbc LDR	D20, [X12]

0x428bc0 FCVT	D5, S21

0x428bc4 FMADD	D6, D20, D5, D19

0x428bc8 STR	D6, [X0, X9,LSL #3]

0x428bcc ADD	X9, X9, #1

0x428bd0 SCVTF	S18, W3

0x428bd4 LDR	D16, [X10]

0x428bd8 ADD	W3, W3, #1

0x428bdc LDR	D17, [X12]

0x428be0 FCVT	D7, S18

0x428be4 FMADD	D31, D17, D7, D16

0x428be8 STR	D31, [X0, X9,LSL #3]

0x428bec ADD	X9, X9, #1

0x428bf0 SCVTF	S30, W3

0x428bf4 LDR	D28, [X10]

0x428bf8 ADD	W3, W3, #1

0x428bfc LDR	D0, [X12]

0x428c00 FCVT	D29, S30

0x428c04 FMADD	D1, D0, D29, D28

0x428c08 STR	D1, [X0, X9,LSL #3]

0x428c0c ADD	X9, X9, #1

0x428c10 SCVTF	S26, W3

0x428c14 LDR	D2, [X10]

0x428c18 ADD	W3, W3, #1

0x428c1c LDR	D25, [X12]

0x428c20 FCVT	D27, S26

0x428c24 FMADD	D24, D25, D27, D2

0x428c28 STR	D24, [X0, X9,LSL #3]

0x428c2c ADD	X9, X9, #1

0x428c30 SCVTF	S3, W3

0x428c34 LDR	D23, [X10]

0x428c38 ADD	W3, W3, #1

0x428c3c LDR	D4, [X12]

0x428c40 FCVT	D22, S3

0x428c44 FMADD	D21, D4, D22, D23

0x428c48 STR	D21, [X0, X9,LSL #3]

0x428c4c ADD	X9, X9, #1

0x428c50 SCVTF	S5, W3

0x428c54 LDR	D20, [X10]

0x428c58 ADD	W3, W3, #1

0x428c5c LDR	D6, [X12]

0x428c60 FCVT	D19, S5

0x428c64 FMADD	D18, D6, D19, D20

0x428c68 STR	D18, [X0, X9,LSL #3]

0x428c6c ADD	X9, X9, #1

0x428c70 SCVTF	S7, W3

0x428c74 LDR	D17, [X10]

0x428c78 ADD	W3, W3, #1

0x428c7c LDR	D31, [X12]

0x428c80 FCVT	D16, S7

0x428c84 FMADD	D30, D31, D16, D17

0x428c88 STR	D30, [X0, X9,LSL #3]

0x428c8c ADD	X9, X9, #1

0x428c90 CMP	W1, W9

0x428c94 B.LE	427614

(236) 0x428c98 SCVTF	S28, W3

(236) 0x428c9c LDR	D5, [X10]

(236) 0x428ca0 ADD	W11, W3, #1

(236) 0x428ca4 ADD	W15, W11, #1

(236) 0x428ca8 ADD	X7, X9, #1

(236) 0x428cac LDR	D19, [X12]

(236) 0x428cb0 SCVTF	S29, W11

(236) 0x428cb4 ADD	W8, W3, #3

(236) 0x428cb8 SCVTF	S0, W15

(236) 0x428cbc ADD	X16, X9, #2

(236) 0x428cc0 ADD	W13, W3, #4

(236) 0x428cc4 SCVTF	S1, W8

(236) 0x428cc8 ADD	X14, X9, #3

(236) 0x428ccc ADD	W23, W3, #5

(236) 0x428cd0 SCVTF	S27, W13

(236) 0x428cd4 ADD	X17, X9, #4

(236) 0x428cd8 ADD	W18, W3, #6

(236) 0x428cdc FCVT	D26, S28

(236) 0x428ce0 SCVTF	S25, W23

(236) 0x428ce4 ADD	X30, X9, #5

(236) 0x428ce8 SCVTF	S21, W18

(236) 0x428cec ADD	W27, W3, #7

(236) 0x428cf0 ADD	X5, X9, #6

(236) 0x428cf4 FCVT	D2, S29

(236) 0x428cf8 ADD	X2, X9, #7

(236) 0x428cfc ADD	W3, W3, #8

(236) 0x428d00 FCVT	D3, S0

(236) 0x428d04 SCVTF	S24, W27

(236) 0x428d08 FCVT	D22, S1

(236) 0x428d0c FCVT	D23, S27

(236) 0x428d10 FMADD	D20, D19, D26, D5

(236) 0x428d14 FCVT	D4, S25

(236) 0x428d18 FCVT	D18, S21

(236) 0x428d1c FCVT	D7, S24

(236) 0x428d20 STR	D20, [X0, X9,LSL #3]

(236) 0x428d24 ADD	X9, X9, #8

(236) 0x428d28 LDR	D6, [X10]

(236) 0x428d2c LDR	D16, [X12]

(236) 0x428d30 FMADD	D17, D16, D2, D6

(236) 0x428d34 STR	D17, [X0, X7,LSL #3]

(236) 0x428d38 LDR	D31, [X10]

(236) 0x428d3c LDR	D30, [X12]

(236) 0x428d40 FMADD	D28, D30, D3, D31

(236) 0x428d44 STR	D28, [X0, X16,LSL #3]

(236) 0x428d48 LDR	D29, [X10]

(236) 0x428d4c LDR	D0, [X12]

(236) 0x428d50 FMADD	D1, D0, D22, D29

(236) 0x428d54 STR	D1, [X0, X14,LSL #3]

(236) 0x428d58 LDR	D26, [X10]

(236) 0x428d5c LDR	D27, [X12]

(236) 0x428d60 FMADD	D2, D27, D23, D26

(236) 0x428d64 STR	D2, [X0, X17,LSL #3]

(236) 0x428d68 LDR	D25, [X10]

(236) 0x428d6c LDR	D3, [X12]

(236) 0x428d70 FMADD	D22, D3, D4, D25

(236) 0x428d74 STR	D22, [X0, X30,LSL #3]

(236) 0x428d78 LDR	D23, [X10]

(236) 0x428d7c LDR	D4, [X12]

(236) 0x428d80 FMADD	D21, D4, D18, D23

(236) 0x428d84 STR	D21, [X0, X5,LSL #3]

(236) 0x428d88 LDR	D24, [X10]

(236) 0x428d8c LDR	D18, [X12]

(236) 0x428d90 FMADD	D7, D18, D7, D24

(236) 0x428d94 STR	D7, [X0, X2,LSL #3]

(236) 0x428d98 CMP	W1, W9

(236) 0x428d9c B.GT	428c98

0x428da0 B	427614

Coverage (%)	Name	Source Location	Module
►98.36+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.64+	GOMP_parallel		libgomp.so.1.0.0
○	initialise_chunk_kernel	initialise_chunk_kernel.f90:135	exec
○	initialise_chunk	initialise_chunk.f90:80	exec
○	start	start.f90:106	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_0

Source file and lines	initialise_chunk_kernel.f90:58-129
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:58-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 164.00 to 58.00 cycles (2.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 164.00 to 137.50 cycles (1.19x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 12 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:58
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:58
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:67
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:79
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:85
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:91
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:97
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:103
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:120

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 16 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
SCVTF: 16 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 64 FP arithmetical operations:

32: addition or subtraction (16 inside FMA instructions)
32: multiply (16 inside FMA instructions)

The binary function is loading 84 bytes.

Arithmetic intensity

Arithmetic intensity is 0.76 FP operations per loaded or stored byte.

General properties

nb instructions	1147
nb uops	1137
loop length	4588
used w registers	28
used x registers	32
used b registers	0
used h registers	0
used s registers	17
used d registers	24
used q registers	0
used v registers	0
used z registers	15
nb stack references	30
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	142.13 cycles
front end	142.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	72.50	72.50	164.00	164.00	164.00	164.00	33.00	33.00	33.00	33.00	93.83	93.50	93.67	7.50	7.50
cycles	72.50	72.50	164.00	164.00	164.00	164.00	33.00	33.00	33.00	33.00	93.83	93.50	93.67	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

55.00-137.50

Cycles summary

Front-end	142.13
Dispatch	164.00
DIV/SQRT	55.00-137.50
Overall L1	164.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	23%
load	25%
store	26%
mul	12%
add-sub	20%
fma	12%
other	20%

all	21%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	22%
load	25%
store	26%
mul	22%
add-sub	22%
fma	22%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 164.00 cycles. At this rate:

0% of peak load performance is reached (0.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 427480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X24, X1, [X26, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [X26, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X20, X19, [X26, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X26, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X26, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X26, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X26, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X26, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X26, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X26, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W23, W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W28, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W25, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W12, W11, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W13, W12, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W14, W13, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W15, W14, W28, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fcc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W16, W14, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W17, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W18, W14, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427614 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X30, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X20, W27,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X1, X30, W15,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X2, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W5, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X3, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X3, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X6, W14,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X12, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X10, X8, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W13, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X12, X8, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W16, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ANDS WZR, W13, W16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
B.EQ 428b38 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL X23, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P5.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X18, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INDEX Z31.S, W4, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1	N/A
UQDECD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1RD {Z30.D}, P5/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z29.D}, P5/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z28.S, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
WHILELO P6.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
WHILELO P7.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W4, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W3, W6, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W15, W3, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W9, W15, W28, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 428020 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W11, W15, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD W7, W9, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X26, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X8, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X8, W9,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X14, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X17, W1,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X30, X18, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X27, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X27, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X5, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X23, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X12, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X12, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.HI 4283c4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xf44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W0, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W6, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 4276e0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W3, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X9, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z5.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
HINT #0																			N/A
CMP W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X18, W11,UXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X16, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X8, X23, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1RD {Z19.D}, P1/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W15, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P2.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X14, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W15, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W23, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W14, W15, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W27, W14, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W5, W27, W28, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fa8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W16, W27, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W17, W5, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W27, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42782c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X10, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X19, W18,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X2, X10, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X4, X12, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X26, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X6, W27,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X27, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X8, X5, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W13, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X5, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W16, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ANDS WZR, W13, W16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
B.EQ 428158 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL X23, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X30, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INDEX Z23.S, W0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1	N/A
UQDECD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1RD {Z4.D}, P3/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z21.D}, P3/Z, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z24.S, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
WHILELO P4.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
WHILELO P5.D, XZR, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X27, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W12, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W1, W0, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W7, W1, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W15, W7, W28, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 428014 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W6, W7, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD W5, W15, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W5, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X26, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X3, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X3, W15,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X14, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X17, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X18, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, W7,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X8, X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X23, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X27, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X27, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.HI 42802c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xbac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W12, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W11, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 427900 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W7, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X15, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z1.D}, P6/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X30, W5,UXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X16, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X3, X23, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1RD {Z26.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W7, W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P7.D, XZR, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X14, X3, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X3, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W23, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W10, W14, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W18, W10, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W9, W18, W28, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fe4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W16, W18, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W17, W9, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427a20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X27, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X2, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X26, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X27, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X3, X14, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X7, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X13, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 428814 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X23, X27, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X23, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X20, X20, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X24, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X17, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X7, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W18, WZR, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X27, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P1.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X2, X30, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X14, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X27, X4, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W0, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W8, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W12, W8, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W15, W12, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W5, W15, W28, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fc0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W30, W15, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD W7, W5, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W23, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X26, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X6, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X22, W0,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X14, X6, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X1, X3, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X18, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X16, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X24, X20, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X20, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X10, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X10, X8, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.HI 4286e8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W27, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W4, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 427ae4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W15, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X11, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z3.D}, P2/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CMP W15, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X3, W2,UXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X5, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X20, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W15, W15, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P4.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LD1RD {Z6.D}, P3/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X23, X30, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W5, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W15, W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W23, W7, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W6, W23, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W14, W6, W28, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fb4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W30, W6, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD W18, W14, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W6, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W18, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427c04 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X20, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X3, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X24, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X26, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X3, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X13, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [X26, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X17, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X27, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X12, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 4284f0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1070>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X15, X20, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W30, WZR, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P5.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X14, X15, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X19, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X6, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X27, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X23, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X20, X6, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X24, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X17, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X20, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W3, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W24, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W1, W13, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W4, W1, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W27, W4, W28, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427ff0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W16, W4, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W17, W27, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W11, W4, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X26, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X0, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X21, W3,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X15, X0, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X9, X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X2, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X7, W4,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X12, X14, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X14, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X30, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X10, X30, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 428a0c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x158c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X19, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W18, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W6, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W18, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 427cc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x848>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W20, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X3, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z27.D}, P6/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CMP W24, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X5, W24,UXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X27, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X14, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W4, W4, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P7.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LD1RD {Z23.D}, P0/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X11, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X24, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W10, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W13, W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W11, W13, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W0, W11, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W0, W28, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fd8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W0, W25, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W0, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W16, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427dd4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W9, W4, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W4, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X23, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W30, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W19, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X7, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W12, W30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X26, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W18, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W18, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427dd4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X20, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W3, W30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X24, X8, W19,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB W10, W3, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
MADD X4, X20, X13, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X27, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X14, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X15, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W23, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W12, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W19, W23, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W18, W19, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W7, W18, W28, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 428008 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W18, W25, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W18, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W16, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427eb0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X6, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W30, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W20, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [X26, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W27, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W4, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X26, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W27, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W10, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427eb0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X18, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X24, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W11, W27, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X0, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB W5, W11, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P8.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
MADD X2, X18, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X23, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X13, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X3, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W6, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W24, W6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W27, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W8, W24, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W4, W8, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W28, W4, W28, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W25, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427ffc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W25, W4, W25, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W16, W4, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427f8c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X30, X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W5, W27, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W17, W27, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X21, [X26, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X26, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W11, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W0, W15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427f8c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X23, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X1, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X22, X22, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X21, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W12, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P9.D, XZR, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X20, X7, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X19, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X24, X1, X3, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X6, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X26, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W27, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427744 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427b48 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427a4c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42752c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427d2c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427964 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427c30 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 427edc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427e00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427858 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427640 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W30, W11, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X23, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X10, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W18, W11, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W9, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W8, W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W27, W8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D27, [X23, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W18, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W27, 4280ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280d8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280c0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280b4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42809c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D2, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D2, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D3, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D22, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D23, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D4, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D21, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D18, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W18, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W18, W0, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X12, X1, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X9, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W23, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S16, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D30, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORN W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W1, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W11, W0, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCVT D17, S16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D28, D30, D17, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D28, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W4, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 42782c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W11, 4282b8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428290 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428270 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428250 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428230 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428210 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xd90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4281f0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xd70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SCVTF S29, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D0, S29	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D27, D26, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D27, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S2, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D3, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D25, S2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D23, D22, D25, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D23, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S4, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D21, S4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D7, D18, D21, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D7, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S19, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D5, S19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D16, D6, D5, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D16, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S17, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D30, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D31, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D29, D28, D31, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D29, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D1, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D2, D27, D1, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D2, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S25, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D22, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D3, S25	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D4, D23, D3, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D4, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W4, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 42782c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42782c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W18, W4, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X23, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X30, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W27, W4, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W5, WZR, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W27, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W12, W10, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D20, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W27, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W12, 428484 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428470 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428464 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428458 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42844c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428440 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428434 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D6, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D16, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D17, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D31, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D28, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D29, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D29, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W27, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X17, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W15, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D27, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SBFM X11, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X27, X27, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W2, WZR, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W8, W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W5, W8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D5, D7, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D20, D5, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D20, [X27, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427c04 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W5, 42861c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x119c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4285fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x117c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4285e4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4285cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x114c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4285b4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42859c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x111c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428584 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D3, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D17, D6, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D29, D17, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D29, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D30, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D16, D28, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D0, D16, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D0, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D25, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D1, D31, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D26, D1, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D26, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D22, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D23, D2, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D4, D23, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D4, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D18, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D24, D21, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D7, D24, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D7, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D5, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D20, D19, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D6, D20, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D6, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D17, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D3, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D28, D29, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D28, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427c04 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427c04 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X18, X20, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W11, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X3, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W11, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORN W1, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W16, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W20, W13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D17, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W16, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W20, 4287a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428794 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428788 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42877c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428770 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428764 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428758 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D29, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D29, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D28, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D16, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D31, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D25, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W16, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X14, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W15, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D3, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SBFM X5, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X7, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W23, W23, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W6, WZR, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X0, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W14, W23, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W1, W14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X3, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D31, D16, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D25, D31, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D25, [X7, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W23, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427a20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W1, 428940 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x14c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428920 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x14a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428908 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4288f0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4288d8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4288c0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4288a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D26, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D27, D1, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D2, D27, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D2, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D23, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D4, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D21, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D21, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D24, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D7, D18, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D19, D7, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D19, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D20, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D6, D5, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D17, D6, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D17, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D29, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D28, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D30, D29, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D16, D30, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D16, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D31, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D25, D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D1, D25, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D1, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D27, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D2, D26, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D22, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D22, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W23, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427a20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427a20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X5, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W24, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X15, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W24, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W9, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W23, W7, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D4, [X5, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W9, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W23, 428acc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x164c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428ab8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428aac <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x162c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428aa0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428a94 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428a88 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428a7c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x15fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D21, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D18, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D24, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D7, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D19, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D5, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D20, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W9, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W27, W4, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X9, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X5, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W1, W23, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S24, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D23, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORN W2, WZR, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W6, W4, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCVT D3, S24	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D4, D23, D3, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D4, [X0, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W1, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427614 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W6, 428c98 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1818>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428c70 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428c50 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428c30 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428c10 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428bf0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428bd0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1750>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SCVTF S21, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D5, S21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D6, D20, D5, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D6, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S18, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D16, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D7, S18	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D31, D17, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D31, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S30, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D28, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D29, S30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D1, D0, D29, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D1, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S26, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D2, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D24, D25, D27, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D24, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S3, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D22, S3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D21, D4, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D21, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S5, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D19, S5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D18, D6, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D18, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S7, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D17, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D16, S7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D30, D31, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D30, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W1, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 427614 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427614 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_0

Source file and lines	initialise_chunk_kernel.f90:58-129
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

unknown: 12 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:58
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:58
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:67
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:79
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:85
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:91
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:97
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:103
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:120

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 16 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
SCVTF: 16 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:73
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:61

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 64 FP arithmetical operations:

32: addition or subtraction (16 inside FMA instructions)
32: multiply (16 inside FMA instructions)

The binary function is loading 84 bytes.

Arithmetic intensity

Arithmetic intensity is 0.76 FP operations per loaded or stored byte.

General properties

nb instructions	1147
nb uops	1137
loop length	4588
used w registers	28
used x registers	32
used b registers	0
used h registers	0
used s registers	17
used d registers	24
used q registers	0
used v registers	0
used z registers	15
nb stack references	30
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	142.13 cycles
front end	142.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	72.50	72.50	164.00	164.00	164.00	164.00	33.00	33.00	33.00	33.00	93.83	93.50	93.67	7.50	7.50
cycles	72.50	72.50	164.00	164.00	164.00	164.00	33.00	33.00	33.00	33.00	93.83	93.50	93.67	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

55.00-137.50

Cycles summary

Front-end	142.13
Dispatch	164.00
DIV/SQRT	55.00-137.50
Overall L1	164.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	23%
load	25%
store	26%
mul	12%
add-sub	20%
fma	12%
other	20%

all	21%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	22%
load	25%
store	26%
mul	22%
add-sub	22%
fma	22%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 164.00 cycles. At this rate:

0% of peak load performance is reached (0.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 427480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X24, X1, [X26, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [X26, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X20, X19, [X26, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X26, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X26, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X26, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X26, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X26, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X26, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X26, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W23, W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W28, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410330 <@plt_start@+0x310>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W25, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W12, W11, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W13, W12, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W14, W13, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W15, W14, W28, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fcc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W16, W14, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W17, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W18, W14, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427614 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X30, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X20, W27,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X1, X30, W15,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X2, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W5, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X3, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X3, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X6, W14,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X12, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X10, X8, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W13, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X12, X8, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W16, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ANDS WZR, W13, W16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
B.EQ 428b38 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL X23, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P5.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X18, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INDEX Z31.S, W4, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1	N/A
UQDECD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1RD {Z30.D}, P5/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z29.D}, P5/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z28.S, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
WHILELO P6.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
WHILELO P7.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W4, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W3, W6, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W15, W3, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W9, W15, W28, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 428020 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W11, W15, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD W7, W9, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X26, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X8, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X8, W9,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X14, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X17, W1,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X30, X18, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X27, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X27, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X5, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X23, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X12, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X12, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.HI 4283c4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xf44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W0, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W6, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 4276e0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W3, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X9, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z5.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
HINT #0																			N/A
CMP W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X18, W11,UXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X16, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X8, X23, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1RD {Z19.D}, P1/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W15, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P2.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X14, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W15, W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W23, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W14, W15, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W27, W14, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W5, W27, W28, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fa8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W16, W27, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W17, W5, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W27, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42782c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X10, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X19, W18,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X2, X10, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X4, X12, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X26, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X6, W27,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X27, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X8, X5, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W13, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X27, X5, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W16, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ANDS WZR, W13, W16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
B.EQ 428158 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL X23, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X30, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INDEX Z23.S, W0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1	N/A
UQDECD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1RD {Z4.D}, P3/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z21.D}, P3/Z, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z24.S, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
WHILELO P4.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
WHILELO P5.D, XZR, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X27, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W12, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W1, W0, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W7, W1, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W15, W7, W28, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 428014 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W6, W7, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD W5, W15, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W5, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X26, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X3, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X3, W15,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X14, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X17, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X18, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, W7,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X8, X23, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X23, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X27, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X27, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.HI 42802c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xbac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W12, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W11, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 427900 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W7, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X15, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z1.D}, P6/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X30, W5,UXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X16, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X3, X23, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1RD {Z26.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W7, W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P7.D, XZR, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X14, X3, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X3, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W23, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W10, W14, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W18, W10, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W9, W18, W28, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fe4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W16, W18, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W17, W9, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427a20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X27, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X2, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X26, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X27, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X3, X14, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X6, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X7, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X13, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 428814 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X23, X27, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X23, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X20, X20, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X24, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X17, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X7, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W18, WZR, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X27, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P1.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X2, X30, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X14, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X27, X4, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W0, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W8, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W12, W8, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W15, W12, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W5, W15, W28, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fc0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W30, W15, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD W7, W5, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W23, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X26, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X6, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X22, W0,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X14, X6, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X1, X3, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X18, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X16, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X24, X20, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X20, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X10, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X10, X8, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.HI 4286e8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W27, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W4, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 427ae4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W15, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X11, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z3.D}, P2/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CMP W15, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X3, W2,UXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X5, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X20, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W15, W15, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P4.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LD1RD {Z6.D}, P3/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X23, X30, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W5, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W15, W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W23, W7, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W6, W23, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W14, W6, W28, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fb4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W30, W6, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD W18, W14, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W6, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W18, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427c04 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X20, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X3, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X24, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X26, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X3, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X13, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [X26, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X17, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X27, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X12, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 4284f0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1070>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X15, X20, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W30, WZR, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P5.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X14, X15, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X19, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X6, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X27, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X23, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X20, X6, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X24, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X17, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X20, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W3, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W24, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W1, W13, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W4, W1, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W27, W4, W28, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427ff0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL W16, W4, W25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W17, W27, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W11, W4, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X26, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X0, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X21, W3,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X15, X0, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X9, X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X2, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X7, W4,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X12, X14, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X14, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X30, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X10, X30, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 428a0c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x158c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTW X19, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W18, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W6, W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W18, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 427cc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x848>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W20, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X3, ALL, MUL #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z27.D}, P6/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CMP W24, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X5, W24,UXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X27, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X14, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W4, W4, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P7.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LD1RD {Z23.D}, P0/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X11, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X24, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W10, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W13, W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W11, W13, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W0, W11, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W0, W28, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427fd8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W0, W25, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W0, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W16, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427dd4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W9, W4, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W4, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X23, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W30, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W19, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X7, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W12, W30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X26, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W18, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W18, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427dd4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x954>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X20, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X6, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W3, W30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X24, X8, W19,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB W10, W3, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
MADD X4, X20, X13, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X27, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X14, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X15, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W23, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W12, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W19, W23, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W18, W19, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W7, W18, W28, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W25, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 428008 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W18, W25, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W18, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W16, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427eb0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X6, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W30, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W20, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [X26, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W27, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W4, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X26, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W27, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W10, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427eb0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X18, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X24, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W11, W27, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X0, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB W5, W11, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P8.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
MADD X2, X18, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X23, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X13, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
BL 4103a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X3, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W6, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W24, W6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W27, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W8, W24, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W4, W8, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W28, W4, W28, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W25, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 427ffc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W25, W4, W25, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W16, W4, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427f8c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X30, X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W5, W27, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W17, W27, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X21, [X26, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X26, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W11, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W0, W15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 427f8c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X23, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X1, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X22, X22, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X21, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W12, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P9.D, XZR, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X20, X7, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X19, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X24, X1, X3, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X6, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X26, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W27, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427744 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427b48 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427a4c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42752c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427d2c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427964 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427c30 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 427edc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427e00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427858 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 427640 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W30, W11, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X23, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X10, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W18, W11, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W9, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W8, W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W27, W8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D27, [X23, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W18, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W27, 4280ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280d8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280c0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280b4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4280a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W27, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42809c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D2, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D2, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D3, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D22, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D23, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D4, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D21, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D18, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W18, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427938 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W18, W0, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X12, X1, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X9, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W23, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S16, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D30, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORN W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W1, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W11, W0, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCVT D17, S16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D28, D30, D17, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D28, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W4, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 42782c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W11, 4282b8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428290 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428270 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428250 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428230 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428210 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xd90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4281f0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xd70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SCVTF S29, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D0, S29	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D27, D26, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D27, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S2, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D3, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D25, S2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D23, D22, D25, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D23, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S4, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D21, S4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D7, D18, D21, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D7, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S19, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D5, S19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D16, D6, D5, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D16, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S17, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D30, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D31, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D29, D28, D31, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D29, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D1, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D2, D27, D1, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D2, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S25, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D22, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D3, S25	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D4, D23, D3, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D4, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W4, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 42782c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42782c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W18, W4, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X23, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X30, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W27, W4, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W5, WZR, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W27, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W12, W10, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D20, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W27, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W12, 428484 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1004>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428470 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428464 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428458 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42844c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428440 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428434 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D6, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D16, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D17, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D31, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D28, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D29, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D29, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W27, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427718 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X17, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W15, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D27, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SBFM X11, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X27, X27, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W2, WZR, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W8, W0, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W5, W8, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D5, D7, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D20, D5, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D20, [X27, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427c04 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W5, 42861c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x119c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4285fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x117c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4285e4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4285cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x114c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4285b4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42859c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x111c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428584 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D3, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D17, D6, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D29, D17, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D29, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D30, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D16, D28, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D0, D16, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D0, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D25, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D1, D31, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D26, D1, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D26, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D22, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D23, D2, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D4, D23, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D4, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D18, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D24, D21, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D7, D24, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D7, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D5, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D20, D19, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D6, D20, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D6, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D17, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D29, D3, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D28, D29, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D28, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427c04 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427c04 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X18, X20, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W11, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X3, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W11, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORN W1, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W16, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W20, W13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D17, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W16, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W20, 4287a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428794 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428788 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42877c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428770 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428764 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428758 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D29, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D29, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D28, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D30, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D16, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D31, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D25, [X18, X24,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W16, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427b1c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X14, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W15, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D3, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SBFM X5, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X7, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W23, W23, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W6, WZR, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X0, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W14, W23, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W1, W14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X3, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D31, D16, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D25, D31, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D25, [X7, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W23, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427a20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W1, 428940 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x14c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428920 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x14a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428908 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4288f0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4288d8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4288c0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4288a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D26, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D27, D1, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D2, D27, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D2, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D23, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D4, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D21, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D21, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D24, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D7, D18, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D19, D7, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D19, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D20, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D6, D5, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D17, D6, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D17, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D29, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D28, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D30, D29, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D16, D30, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D16, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D31, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D25, D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D1, D25, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D1, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D27, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D2, D26, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D22, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D22, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W23, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427a20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427a20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X5, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W0, W24, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X15, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W24, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W9, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W23, W7, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D4, [X5, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W9, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W23, 428acc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x164c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428ab8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428aac <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x162c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428aa0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428a94 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428a88 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428a7c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x15fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D21, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D18, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D24, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D7, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D19, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D5, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D20, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W9, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427d00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x880>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W27, W4, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X9, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X5, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W1, W23, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S24, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D23, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORN W2, WZR, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND W6, W4, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCVT D3, S24	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D4, D23, D3, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D4, [X0, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP W1, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 427614 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W6, 428c98 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1818>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428c70 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428c50 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428c30 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428c10 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428bf0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 428bd0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1750>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SCVTF S21, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D5, S21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D6, D20, D5, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D6, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S18, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D16, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D7, S18	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D31, D17, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D31, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S30, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D28, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D29, S30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D1, D0, D29, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D1, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S26, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D2, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D24, D25, D27, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D24, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S3, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D22, S3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D21, D4, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D21, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S5, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D19, S5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D18, D6, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D18, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SCVTF S7, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LDR D17, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCVT D16, S7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
FMADD D30, D31, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D30, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W1, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 427614 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 427614 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0–	0.02	0.02
○Loop 233 - initialise_chunk_kernel.f90:67-67 - exec	0.00	0.00
○Loop 221 - initialise_chunk_kernel.f90:97-97 - exec	0.00	0.00
○Loop 219 - initialise_chunk_kernel.f90:103-103 - exec	0.00	0.00
○Loop 220 - initialise_chunk_kernel.f90:103-103 - exec	0.00	0.00
○Loop 222 - initialise_chunk_kernel.f90:97-97 - exec	0.00	0.00
○Loop 224 - initialise_chunk_kernel.f90:91-91 - exec	0.00	0.00
○Loop 227 - initialise_chunk_kernel.f90:85-85 - exec	0.00	0.00
○Loop 218 - initialise_chunk_kernel.f90:103-103 - exec	0.00	0.00
○Loop 235 - initialise_chunk_kernel.f90:67-67 - exec	0.00	0.00
○Loop 231 - initialise_chunk_kernel.f90:73-73 - exec	0.00	0.00
○Loop 236 - initialise_chunk_kernel.f90:61-61 - exec	0.00	0.00
○Loop 229 - initialise_chunk_kernel.f90:79-79 - exec	0.00	0.00
○Loop 232 - initialise_chunk_kernel.f90:73-73 - exec	0.00	0.00
○Loop 226 - initialise_chunk_kernel.f90:85-85 - exec	0.00	0.00
▼Loop 217 - initialise_chunk_kernel.f90:107-111 - exec–	0.00	0.00
○Loop 216 - initialise_chunk_kernel.f90:111-111 - exec	0.00	0.00
▼Loop 213 - initialise_chunk_kernel.f90:125-129 - exec–	0.00	0.00
○Loop 212 - initialise_chunk_kernel.f90:129-129 - exec	0.00	0.00
○Loop 234 - initialise_chunk_kernel.f90:67-67 - exec	0.00	0.00
○Loop 223 - initialise_chunk_kernel.f90:91-91 - exec	0.00	0.00
▼Loop 215 - initialise_chunk_kernel.f90:116-120 - exec–	0.00	0.00
○Loop 214 - initialise_chunk_kernel.f90:120-120 - exec	0.00	0.00
○Loop 225 - initialise_chunk_kernel.f90:91-91 - exec	0.00	0.00
○Loop 230 - initialise_chunk_kernel.f90:79-79 - exec	0.00	0.00
○Loop 228 - initialise_chunk_kernel.f90:79-79 - exec	0.00	0.00
○Loop 237 - initialise_chunk_kernel.f90:61-61 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

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Back-end

Cycles summary

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Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

CALL instructions

Details

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code