OV - exec - Loop 107

0x421380 ADD	X17, X27, #1

0x421384 SUB	X25, X10, #1

0x421388 ADD	X26, X1, X17

0x42138c ORR	X7, XZR, X27

0x421390 B	421398

  (106) 0x421394 ADD	X17, X17, #1

  (106) 0x421398 LDR	D24, [X15, X7,LSL #3]

  (106) 0x42139c SBFM	X4, X16, #0, #31

  (106) 0x4213a0 ORR	X28, XZR, X10

  (106) 0x4213a4 ORR	X12, XZR, X25

  (106) 0x4213a8 ORR	W20, WZR, W13

  (106) 0x4213ac FCMPE	D24, #0

  (106) 0x4213b0 B.MI	4213c4

  (106) 0x4213b4 SBFM	X4, X11, #0, #31

  (106) 0x4213b8 ORR	X12, XZR, X10

  (106) 0x4213bc ORR	X28, XZR, X25

  (106) 0x4213c0 ORR	W20, WZR, W11

  (106) 0x4213c4 ADD	X3, X19, X7

  (106) 0x4213c8 ADD	X5, X21, X7

  (106) 0x4213cc MOVI	D17, #0

  (106) 0x4213d0 FABS	D3, D24

  (106) 0x4213d4 ADD	X20, X24, W20,SXTW

  (106) 0x4213d8 MADD	X4, X4, X22, X3

  (106) 0x4213dc MADD	X12, X22, X12, X3

  (106) 0x4213e0 MADD	X3, X22, X28, X3

  (106) 0x4213e4 LDR	D7, [X9, X4,LSL #3]

  (106) 0x4213e8 MADD	X28, X23, X28, X5

  (106) 0x4213ec LDR	D5, [X9, X3,LSL #3]

  (106) 0x4213f0 LDR	D2, [X9, X12,LSL #3]

  (106) 0x4213f4 LDR	D6, [X18, X28,LSL #3]

  (106) 0x4213f8 FSUB	D23, D5, S7

  (106) 0x4213fc FSUB	D22, D2, S5

  (106) 0x421400 FDIV	D18, D3, D6

  (106) 0x421404 FABS	D31, D23

  (106) 0x421408 FMUL	D16, D23, D22

  (106) 0x42140c FCMPE	D16, D17

  (106) 0x421410 B.GT	421ac0

  (106) 0x421414 FSUB	D18, D26, S18

  (106) 0x421418 FMADD	D5, D17, D18, D5

  (106) 0x42141c FMUL	D24, D24, D5

  (106) 0x421420 STR	D24, [X14, X7,LSL #3]

  (106) 0x421424 ORR	X7, XZR, X17

  (106) 0x421428 CMP	X26, X17

  (106) 0x42142c B.NE	421394

0x421430 LDR	X25, [SP, #128]

0x421434 ADD	X10, X10, #1

0x421438 ADD	W16, W16, #1

0x42143c ADD	W11, W11, #1

0x421440 LDR	X26, [SP, #136]

0x421444 LDR	W20, [SP, #120]

0x421448 ADD	X14, X14, X25

0x42144c ADD	X15, X15, X26

0x421450 CMP	W20, W13

0x421454 B.LE	421460

0x421458 ADD	W13, W13, #1

0x42145c B	421380

  (106) 0x421ac0 FSUB	D29, D19, S18

  (106) 0x421ac4 FADD	D0, D18, D26

  (106) 0x421ac8 LDR	D30, [X30, X10,LSL #3]

  (106) 0x421acc FABS	D17, D22

  (106) 0x421ad0 FCMPE	D22, #0

  (106) 0x421ad4 FMINNM	D4, D31, D17

  (106) 0x421ad8 LDR	D21, [X0, X20,LSL #3]

  (106) 0x421adc FMUL	D28, D29, D17

  (106) 0x421ae0 FMUL	D27, D0, D31

  (106) 0x421ae4 FCSEL	D1, D20, D26, #9

  (106) 0x421ae8 FDIV	D3, D28, D30

  (106) 0x421aec FDIV	D7, D27, D21

  (106) 0x421af0 FADD	D2, D7, D3

  (106) 0x421af4 FMUL	D6, D2, D30

  (106) 0x421af8 FDIV	D23, D6, D25

  (106) 0x421afc FMINNM	D22, D23, D4

  (106) 0x421b00 FMUL	D17, D22, D1

  (106) 0x421b04 B	421414

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 214 - 240

--------------------------------------------------------------------------------

214:         DO j=x_min,x_max+1

215:           IF(node_flux(j,k).LT.0.0)THEN

216:             upwind=k+2

217:             donor=k+1

218:             downwind=k

219:             dif=donor

220:           ELSE

221:             upwind=k-1

222:             donor=k

223:             downwind=k+1

224:             dif=upwind

225:           ENDIF

226:

227:           sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor))

228:           width=celldy(k)

229:           vdiffuw=vel1(j,donor)-vel1(j,upwind)

230:           vdiffdw=vel1(j,downwind)-vel1(j,donor)

231:           limiter=0.0

232:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

233:             auw=ABS(vdiffuw)

234:             adw=ABS(vdiffdw)

235:             wind=1.0_8

236:             IF(vdiffdw.LE.0.0) wind=-1.0_8

237:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw)

238:           ENDIF

239:           advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter

240:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P2, P3, P4, P5,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:214-215,advec_mom_kernel.f90:237-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.56
Front-end cycles	2.13
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.09
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.15
Vector-efficiency ratio load	20.83
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P2, P3, P4, P5,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:214-215,advec_mom_kernel.f90:237-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.56
Front-end cycles	2.13
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.09
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.15
Vector-efficiency ratio load	20.83
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:214-240
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214-240.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214-215,237.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.56 cycles (4.89x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 3 bytes.

General properties

nb instructions	17
nb uops	17
loop length	68
used w registers	4
used x registers	10
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.13 cycles
front end	2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00
cycles	1.50	1.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Dispatch	2.75
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	21%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

1% of peak load performance is reached (1.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X17, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
SUB X25, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X26, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ORR X7, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B 421398 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x8b8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
LDR X26, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR W20, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
ADD X14, X14, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X15, X15, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W20, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.LE 421460 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B 421380 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x8a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:214-240
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214-240.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214-215,237.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.56 cycles (4.89x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 3 bytes.

General properties

nb instructions	17
nb uops	17
loop length	68
used w registers	4
used x registers	10
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.13 cycles
front end	2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00
cycles	1.50	1.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Dispatch	2.75
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	21%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

1% of peak load performance is reached (1.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X17, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
SUB X25, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X26, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ORR X7, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B 421398 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x8b8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
LDR X26, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR W20, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
ADD X14, X14, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X15, X15, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP W20, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.LE 421460 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B 421380 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x8a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

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ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code