OV - exec - Loop 157

	Loop Id: 157	Module: exec	Source: calc_dt_kernel.f90:93-129	Coverage: 4.36%

0x4236c4 FMOV	D30, D23

0x4236c8 FMOV	D26, D22

0x4236cc LDR	D1, [X4, X1,LSL #3]    [10]

0x4236d0 FMOV	D3, D28

0x4236d4 FABS	D4, D28

0x4236d8 LDR	D29, [X2, X1,LSL #3]    [9]

0x4236dc LDR	D2, [X3, X1,LSL #3]    [14]

0x4236e0 LDR	D22, [X6, X1,LSL #3]    [12]

0x4236e4 FADD	D14, D1, D29

0x4236e8 LDR	D15, [X10, X1,LSL #3]    [1]

0x4236ec LDR	D23, [X5, X1,LSL #3]    [11]

0x4236f0 FADD	D24, D22, D26

0x4236f4 LDR	D26, [X7, X1,LSL #3]    [3]

0x4236f8 FMUL	D28, D14, D2

0x4236fc LDR	D0, [X9, X1,LSL #3]    [5]

0x423700 LDR	D27, [X11, X1,LSL #3]    [2]

0x423704 FADD	D25, D23, D30

0x423708 FADD	D1, D26, D26

0x42370c FMUL	D24, D24, D15

0x423710 LDR	D2, [X28, X1,LSL #3]    [13]

0x423714 FMINNM	D14, D2, D7

0x423718 FADD	D31, D28, D6

0x42371c LDR	D29, [X12, X1,LSL #3]    [8]

0x423720 FABS	D15, D28

0x423724 FMUL	D25, D25, D27

0x423728 FMUL	D27, D14, D16

0x42372c LDR	D30, [X8, X1,LSL #3]    [4]

0x423730 FDIV	D26, D1, D0

0x423734 FABS	D14, D24

0x423738 FSUB	D31, D31, S3

0x42373c FADD	D2, D29, D29

0x423740 FABS	D3, D25

0x423744 FMAXNM	D14, D3, D14

0x423748 FMUL	D1, D29, D19

0x42374c FMUL	D0, D29, D18

0x423750 FMUL	D29, D21, D29

0x423754 FADD	D24, D31, D24

0x423758 FMAXNM	D3, D14, D29

0x42375c FMAXNM	D14, D4, D29

0x423760 FMAXNM	D15, D14, D15

0x423764 FDIV	D4, D1, D3

0x423768 FSUB	D25, D24, S25

0x42376c FMADD	D30, D30, D30, D26

0x423770 FDIV	D1, D0, D15

0x423774 FDIV	D26, D25, D2

0x423778 FSQRT	D2, D30

0x42377c FMAXNM	D31, D2, D21

0x423780 FDIV	D27, D27, D31

0x423784 FMINNM	D29, D4, D27

0x423788 FCMPE	D26, D17

0x42378c B.MI	42383c

0x423790 ADD	X1, X1, #1

0x423794 LDR	D0, [X30]    [7]

0x423798 FMINNM	D3, D1, D0

0x42379c FMINNM	D14, D3, D29

0x4237a0 FMINNM	D20, D20, D14

0x4237a4 CMP	W13, W1

0x4237a8 B.GE	4236c4

0x42383c FDIV	D4, D5, D26

0x423840 LDR	D15, [X18]    [6]

0x423844 ADD	X1, X1, #1

0x423848 FNMUL	D24, D4, D15

0x42384c FMINNM	D1, D24, D1

0x423850 FMINNM	D25, D1, D29

0x423854 FMINNM	D20, D20, D25

0x423858 CMP	W13, W1

0x42385c B.GE	4236c4

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 93 - 129

--------------------------------------------------------------------------------

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

Coverage (%)	Name	Source Location	Module
►98.42+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	GOMP_parallel		libgomp.so.1.0.0
○	calc_dt_kernel	calc_dt_kernel.f90:89	exec
○	calc_dt	calc_dt.f90:81	exec
○	timestep	timestep.f90:87	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.63 - 5.30
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08 - 2.19
Bottlenecks
Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source	calc_dt_kernel.f90:93-129
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.38 - 22.98
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	5.75 - 11.49
CQA cycles if fully vectorized	5.69 - 11.49
Front-end cycles	7.38
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	10.50
P7 cycles	10.50
P8 cycles	10.50
P9 cycles	10.50
P10 cycles	4.33
P11 cycles	4.33
P12 cycles	4.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	11.38 - 22.98
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.15 - 1.07
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	1.00
Nb FLOP div	5.50
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	12.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	2.42 - 4.90
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03 - 2.07
Bottlenecks	P6, P8,
Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source	calc_dt_kernel.f90:93-129
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.51 - 21.23
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	5.38 - 10.61
CQA cycles if fully vectorized	5.25 - 10.61
Front-end cycles	7.25
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	10.25
P7 cycles	10.25
P8 cycles	10.25
P9 cycles	10.25
P10 cycles	4.33
P11 cycles	4.33
P12 cycles	4.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	10.51 - 21.23
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.28 - 1.13
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	1.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	12.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	2.83 - 5.71
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14 - 2.30
Bottlenecks	P6, P8,
Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source	calc_dt_kernel.f90:93-129
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.26 - 24.72
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	6.13 - 12.36
CQA cycles if fully vectorized	6.13 - 12.36
Front-end cycles	7.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	10.75
P7 cycles	10.75
P8 cycles	10.75
P9 cycles	10.75
P10 cycles	4.33
P11 cycles	4.33
P12 cycles	4.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	12.26 - 24.72
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.04 - 1.01
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	1.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	12.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source file and lines	calc_dt_kernel.f90:93-129
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:93-129.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 22.98 to 11.49 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.98 to 8.88 cycles (2.59x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 12 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24.5 FP arithmetical operations:

10: addition or subtraction (1 inside FMA instructions)
8: multiply (1 inside FMA instructions)
5.50: divide
1: square root

The binary loop does not load or store any data.

General properties

nb instructions	59
nb uops	59
loop length	236
used w registers	2
used x registers	14
used b registers	0
used h registers	0
used s registers	2
used d registers	25.50
used q registers	0
used v registers	0
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	7.38 cycles
front end	7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.50	0.50	0.50	0.50	10.50	10.50	10.50	10.50	4.33	4.33	4.33	0.00	0.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	10.50	10.50	10.50	10.50	4.33	4.33	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	11.38-22.98
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.38
Dispatch	10.50
DIV/SQRT	11.38-22.98
Data deps.	2.00
Overall L1	11.38-22.98

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.98 cycles.

Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source file and lines	calc_dt_kernel.f90:93-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.23 to 4.33 cycles (4.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 21.23 to 10.61 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 21.23 to 8.75 cycles (2.43x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 12 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

10: addition or subtraction (1 inside FMA instructions)
8: multiply (1 inside FMA instructions)
5: divide
1: square root

The binary loop does not load or store any data.

General properties

nb instructions	58
nb uops	58
loop length	232
used w registers	2
used x registers	14
used b registers	0
used h registers	0
used s registers	2
used d registers	25
used q registers	0
used v registers	0
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.50	0.50	0.50	0.50	10.25	10.25	10.25	10.25	4.33	4.33	4.33	0.00	0.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	10.25	10.25	10.25	10.25	4.33	4.33	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	10.51-21.23
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.25
Dispatch	10.25
DIV/SQRT	10.51-21.23
Data deps.	2.00
Overall L1	10.51-21.23

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.23 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4236cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
FMOV D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV D26, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D1, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV D3, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D4, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D29, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D14, D1, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D15, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D23, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D24, D22, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D26, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D28, D14, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D27, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D25, D23, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D1, D26, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D24, D24, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D2, [X28, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMINNM D14, D2, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D31, D28, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D29, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FABS D15, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D25, D25, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D27, D14, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D30, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D26, D1, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FABS D14, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D31, D31, S3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D2, D29, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D3, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMAXNM D14, D3, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D1, D29, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D0, D29, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D29, D21, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FADD D24, D31, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMAXNM D3, D14, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMAXNM D14, D4, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMAXNM D15, D14, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D4, D1, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D25, D24, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D30, D30, D30, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D1, D0, D15	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FDIV D26, D25, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSQRT D2, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FMAXNM D31, D2, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D27, D27, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMINNM D29, D4, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMPE D26, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 42383c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMINNM D3, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMINNM D14, D3, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMINNM D20, D20, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4236c4 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0
Source file and lines	calc_dt_kernel.f90:93-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.72 to 4.33 cycles (5.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 24.72 to 12.36 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.72 to 9.00 cycles (2.75x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 12 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

10: addition or subtraction (1 inside FMA instructions)
8: multiply (1 inside FMA instructions)
6: divide
1: square root

The binary loop does not load or store any data.

General properties

nb instructions	60
nb uops	60
loop length	240
used w registers	2
used x registers	14
used b registers	0
used h registers	0
used s registers	2
used d registers	26
used q registers	0
used v registers	0
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.50	0.50	0.50	0.50	10.75	10.75	10.75	10.75	4.33	4.33	4.33	0.00	0.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	10.75	10.75	10.75	10.75	4.33	4.33	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	12.26-24.72
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.50
Dispatch	10.75
DIV/SQRT	12.26-24.72
Data deps.	2.00
Overall L1	12.26-24.72

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.72 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4236cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
FMOV D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMOV D26, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D1, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV D3, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D4, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D29, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D14, D1, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D15, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D23, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D24, D22, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D26, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D28, D14, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D27, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D25, D23, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D1, D26, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D24, D24, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D2, [X28, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMINNM D14, D2, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D31, D28, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D29, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FABS D15, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D25, D25, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D27, D14, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D30, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D26, D1, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FABS D14, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D31, D31, S3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D2, D29, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D3, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMAXNM D14, D3, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D1, D29, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D0, D29, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D29, D21, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FADD D24, D31, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMAXNM D3, D14, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMAXNM D14, D4, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMAXNM D15, D14, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D4, D1, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D25, D24, S25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D30, D30, D30, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D1, D0, D15	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FDIV D26, D25, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSQRT D2, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1.75-3.75	scal (25.0%)
FMAXNM D31, D2, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D27, D27, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMINNM D29, D4, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMPE D26, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 42383c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D4, D5, D26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D15, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FNMUL D24, D4, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D1, D24, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMINNM D25, D1, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMINNM D20, D20, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4236c4 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code