OV - exec - Loop 165

	Loop Id: 165	Module: exec	Source: field_summary_kernel.f90:62-71	Coverage: 0.34%

0x424928 LD1D	{Z4.D}, P7/Z, [X12, X1,LSL #3]    [6]

0x42492c LD1D	{Z0.D}, P7/Z, [X0, X1,LSL #3]    [10]

0x424930 LD1D	{Z24.D}, P7/Z, [X3, X1,LSL #3]    [11]

0x424934 LD1D	{Z23.D}, P7/Z, [X22, X1,LSL #3]    [7]

0x424938 LD1D	{Z22.D}, P7/Z, [X9, X1,LSL #3]    [4]

0x42493c LD1D	{Z20.D}, P7/Z, [X11, X1,LSL #3]    [5]

0x424940 LD1D	{Z19.D}, P7/Z, [X4, X1,LSL #3]    [12]

0x424944 LD1D	{Z17.D}, P7/Z, [X8, X1,LSL #3]    [3]

0x424948 LD1D	{Z16.D}, P7/Z, [X6, X1,LSL #3]    [2]

0x42494c LD1D	{Z6.D}, P7/Z, [X14, X1,LSL #3]    [9]

0x424950 LD1D	{Z25.D}, P7/Z, [X13, X1,LSL #3]    [8]

0x424954 MOVPRFX	Z5, Z4

0x424958 FMUL	Z5.D, P7/M, Z5.D, Z6.D

0x42495c LD1D	{Z27.D}, P7/Z, [X5, X1,LSL #3]    [1]

0x424960 MOVPRFX	Z29, Z5

0x424964 FMUL	Z29.D, P7/M, Z29.D, Z25.D

0x424968 MOVPRFX	Z28, Z0

0x42496c FMUL	Z28.D, P7/M, Z28.D, Z0.D

0x424970 MOVPRFX	Z21, Z23

0x424974 FMUL	Z21.D, P7/M, Z21.D, Z23.D

0x424978 FMLA	Z28.D, P7/M, Z24.D, Z24.D

0x42497c FMLA	Z21.D, P7/M, Z22.D, Z22.D

0x424980 FMUL	Z28.D, P7/M, Z28.D, Z30.D

0x424984 MOVPRFX	Z18, Z20

0x424988 FMUL	Z18.D, P7/M, Z18.D, Z20.D

0x42498c FADD	Z28.D, P7/M, Z28.D, Z31.D

0x424990 FMLA	Z18.D, P7/M, Z19.D, Z19.D

0x424994 FMLA	Z28.D, P7/M, Z21.D, Z30.D

0x424998 MOVPRFX	Z7, Z17

0x42499c FMUL	Z7.D, P7/M, Z7.D, Z17.D

0x4249a0 FMLA	Z28.D, P7/M, Z18.D, Z30.D

0x4249a4 FMLA	Z7.D, P7/M, Z16.D, Z16.D

0x4249a8 FADDA	D11, P7, D11, Z4.D

0x4249ac FMLA	Z28.D, P7/M, Z7.D, Z30.D

0x4249b0 FADDA	D12, P7, D12, Z5.D

0x4249b4 FMUL	Z4.D, P7/M, Z4.D, Z27.D

0x4249b8 FMUL	Z5.D, P7/M, Z5.D, #0.0000000

0x4249bc ADD	X1, X1, X15

0x4249c0 FMUL	Z5.D, P7/M, Z5.D, Z28.D

0x4249c4 FADDA	D14, P7, D14, Z29.D

0x4249c8 FADDA	D13, P7, D13, Z4.D

0x4249cc FADDA	D15, P7, D15, Z5.D

0x4249d0 WHILELO	P7.D, X1, X2

0x4249d4 B.NE	424928

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 62 - 71

--------------------------------------------------------------------------------

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Coverage (%)	Name	Source Location	Module
►98.42+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.26+	GOMP_parallel		libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:77	exec
○	field_summary	field_summary.f90:81	exec
○	hydro	hydro.f90:74	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P6, P7,
Function	__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	14.50
Front-end cycles	5.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	14.50
P7 cycles	14.50
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	44.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.28
Nb FLOP add-sub	24.00
Nb FLOP mul	40.00
Nb FLOP fma	28.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.48
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	0.00
Vectorization ratio all	85.37
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P6, P7,
Function	__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	14.50
Front-end cycles	5.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	14.50
P7 cycles	14.50
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	44.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.28
Nb FLOP add-sub	24.00
Nb FLOP mul	40.00
Nb FLOP fma	28.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.48
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	0.00
Vectorization ratio all	85.37
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:62-71.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 12 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

52: addition or subtraction (28 inside FMA instructions)
68: multiply (28 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	44
loop length	176
used w registers	0
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	5
used q registers	0
used v registers	0
used z registers	20
nb stack references	0
ADD-SUB / MUL ratio	0.60

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	14.50	14.50	0.00	0.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	14.50	14.50	11.50	11.50	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.50
Dispatch	14.50
Data deps.	8.00
Overall L1	14.50

Vectorization ratios

INT

all	66%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

27% of peak load performance is reached (26.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424928

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z4.D}, P7/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P7/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z29, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z21, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z21.D, P7/M, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z28.D, P7/M, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z18, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z18.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z28.D, P7/M, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z18.D, P7/M, Z19.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z28.D, P7/M, Z21.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z7, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z7.D, P7/M, Z7.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z28.D, P7/M, Z18.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z7.D, P7/M, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADDA D11, P7, D11, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
FMLA Z28.D, P7/M, Z7.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADDA D12, P7, D12, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
FMUL Z4.D, P7/M, Z4.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X1, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z5.D, P7/M, Z5.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADDA D14, P7, D14, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
FADDA D13, P7, D13, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
FADDA D15, P7, D15, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
WHILELO P7.D, X1, X2	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
B.NE 424928 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 12 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

52: addition or subtraction (28 inside FMA instructions)
68: multiply (28 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	44
loop length	176
used w registers	0
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	5
used q registers	0
used v registers	0
used z registers	20
nb stack references	0
ADD-SUB / MUL ratio	0.60

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	14.50	14.50	0.00	0.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	14.50	14.50	11.50	11.50	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.50
Dispatch	14.50
Data deps.	8.00
Overall L1	14.50

Vectorization ratios

INT

all	66%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

27% of peak load performance is reached (26.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424928

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z4.D}, P7/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P7/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z29, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z21, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z21.D, P7/M, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z28.D, P7/M, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z21.D, P7/M, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
MOVPRFX Z18, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z18.D, P7/M, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z28.D, P7/M, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z18.D, P7/M, Z19.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z28.D, P7/M, Z21.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z7, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z7.D, P7/M, Z7.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z28.D, P7/M, Z18.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z7.D, P7/M, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADDA D11, P7, D11, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
FMLA Z28.D, P7/M, Z7.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADDA D12, P7, D12, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
FMUL Z4.D, P7/M, Z4.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X1, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z5.D, P7/M, Z5.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADDA D14, P7, D14, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
FADDA D13, P7, D13, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
FADDA D15, P7, D15, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
WHILELO P7.D, X1, X2	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
B.NE 424928 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code