OV - exec - Loop 59

	Loop Id: 59	Module: exec	Source: PdV_kernel.f90:114-135 [...]	Coverage: 8.00%

0x41cf6c LD1D	{Z21.D}, P7/Z, [X8, X0,LSL #3]    [14]

0x41cf70 LD1D	{Z27.D}, P7/Z, [X16, X0,LSL #3]    [23]

0x41cf74 LD1D	{Z2.D}, P7/Z, [X7, X0,LSL #3]    [12]

0x41cf78 LD1D	{Z7.D}, P7/Z, [X19, X0,LSL #3]    [26]

0x41cf7c LD1D	{Z26.D}, P7/Z, [X18, X0,LSL #3]    [25]

0x41cf80 LD1D	{Z25.D}, P7/Z, [X17, X0,LSL #3]    [24]

0x41cf84 LD1D	{Z0.D}, P7/Z, [X14, X0,LSL #3]    [13]

0x41cf88 LD1D	{Z22.D}, P7/Z, [X30, X0,LSL #3]    [21]

0x41cf8c LD1D	{Z1.D}, P7/Z, [X23, X0,LSL #3]    [18]

0x41cf90 LD1D	{Z3.D}, P7/Z, [X20, X0,LSL #3]    [17]

0x41cf94 FADD	Z22.D, P7/M, Z22.D, Z21.D

0x41cf98 FADD	Z3.D, P7/M, Z3.D, Z7.D

0x41cf9c FADD	Z22.D, P7/M, Z22.D, Z27.D

0x41cfa0 FADD	Z3.D, P7/M, Z3.D, Z26.D

0x41cfa4 FADD	Z22.D, P7/M, Z22.D, Z2.D

0x41cfa8 FADD	Z3.D, P7/M, Z3.D, Z25.D

0x41cfac FMUL	Z1.D, P7/M, Z1.D, Z22.D

0x41cfb0 FMUL	Z1.D, P7/M, Z1.D, Z31.D

0x41cfb4 LD1D	{Z21.D}, P7/Z, [X5, X0,LSL #3]    [10]

0x41cfb8 LD1RD	{Z24.D}, P6/Z, [X27]    [20]

0x41cfbc LD1D	{Z22.D}, P7/Z, [X3, X0,LSL #3]    [9]

0x41cfc0 LD1D	{Z29.D}, P7/Z, [X28, X0,LSL #3]    [4]

0x41cfc4 LD1D	{Z6.D}, P7/Z, [X13, X0,LSL #3]    [5]

0x41cfc8 LD1D	{Z17.D}, P7/Z, [X6, X0,LSL #3]    [11]

0x41cfcc LD1D	{Z16.D}, P7/Z, [X10, X0,LSL #3]    [3]

0x41cfd0 LD1D	{Z18.D}, P7/Z, [X9, X0,LSL #3]    [22]

0x41cfd4 LD1D	{Z5.D}, P7/Z, [X21, X0,LSL #3]    [27]

0x41cfd8 LD1D	{Z23.D}, P7/Z, [X15, X0,LSL #3]    [6]

0x41cfdc LD1D	{Z20.D}, P7/Z, [X12, X0,LSL #3]    [16]

0x41cfe0 LD1D	{Z19.D}, P7/Z, [X11, X0,LSL #3]    [15]

0x41cfe4 LD1D	{Z28.D}, P7/Z, [X22, X0,LSL #3]    [28]

0x41cfe8 LD1D	{Z26.D}, P7/Z, [X24, X0,LSL #3]    [1]

0x41cfec LD1D	{Z25.D}, P7/Z, [X25, X0,LSL #3]    [19]

0x41cff0 MOVPRFX	Z4, Z24

0x41cff4 FMUL	Z4.D, P7/M, Z4.D, Z1.D

0x41cff8 FMUL	Z29.D, P7/M, Z29.D, Z3.D

0x41cffc LD1D	{Z1.D}, P7/Z, [X26, X0,LSL #3]    [2]

0x41d000 FADD	Z23.D, P7/M, Z23.D, Z0.D

0x41d004 FMUL	Z29.D, P7/M, Z29.D, Z31.D

0x41d008 FADD	Z6.D, P7/M, Z6.D, Z17.D

0x41d00c FMLS	Z4.D, P7/M, Z24.D, Z29.D

0x41d010 FADD	Z6.D, P7/M, Z6.D, Z16.D

0x41d014 FADD	Z23.D, P7/M, Z23.D, Z20.D

0x41d018 FADD	Z6.D, P7/M, Z6.D, Z18.D

0x41d01c FADD	Z23.D, P7/M, Z23.D, Z19.D

0x41d020 FMUL	Z5.D, P7/M, Z5.D, Z6.D

0x41d024 FMUL	Z28.D, P7/M, Z28.D, Z23.D

0x41d028 FMUL	Z5.D, P7/M, Z5.D, Z31.D

0x41d02c MOVPRFX	Z3, Z30

0x41d030 FDIV	Z3.D, P7/M, Z3.D, Z21.D

0x41d034 MOVPRFX	Z7, Z24

0x41d038 FMUL	Z7.D, P7/M, Z7.D, Z5.D

0x41d03c FMUL	Z28.D, P7/M, Z28.D, Z31.D

0x41d040 FADD	Z7.D, P7/M, Z7.D, Z4.D

0x41d044 FDIV	Z1.D, P7/M, Z1.D, Z22.D

0x41d048 FMLS	Z7.D, P7/M, Z28.D, Z24.D

0x41d04c FDIV	Z26.D, P7/M, Z26.D, Z22.D

0x41d050 MOVPRFX	Z2, Z7

0x41d054 FADD	Z2.D, P7/M, Z2.D, Z21.D

0x41d058 FADD	Z1.D, P7/M, Z1.D, Z26.D

0x41d05c MOVPRFX	Z27, Z21

0x41d060 FDIV	Z27.D, P7/M, Z27.D, Z2.D

0x41d064 FMUL	Z7.D, P7/M, Z7.D, Z1.D

0x41d068 FMLS	Z25.D, P7/M, Z7.D, Z3.D

0x41d06c ST1D	{Z25.D}, P7, [X1, X0,LSL #3]    [7]

0x41d070 LD1D	{Z0.D}, P7/Z, [X3, X0,LSL #3]    [9]

0x41d074 FMUL	Z27.D, P7/M, Z27.D, Z0.D

0x41d078 ST1D	{Z27.D}, P7, [X2, X0,LSL #3]    [8]

0x41d07c INCD	X0, ALL

0x41d080 WHILELO	P7.D, X0, X4

0x41d084 B.NE	41cf6c

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 114 - 135

--------------------------------------------------------------------------------

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
►98.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	GOMP_parallel		libgomp.so.1.0.0
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:58	exec
○	hydro	hydro.f90:60	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43 - 2.89
Bottlenecks	P6, P8,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	8.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	19.50
P7 cycles	19.50
P8 cycles	15.00
P9 cycles	15.00
P10 cycles	14.50
P11 cycles	14.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	71.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.29 - 2.63
Nb FLOP add-sub	60.00
Nb FLOP mul	48.00
Nb FLOP fma	12.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.90 - 32.03
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	91.18
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.90
Vector-efficiency ratio load	97.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43 - 2.89
Bottlenecks	P6, P8,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	8.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	19.50
P7 cycles	19.50
P8 cycles	15.00
P9 cycles	15.00
P10 cycles	14.50
P11 cycles	14.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	71.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.29 - 2.63
Nb FLOP add-sub	60.00
Nb FLOP mul	48.00
Nb FLOP fma	12.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.90 - 32.03
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	91.18
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.90
Vector-efficiency ratio load	97.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:114-123,129-135.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

91% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 17.50 cycles (3.22x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
60: multiply (12 inside FMA instructions)
16: divide

The binary loop is loading 832 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	71
nb uops	71
loop length	284
used w registers	0
used x registers	30
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.88 cycles
front end	8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	19.50	19.50	1.00	1.00	14.50	14.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	19.50	19.50	15.00	15.00	14.50	14.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.88
Dispatch	19.50
DIV/SQRT	27.97-56.34
Data deps.	2.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	82%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	91%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	97%
load	97%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

15% of peak load performance is reached (14.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41cf6c

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z21.D}, P7/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P7/M, Z1.D, Z22.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, P7/M, Z1.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1RD {Z24.D}, P6/Z, [X27]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1D {Z22.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z29.D}, P7/Z, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P7/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z24	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z4.D, P7/M, Z4.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z23.D, P7/M, Z23.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z17.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLS Z4.D, P7/M, Z24.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z23.D, P7/M, Z23.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z23.D, P7/M, Z23.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z3, Z30	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z3.D, P7/M, Z3.D, Z21.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z7, Z24	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z7.D, P7/M, Z7.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z7.D, P7/M, Z7.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z1.D, P7/M, Z1.D, Z22.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z7.D, P7/M, Z28.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z26.D, P7/M, Z26.D, Z22.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z2, Z7	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z2.D, P7/M, Z2.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z1.D, P7/M, Z1.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z27, Z21	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z27.D, P7/M, Z27.D, Z2.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z7.D, P7/M, Z7.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLS Z25.D, P7/M, Z7.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z25.D}, P7, [X1, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, P7/M, Z27.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z27.D}, P7, [X2, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
INCD X0, ALL	1	0	0	1	0	0	0	0	0	0	2	1	N/A
WHILELO P7.D, X0, X4	1	0	0	1	0	0	0	0	0	0	3	2	N/A
B.NE 41cf6c <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x84c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

91% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 17.50 cycles (3.22x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
60: multiply (12 inside FMA instructions)
16: divide

The binary loop is loading 832 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	71
nb uops	71
loop length	284
used w registers	0
used x registers	30
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.88 cycles
front end	8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	19.50	19.50	1.00	1.00	14.50	14.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	19.50	19.50	15.00	15.00	14.50	14.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.88
Dispatch	19.50
DIV/SQRT	27.97-56.34
Data deps.	2.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	82%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	91%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	97%
load	97%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

15% of peak load performance is reached (14.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41cf6c

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z21.D}, P7/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P7/M, Z1.D, Z22.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, P7/M, Z1.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1RD {Z24.D}, P6/Z, [X27]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1D {Z22.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z29.D}, P7/Z, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P7/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z24	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z4.D, P7/M, Z4.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z23.D, P7/M, Z23.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z17.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLS Z4.D, P7/M, Z24.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z23.D, P7/M, Z23.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z23.D, P7/M, Z23.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z3, Z30	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z3.D, P7/M, Z3.D, Z21.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z7, Z24	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z7.D, P7/M, Z7.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z7.D, P7/M, Z7.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z1.D, P7/M, Z1.D, Z22.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z7.D, P7/M, Z28.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z26.D, P7/M, Z26.D, Z22.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z2, Z7	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z2.D, P7/M, Z2.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z1.D, P7/M, Z1.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z27, Z21	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z27.D, P7/M, Z27.D, Z2.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z7.D, P7/M, Z7.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLS Z25.D, P7/M, Z7.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z25.D}, P7, [X1, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z27.D, P7/M, Z27.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z27.D}, P7, [X2, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
INCD X0, ALL	1	0	0	1	0	0	0	0	0	0	2	1	N/A
WHILELO P7.D, X0, X4	1	0	0	1	0	0	0	0	0	0	3	2	N/A
B.NE 41cf6c <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x84c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code