OV - exec - Loop 62

	Loop Id: 62	Module: exec	Source: PdV_kernel.f90:78-99 [...]	Coverage: 6.39%

0x41ca24 LD1D	{Z24.D}, P2/Z, [X14, X0,LSL #3]    [7]

0x41ca28 LD1D	{Z4.D}, P2/Z, [X4, X0,LSL #3]    [20]

0x41ca2c LD1D	{Z6.D}, P2/Z, [X25, X0,LSL #3]    [9]

0x41ca30 LD1D	{Z16.D}, P2/Z, [X24, X0,LSL #3]    [8]

0x41ca34 LD1D	{Z5.D}, P2/Z, [X27, X0,LSL #3]    [2]

0x41ca38 MOVPRFX	Z17, Z24

0x41ca3c FADD	Z17.D, P2/M, Z17.D, Z4.D

0x41ca40 MOVPRFX	Z18, Z6

0x41ca44 FADD	Z18.D, P2/M, Z18.D, Z16.D

0x41ca48 FADD	Z24.D, P2/M, Z24.D, Z17.D

0x41ca4c FADD	Z6.D, P2/M, Z6.D, Z18.D

0x41ca50 FADD	Z4.D, P2/M, Z4.D, Z24.D

0x41ca54 FADD	Z16.D, P2/M, Z16.D, Z6.D

0x41ca58 FMUL	Z5.D, P2/M, Z5.D, Z16.D

0x41ca5c FMUL	Z5.D, P2/M, Z5.D, Z31.D

0x41ca60 LD1D	{Z24.D}, P2/Z, [X19, X0,LSL #3]    [18]

0x41ca64 LD1RD	{Z28.D}, P0/Z, [X26]    [11]

0x41ca68 LD1D	{Z20.D}, P2/Z, [X3, X0,LSL #3]    [16]

0x41ca6c LD1D	{Z7.D}, P2/Z, [X20, X0,LSL #3]    [17]

0x41ca70 LD1D	{Z19.D}, P2/Z, [X6, X0,LSL #3]    [3]

0x41ca74 LD1D	{Z1.D}, P2/Z, [X23, X0,LSL #3]    [6]

0x41ca78 LD1D	{Z26.D}, P2/Z, [X8, X0,LSL #3]    [5]

0x41ca7c LD1D	{Z23.D}, P2/Z, [X5, X0,LSL #3]    [1]

0x41ca80 LD1D	{Z2.D}, P2/Z, [X21, X0,LSL #3]    [19]

0x41ca84 LD1D	{Z27.D}, P2/Z, [X16, X0,LSL #3]    [10]

0x41ca88 LD1D	{Z6.D}, P2/Z, [X7, X0,LSL #3]    [4]

0x41ca8c LD1D	{Z25.D}, P2/Z, [X18, X0,LSL #3]    [15]

0x41ca90 LD1D	{Z16.D}, P2/Z, [X17, X0,LSL #3]    [13]

0x41ca94 MOVPRFX	Z22, Z28

0x41ca98 FMUL	Z22.D, P2/M, Z22.D, Z5.D

0x41ca9c FMUL	Z23.D, P2/M, Z23.D, Z4.D

0x41caa0 MOVPRFX	Z21, Z20

0x41caa4 FADD	Z21.D, P2/M, Z21.D, Z7.D

0x41caa8 MOVPRFX	Z3, Z19

0x41caac FADD	Z3.D, P2/M, Z3.D, Z1.D

0x41cab0 FMUL	Z23.D, P2/M, Z23.D, Z31.D

0x41cab4 FMUL	Z22.D, P2/M, Z22.D, #0.0000000

0x41cab8 FMUL	Z23.D, P2/M, Z23.D, Z28.D

0x41cabc FADD	Z20.D, P2/M, Z20.D, Z21.D

0x41cac0 FMLS	Z22.D, P2/M, Z23.D, Z30.D

0x41cac4 FADD	Z7.D, P2/M, Z7.D, Z20.D

0x41cac8 FADD	Z19.D, P2/M, Z19.D, Z3.D

0x41cacc FMUL	Z2.D, P2/M, Z2.D, Z7.D

0x41cad0 FADD	Z1.D, P2/M, Z1.D, Z19.D

0x41cad4 FMUL	Z2.D, P2/M, Z2.D, Z31.D

0x41cad8 FMUL	Z27.D, P2/M, Z27.D, Z1.D

0x41cadc MOVPRFX	Z4, Z29

0x41cae0 FDIV	Z4.D, P2/M, Z4.D, Z24.D

0x41cae4 FMUL	Z27.D, P2/M, Z27.D, Z31.D

0x41cae8 FDIV	Z6.D, P2/M, Z6.D, Z26.D

0x41caec MOVPRFX	Z0, Z28

0x41caf0 FMUL	Z0.D, P2/M, Z0.D, Z27.D

0x41caf4 FDIV	Z25.D, P2/M, Z25.D, Z26.D

0x41caf8 FMUL	Z28.D, P2/M, Z28.D, Z2.D

0x41cafc FADD	Z6.D, P2/M, Z6.D, Z25.D

0x41cb00 FMUL	Z28.D, P2/M, Z28.D, #0.0000000

0x41cb04 FADD	Z28.D, P2/M, Z28.D, Z22.D

0x41cb08 FMLS	Z28.D, P2/M, Z0.D, Z30.D

0x41cb0c MOVPRFX	Z17, Z28

0x41cb10 FADD	Z17.D, P2/M, Z17.D, Z24.D

0x41cb14 FMUL	Z28.D, P2/M, Z28.D, Z6.D

0x41cb18 MOVPRFX	Z18, Z24

0x41cb1c FDIV	Z18.D, P2/M, Z18.D, Z17.D

0x41cb20 FMLS	Z16.D, P2/M, Z28.D, Z4.D

0x41cb24 ST1D	{Z16.D}, P2, [X2, X0,LSL #3]    [14]

0x41cb28 LD1D	{Z5.D}, P2/Z, [X8, X0,LSL #3]    [5]

0x41cb2c FMUL	Z18.D, P2/M, Z18.D, Z5.D

0x41cb30 ST1D	{Z18.D}, P2, [X1, X0,LSL #3]    [12]

0x41cb34 ADD	X0, X0, X22

0x41cb38 WHILELO	P2.D, X0, X13

0x41cb3c B.NE	41ca24

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 78 - 99

--------------------------------------------------------------------------------

78:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

79:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

80:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

81:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

82:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

83:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

84:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

85:           total_flux=right_flux-left_flux+top_flux-bottom_flux

86:

87:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

93:           recip_volume=1.0/volume(j,k)

94:

95:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

96:

97:           energy1(j,k)=energy0(j,k)-energy_change

98:

99:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
►98.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	GOMP_parallel		libgomp.so.1.0.0
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:58	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19 - 2.40
Bottlenecks	P6, P8,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:78-87,PdV_kernel.f90:93-99
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	8.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	23.50
P7 cycles	23.50
P8 cycles	17.00
P9 cycles	17.00
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	71.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.86 - 2.91
Nb FLOP add-sub	60.00
Nb FLOP mul	64.00
Nb FLOP fma	12.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.36 - 22.88
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	19.00
Stride indirect	0.00
Vectorization ratio all	85.29
Vectorization ratio load	94.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.90
Vector-efficiency ratio load	96.05
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19 - 2.40
Bottlenecks	P6, P8,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:78-87,PdV_kernel.f90:93-99
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	8.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	23.50
P7 cycles	23.50
P8 cycles	17.00
P9 cycles	17.00
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	71.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.86 - 2.91
Nb FLOP add-sub	60.00
Nb FLOP mul	64.00
Nb FLOP fma	12.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.36 - 22.88
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	19.00
Stride indirect	0.00
Vectorization ratio all	85.29
Vectorization ratio load	94.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.90
Vector-efficiency ratio load	96.05
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:78-99
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:78-87,93-99.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 21.50 cycles (2.62x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 19 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
76: multiply (12 inside FMA instructions)
16: divide

The binary loop is loading 576 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	71
nb uops	71
loop length	284
used w registers	0
used x registers	23
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	0.94

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.88 cycles
front end	8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	23.50	23.50	1.00	1.00	10.50	10.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	23.50	23.50	17.00	17.00	10.50	10.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.88
Dispatch	23.50
DIV/SQRT	27.97-56.34
Data deps.	1.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	66%
load	94%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	85%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	97%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

10% of peak load performance is reached (10.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41ca24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z24.D}, P2/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z17, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z17.D, P2/M, Z17.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z18.D, P2/M, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z24.D, P2/M, Z24.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, P2/M, Z6.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, P2/M, Z4.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z16.D, P2/M, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P2/M, Z5.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, P2/M, Z5.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1RD {Z28.D}, P0/Z, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1D {Z20.D}, P2/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P2/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P2/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P2/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P2/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P2/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z22, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z22.D, P2/M, Z22.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, P2/M, Z23.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z21.D, P2/M, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z3, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z3.D, P2/M, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z23.D, P2/M, Z23.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, P2/M, Z22.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, P2/M, Z23.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z20.D, P2/M, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLS Z22.D, P2/M, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z7.D, P2/M, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, P2/M, Z19.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, P2/M, Z2.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z1.D, P2/M, Z1.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, P2/M, Z2.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z27.D, P2/M, Z27.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z4, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z4.D, P2/M, Z4.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z27.D, P2/M, Z27.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z6.D, P2/M, Z6.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z0, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z0.D, P2/M, Z0.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z25.D, P2/M, Z25.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z28.D, P2/M, Z28.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z6.D, P2/M, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z28.D, P2/M, Z28.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z28.D, P2/M, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLS Z28.D, P2/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z17, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z17.D, P2/M, Z17.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z28.D, P2/M, Z28.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z18, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z18.D, P2/M, Z18.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z16.D, P2/M, Z28.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z16.D}, P2, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, P2/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z18.D}, P2, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X0, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P2.D, X0, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 41ca24 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:78-99
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 21.50 cycles (2.62x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 19 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
76: multiply (12 inside FMA instructions)
16: divide

The binary loop is loading 576 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	71
nb uops	71
loop length	284
used w registers	0
used x registers	23
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	0.94

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.88 cycles
front end	8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	23.50	23.50	1.00	1.00	10.50	10.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	23.50	23.50	17.00	17.00	10.50	10.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.88
Dispatch	23.50
DIV/SQRT	27.97-56.34
Data deps.	1.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	66%
load	94%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	85%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	97%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

10% of peak load performance is reached (10.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41ca24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z24.D}, P2/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z17, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z17.D, P2/M, Z17.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z18.D, P2/M, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z24.D, P2/M, Z24.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, P2/M, Z6.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, P2/M, Z4.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z16.D, P2/M, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P2/M, Z5.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, P2/M, Z5.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1RD {Z28.D}, P0/Z, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1D {Z20.D}, P2/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P2/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P2/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P2/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P2/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P2/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P2/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z22, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z22.D, P2/M, Z22.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, P2/M, Z23.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z21, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z21.D, P2/M, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z3, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z3.D, P2/M, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z23.D, P2/M, Z23.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, P2/M, Z22.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, P2/M, Z23.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z20.D, P2/M, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLS Z22.D, P2/M, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z7.D, P2/M, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, P2/M, Z19.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, P2/M, Z2.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z1.D, P2/M, Z1.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, P2/M, Z2.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z27.D, P2/M, Z27.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z4, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z4.D, P2/M, Z4.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z27.D, P2/M, Z27.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z6.D, P2/M, Z6.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z0, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z0.D, P2/M, Z0.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z25.D, P2/M, Z25.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z28.D, P2/M, Z28.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z6.D, P2/M, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z28.D, P2/M, Z28.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z28.D, P2/M, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLS Z28.D, P2/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z17, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z17.D, P2/M, Z17.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z28.D, P2/M, Z28.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z18, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z18.D, P2/M, Z18.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z16.D, P2/M, Z28.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z16.D}, P2, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z18.D, P2/M, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z18.D}, P2, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X0, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P2.D, X0, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 41ca24 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code