OV - exec - Loop 73

	Loop Id: 73	Module: exec	Source: advec_cell_kernel.f90:110-155 [...]	Coverage: 2.99%

0x41f0c0 LDR	D3, [X30, X0,LSL #3]    [6]

0x41f0c4 SUB	W22, W0, #2

0x41f0c8 ORR	X21, XZR, X0

0x41f0cc ORR	X12, XZR, X18

0x41f0d0 SBFM	X5, X22, #0, #31

0x41f0d4 ORR	X11, XZR, X18

0x41f0d8 FCMPE	D3, #0

0x41f0dc B.GT	41f0fc

0x41f0e0 ADD	W21, W0, #1

0x41f0e4 ORR	X12, XZR, X0

0x41f0e8 CMP	W21, W13

0x41f0ec CSEL	W27, W21, W13, #13

0x41f0f0 SBFM	X11, X27, #0, #31

0x41f0f4 ORR	X5, XZR, X11

0x41f0f8 ORR	X21, XZR, X18

0x41f0fc ADD	X23, X17, X12

0x41f100 FABS	D30, D3

0x41f104 ADD	X11, X24, X11

0x41f108 LDR	D22, [X26, X0,LSL #3]    [2]

0x41f10c ADD	X27, X8, X12

0x41f110 ADD	X22, X8, X21

0x41f114 MOVI	D31, #0

0x41f118 LDR	D29, [X14, X23,LSL #3]    [4]

0x41f11c LDR	D2, [X25, X11,LSL #3]    [1]

0x41f120 ADD	X11, X8, X5

0x41f124 LDR	D20, [X7, X27,LSL #3]    [5]

0x41f128 FDIV	D0, D30, D29

0x41f12c LDR	D26, [X7, X22,LSL #3]    [5]

0x41f130 LDR	D16, [X7, X11,LSL #3]    [5]

0x41f134 FDIV	D27, D22, D2

0x41f138 FSUB	D28, D26, S20

0x41f13c FSUB	D19, D20, S16

0x41f140 FCMPE	D28, D31

0x41f144 FABS	D7, D28

0x41f148 FMUL	D21, D19, D28

0x41f14c FABS	D18, D19

0x41f150 FADD	D17, D0, D6

0x41f154 FSUB	D1, D25, S0

0x41f158 FCSEL	D4, D24, D6, #9

0x41f15c FCMPE	D21, D31

0x41f160 FMUL	D22, D27, D17

0x41f164 B.GT	41f574

0x41f168 FADD	D20, D31, D20

0x41f16c ADD	X12, X9, X12

0x41f170 ADD	X21, X9, X21

0x41f174 ADD	X5, X9, X5

0x41f178 FMUL	D3, D20, D3

0x41f17c STR	D3, [X15, X0,LSL #3]    [7]

0x41f180 FABS	D27, D3

0x41f184 LDR	D7, [X10, X12,LSL #3]    [3]

0x41f188 LDR	D28, [X10, X21,LSL #3]    [3]

0x41f18c LDR	D19, [X10, X5,LSL #3]    [3]

0x41f190 FSUB	D21, D28, S7

0x41f194 FSUB	D17, D7, S19

0x41f198 FCMPE	D21, #0

0x41f19c FABS	D4, D21

0x41f1a0 FMUL	D30, D17, D21

0x41f1a4 FABS	D18, D17

0x41f1a8 FCSEL	D2, D24, D6, #9

0x41f1ac FCMPE	D30, #0

0x41f1b0 B.GT	41f598

0x41f1b4 FADD	D7, D7, D23

0x41f1b8 ADD	X18, X18, #1

0x41f1bc FMUL	D3, D7, D3

0x41f1c0 STR	D3, [X16, X0,LSL #3]    [8]

0x41f1c4 ADD	X0, X0, #1

0x41f1c8 CMP	W13, W0

0x41f1cc B.GE	41f0c0

0x41f574 FMUL	D31, D1, D7

0x41f578 FSUB	D30, D6, S0

0x41f57c FMINNM	D29, D7, D18

0x41f580 FMADD	D2, D22, D18, D31

0x41f584 FMUL	D0, D30, D4

0x41f588 FMUL	D26, D2, D5

0x41f58c FMINNM	D16, D26, D29

0x41f590 FMUL	D31, D16, D0

0x41f594 B	41f168

0x41f598 LDR	D29, [X7, X27,LSL #3]    [5]

0x41f59c FMUL	D1, D1, D4

0x41f5a0 FMINNM	D0, D4, D18

0x41f5a4 ADD	X18, X18, #1

0x41f5a8 LDR	D26, [X14, X23,LSL #3]    [4]

0x41f5ac FMADD	D22, D22, D18, D1

0x41f5b0 FMUL	D16, D29, D26

0x41f5b4 FDIV	D31, D27, D16

0x41f5b8 FMUL	D20, D22, D5

0x41f5bc FMINNM	D27, D20, D0

0x41f5c0 FSUB	D28, D6, S31

0x41f5c4 FMUL	D19, D28, D2

0x41f5c8 FMADD	D7, D27, D19, D7

0x41f5cc B	41f1bc

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 110 - 155

--------------------------------------------------------------------------------

110:         DO j=x_min,x_max+2

111:

112:           IF(vol_flux_x(j,k).GT.0.0)THEN

113:             upwind   =j-2

114:             donor    =j-1

115:             downwind =j

116:             dif      =donor

117:           ELSE

118:             upwind   =MIN(j+1,x_max+2)

[...]

124:           sigmat=ABS(vol_flux_x(j,k))/pre_vol(donor,k)

125:           sigma3=(1.0_8+sigmat)*(vertexdx(j)/vertexdx(dif))

126:           sigma4=2.0_8-sigmat

127:

128:           sigma=sigmat

129:           sigmav=sigmat

130:

131:           diffuw=density1(donor,k)-density1(upwind,k)

132:           diffdw=density1(downwind,k)-density1(donor,k)

133:           wind=1.0_8

134:           IF(diffdw.LE.0.0) wind=-1.0_8

135:           IF(diffuw*diffdw.GT.0.0)THEN

136:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

137:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

138:           ELSE

139:             limiter=0.0

140:           ENDIF

141:           mass_flux_x(j,k)=vol_flux_x(j,k)*(density1(donor,k)+limiter)

142:

143:           sigmam=ABS(mass_flux_x(j,k))/(density1(donor,k)*pre_vol(donor,k))

144:           diffuw=energy1(donor,k)-energy1(upwind,k)

145:           diffdw=energy1(downwind,k)-energy1(donor,k)

146:           wind=1.0_8

147:           IF(diffdw.LE.0.0) wind=-1.0_8

148:           IF(diffuw*diffdw.GT.0.0)THEN

149:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

150:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

151:           ELSE

152:             limiter=0.0

153:           ENDIF

154:

155:           ener_flux(j,k)=mass_flux_x(j,k)*(energy1(donor,k)+limiter)

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.62
CQA speedup if FP arith vectorized	1.85
CQA speedup if fully vectorized	4.00 - 2.34
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6, P7, P8, P9,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:110-118,advec_cell_kernel.f90:124-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	6.63
CQA cycles if fully vectorized	3.06 - 5.24
Front-end cycles	11.38
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	12.25
P7 cycles	12.25
P8 cycles	12.25
P9 cycles	12.25
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	4.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	91.00
Nb uops	91.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.61
Nb FLOP add-sub	10.00
Nb FLOP mul	13.00
Nb FLOP fma	3.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.61
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	23.68

Metric	Value
CQA speedup if no scalar integer	2.62
CQA speedup if FP arith vectorized	1.85
CQA speedup if fully vectorized	4.00 - 2.34
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6, P7, P8, P9,
Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:110-118,advec_cell_kernel.f90:124-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	6.63
CQA cycles if fully vectorized	3.06 - 5.24
Front-end cycles	11.38
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	12.25
P7 cycles	12.25
P8 cycles	12.25
P9 cycles	12.25
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	4.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	91.00
Nb uops	91.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.61
Nb FLOP add-sub	10.00
Nb FLOP mul	13.00
Nb FLOP fma	3.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.61
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	23.68

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:110-155
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110-118,124-155.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 4.67 cycles (2.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.25 to 5.24 cycles (2.34x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.25 to 11.50 cycles (1.07x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

13: addition or subtraction (3 inside FMA instructions)
16: multiply (3 inside FMA instructions)
3: divide

The binary loop does not load or store any data.

General properties

nb instructions	91
nb uops	91
loop length	364
used w registers	5
used x registers	22
used b registers	0
used h registers	0
used s registers	6
used d registers	24
used q registers	0
used v registers	0
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.38 cycles
front end	11.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.00	6.00	6.00	6.00	12.25	12.25	12.25	12.25	4.67	4.67	4.67	0.00	0.00
cycles	3.00	3.00	6.00	6.00	6.00	6.00	12.25	12.25	12.25	12.25	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	11.38
Dispatch	12.25
DIV/SQRT	5.25-10.49
Overall L1	12.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	24%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41f0c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR D3, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SUB W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X12, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X5, X22, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FCMPE D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 41f0fc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x97c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W21, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X12, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W21, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W27, W21, W13, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X11, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X5, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FABS D30, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X11, X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X27, X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X22, X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	N/A
LDR D29, [X14, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X25, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X11, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X7, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D0, D30, D29	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D26, [X7, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D16, [X7, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D27, D22, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D28, D26, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D19, D20, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMPE D28, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D7, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D21, D19, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FABS D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D17, D0, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D1, D25, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D4, D24, D6, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMPE D21, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D22, D27, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
B.GT 41f574 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D20, D31, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X12, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X9, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D3, D20, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
FABS D27, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D7, [X10, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D28, [X10, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D21, D28, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D17, D7, S19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D4, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D30, D17, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FABS D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D2, D24, D6, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 41f598 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xe18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D7, D7, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMUL D3, D7, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W13, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 41f0c0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x940>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D31, D1, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FSUB D30, D6, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMINNM D29, D7, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D2, D22, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D0, D30, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D26, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D16, D26, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D31, D16, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
B 41f168 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x9e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D29, [X7, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D1, D1, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D0, D4, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D26, [X14, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D22, D22, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D16, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D31, D27, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D20, D22, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D27, D20, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D28, D6, S31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D19, D28, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D7, D27, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
B 41f1bc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:110-155
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 4.67 cycles (2.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.25 to 11.50 cycles (1.07x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

13: addition or subtraction (3 inside FMA instructions)
16: multiply (3 inside FMA instructions)
3: divide

The binary loop does not load or store any data.

General properties

nb instructions	91
nb uops	91
loop length	364
used w registers	5
used x registers	22
used b registers	0
used h registers	0
used s registers	6
used d registers	24
used q registers	0
used v registers	0
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.38 cycles
front end	11.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.00	6.00	6.00	6.00	12.25	12.25	12.25	12.25	4.67	4.67	4.67	0.00	0.00
cycles	3.00	3.00	6.00	6.00	6.00	6.00	12.25	12.25	12.25	12.25	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	11.38
Dispatch	12.25
DIV/SQRT	5.25-10.49
Overall L1	12.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	24%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41f0c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR D3, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SUB W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X12, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X5, X22, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FCMPE D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 41f0fc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x97c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W21, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X12, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W21, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W27, W21, W13, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X11, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X5, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FABS D30, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X11, X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X27, X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X22, X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	N/A
LDR D29, [X14, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X25, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X11, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X7, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D0, D30, D29	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D26, [X7, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D16, [X7, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D27, D22, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D28, D26, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D19, D20, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMPE D28, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D7, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D21, D19, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FABS D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FADD D17, D0, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D1, D25, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D4, D24, D6, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMPE D21, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FMUL D22, D27, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
B.GT 41f574 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D20, D31, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X12, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X9, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D3, D20, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
FABS D27, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D7, [X10, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D28, [X10, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D21, D28, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D17, D7, S19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D4, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D30, D17, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FABS D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D2, D24, D6, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FCMPE D30, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 41f598 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xe18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D7, D7, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMUL D3, D7, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W13, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 41f0c0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x940>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D31, D1, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FSUB D30, D6, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMINNM D29, D7, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D2, D22, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D0, D30, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D26, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D16, D26, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D31, D16, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
B 41f168 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x9e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D29, [X7, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D1, D1, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D0, D4, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D26, [X14, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D22, D22, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D16, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D31, D27, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D20, D22, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D27, D20, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D28, D6, S31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D19, D28, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D7, D27, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
B 41f1bc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code