OV - exec - Function _QMpdv_kernel_modulePpdv_kernel..omp

	Function: _QMpdv_kernel_modulePpdv_kernel..omp_par	Module: exec	Source: :0-0 [...]	Coverage (incl. loops): 14.53% \| (excl. loops): 0.01%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 69 - 135

--------------------------------------------------------------------------------

69:     IF(predict)THEN

70:

71:       !$OMP DO PRIVATE(right_flux,left_flux,top_flux,bottom_flux,total_flux,min_cell_volume, &

72:       !$OMP            energy_change,recip_volume,volume_change_s)

73:       DO k=y_min,y_max

74:       !$OMP SIMD

75:         DO j=x_min,x_max

76:

77:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

78:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

79:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

80:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

81:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

82:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

83:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

84:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

85:           total_flux=right_flux-left_flux+top_flux-bottom_flux

86:

87:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

95:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

96:

97:           energy1(j,k)=energy0(j,k)-energy_change

98:

99:           density1(j,k)=density0(j,k)*volume_change_s

[...]

107:       !$OMP DO PRIVATE(right_flux,left_flux,top_flux,bottom_flux,total_flux,min_cell_volume, &

108:       !$OMP            energy_change,recip_volume,volume_change_s)

109:       DO k=y_min,y_max

110:       !$OMP SIMD

111:         DO j=x_min,x_max

112:

113:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

0x416aa0 SUB	SP, SP, #256

0x416aa4 STP	X29, X30, [SP, #160]

0x416aa8 STP	X28, X27, [SP, #176]

0x416aac STP	X26, X25, [SP, #192]

0x416ab0 STP	X24, X23, [SP, #208]

0x416ab4 STP	X22, X21, [SP, #224]

0x416ab8 STP	X20, X19, [SP, #240]

0x416abc ADD	X29, SP, #160

0x416ac0 LDP	X14, X13, [X2, #56]

0x416ac4 LDP	X8, X9, [X2]

0x416ac8 ADRP	X0,

0x416acc ADD	X0, X0, #3368

0x416ad0 LDR	X10, [X2, #16]

0x416ad4 LDR	X26, [X8]

0x416ad8 STUR	X14, [X29, #464]

0x416adc STR	X13, [SP, #48]

0x416ae0 LDP	X14, X13, [X2, #72]

0x416ae4 LDP	X11, X12, [X2, #40]

0x416ae8 LDR	X8, [X9]

0x416aec LDR	X9, [X10]

0x416af0 LDP	X20, X21, [X2, #88]

0x416af4 STR	X13, [SP, #32]

0x416af8 LDP	X28, X13, [X2, #136]

0x416afc STR	X14, [SP, #16]

0x416b00 LDP	X27, X14, [X2, #104]

0x416b04 LDP	X23, X24, [X2, #120]

0x416b08 LDP	X22, X25, [X2, #184]

0x416b0c STUR	X13, [X29, #472]

0x416b10 LDP	X15, X13, [X2, #152]

0x416b14 STUR	X13, [X29, #440]

0x416b18 LDP	X13, X19, [X2, #168]

0x416b1c STP	X15, X14, [X29, #960]

0x416b20 STP	X8, X13, [SP, #72]

0x416b24 LDR	X8, [X11]

0x416b28 STP	X8, X9, [SP, #56]

0x416b2c LDR	W8, [X12]

0x416b30 STR	W8, [SP, #44]

0x416b34 BL	4101f0

0x416b38 LDUR	X8, [X29, #464]

0x416b3c ORR	W1, WZR, W0

0x416b40 STR	W0, [SP, #28]

0x416b44 LDR	W9, [X8]

0x416b48 LDR	X8, [SP, #48]

0x416b4c LDR	W8, [X8]

0x416b50 SUBS	W8, W8, W9

0x416b54 STR	W9, [SP, #48]

0x416b58 LDR	W9, [SP, #44]

0x416b5c CSINV	W8, W8, WZR, #10

0x416b60 CBZ	W9, 416e4c

0x416b64 STP	W8, WZR, [X29, #500]

0x416b68 MOVZ	W8, #1

0x416b6c ADRP	X0,

0x416b70 ADD	X0, X0, #3320

0x416b74 SUB	X3, X29, #4

0x416b78 STR	WZR, [SP]

0x416b7c SUB	X4, X29, #8

0x416b80 SUB	X5, X29, #12

0x416b84 SUB	X6, X29, #16

0x416b88 MOVZ	W2, #34

0x416b8c STUR	W8, [X29, #496]

0x416b90 MOVZ	W7, #1

0x416b94 BL	410090

0x416b98 LDP	W8, W9, [X29, #500]

0x416b9c SUB	W8, W8, W9

0x416ba0 CMN	W8, #1

0x416ba4 B.EQ	416e2c

0x416ba8 LDR	W11, [SP, #48]

0x416bac CNTD	X16, ALL

0x416bb0 FMOV	D0, #0.2500000

0x416bb4 ORR	W10, WZR, WZR

0x416bb8 ADD	W9, W9, W11

0x416bbc PTRUE	P1.D, ALL

0x416bc0 STR	W9, [SP, #48]

0x416bc4 LDR	X9, [SP, #16]

0x416bc8 LDR	W11, [X9]

0x416bcc LDR	X9, [SP, #32]

0x416bd0 LDR	W15, [X9]

0x416bd4 SUBS	W12, W15, W11

0x416bd8 CSINC	W13, WZR, WZR, #11

0x416bdc ADDS	W12, W12, #1

0x416be0 CSEL	W9, WZR, W13, #0

0x416be4 SUBS	W17, W12, W16

0x416be8 CSEL	W17, WZR, W17, #3

0x416bec WHILELO	P0.D, WZR, W12

0x416bf0 STUR	W9, [X29, #464]

0x416bf4 ADD	W9, W15, #1

0x416bf8 STR	W9, [SP, #44]

0x416bfc B	416c0c

(44) 0x416c00 CMP	W10, W8

(44) 0x416c04 ADD	W10, W10, #1

(44) 0x416c08 B.EQ	416e2c

(44) 0x416c0c LDUR	W9, [X29, #464]

(44) 0x416c10 CBZ	W9, 416c00

(44) 0x416c14 LDR	W9, [SP, #48]

(44) 0x416c18 LDUR	X3, [X29, #456]

(44) 0x416c1c ADD	W0, W9, W10

(44) 0x416c20 LDP	X13, X9, [SP, #64]

(44) 0x416c24 LDR	D1, [X3]

(44) 0x416c28 SBFM	X18, X0, #0, #31

(44) 0x416c2c ADD	W0, W0, #1

(44) 0x416c30 SBFM	X0, X0, #0, #31

(44) 0x416c34 SUB	X1, X18, X13

(44) 0x416c38 SUB	X2, X0, X13

(44) 0x416c3c LDR	W13, [SP, #44]

(44) 0x416c40 MUL	X18, X1, X9

(44) 0x416c44 MUL	X0, X2, X9

(44) 0x416c48 LDR	X9, [SP, #56]

(44) 0x416c4c FMUL	D1, D1, D0

(44) 0x416c50 MUL	X2, X2, X9

(44) 0x416c54 MUL	X1, X1, X9

(44) 0x416c58 ADD	W9, W11, #1

(44) 0x416c5c CMP	W13, W9

(44) 0x416c60 ADD	X2, X23, X2,LSL #3

(44) 0x416c64 B.GE	416d48

(44) 0x416c68 LDUR	X14, [X29, #472]

(44) 0x416c6c LDP	X15, X9, [X29, #952]

(44) 0x416c70 ORR	W3, WZR, WZR

(44) 0x416c74 LDR	X13, [SP, #80]

(44) 0x416c78 HINT	#0

(44) 0x416c7c HINT	#0

  (46) 0x416c80 ADD	W4, W11, W3

  (46) 0x416c84 ADD	W3, W3, #1

  (46) 0x416c88 SBFM	X5, X4, #0, #31

  (46) 0x416c8c ADD	W4, W4, #1

  (46) 0x416c90 CMP	W12, W3

  (46) 0x416c94 SUB	X5, X5, X26

  (46) 0x416c98 SBFM	X4, X4, #0, #31

  (46) 0x416c9c ADD	X6, X5, X18

  (46) 0x416ca0 ADD	X7, X5, X0

  (46) 0x416ca4 SUB	X4, X4, X26

  (46) 0x416ca8 ADD	X28, X5, X1

  (46) 0x416cac LDR	D3, [X21, X6,LSL #3]

  (46) 0x416cb0 LDR	D4, [X21, X7,LSL #3]

  (46) 0x416cb4 ADD	X27, X4, X18

  (46) 0x416cb8 LDR	D16, [X24, X6,LSL #3]

  (46) 0x416cbc ADD	X4, X4, X0

  (46) 0x416cc0 LDR	D2, [X20, X6,LSL #3]

  (46) 0x416cc4 LDR	D18, [X24, X7,LSL #3]

  (46) 0x416cc8 LDR	D17, [X24, X27,LSL #3]

  (46) 0x416ccc LDR	D6, [X21, X27,LSL #3]

  (46) 0x416cd0 LDR	D7, [X21, X4,LSL #3]

  (46) 0x416cd4 LDR	D5, [X20, X27,LSL #3]

  (46) 0x416cd8 LDR	D19, [X24, X4,LSL #3]

  (46) 0x416cdc FADD	D3, D4, D3

  (46) 0x416ce0 LDR	D4, [X23, X28,LSL #3]

  (46) 0x416ce4 FADD	D16, D17, D16

  (46) 0x416ce8 LDR	D17, [X2, X5,LSL #3]

  (46) 0x416cec FADD	D6, D7, D6

  (46) 0x416cf0 FADD	D7, D19, D18

  (46) 0x416cf4 FMUL	D4, D4, D16

  (46) 0x416cf8 FMADD	D2, D2, D3, D4

  (46) 0x416cfc LDR	D3, [X14, X28,LSL #3]

  (46) 0x416d00 FNMSUB	D2, D6, D5, D2

  (46) 0x416d04 LDR	D5, [X9, X28,LSL #3]

  (46) 0x416d08 LDR	D6, [X15, X28,LSL #3]

  (46) 0x416d0c FMADD	D2, D7, D17, D2

  (46) 0x416d10 LDR	D7, [X13, X28,LSL #3]

  (46) 0x416d14 FMUL	D2, D1, D2

  (46) 0x416d18 FADD	D5, D7, D5

  (46) 0x416d1c FADD	D4, D2, D3

  (46) 0x416d20 FMUL	D3, D6, D3

  (46) 0x416d24 FMUL	D2, D5, D2

  (46) 0x416d28 LDR	D5, [X19, X28,LSL #3]

  (46) 0x416d2c FDIV	D2, D2, D3

  (46) 0x416d30 FDIV	D3, D3, D4

  (46) 0x416d34 FSUB	D2, D5, S2

  (46) 0x416d38 STR	D3, [X25, X28,LSL #3]

  (46) 0x416d3c STR	D2, [X22, X28,LSL #3]

  (46) 0x416d40 B.HI	416c80

(44) 0x416d44 B	416c00

(44) 0x416d48 LDUR	X14, [X29, #472]

(44) 0x416d4c LDP	X15, X9, [X29, #952]

(44) 0x416d50 DUP	Z1.D, Z1.D[0]

(44) 0x416d54 SUB	X4, XZR, X16

(44) 0x416d58 ORR	P2.B, P0/Z, P0.B, P0.B

(44) 0x416d5c ORR	W3, WZR, W11

(44) 0x416d60 LDR	X13, [SP, #80]

  (45) 0x416d64 ADD	W27, W3, #1

  (45) 0x416d68 SBFM	X5, X3, #0, #31

  (45) 0x416d6c ADD	W4, W4, W16

  (45) 0x416d70 ADD	W3, W3, W16

  (45) 0x416d74 SBFM	X27, X27, #0, #31

  (45) 0x416d78 SUB	X5, X5, X26

  (45) 0x416d7c SUB	X27, X27, X26

  (45) 0x416d80 ADD	X6, X5, X18

  (45) 0x416d84 ADD	X7, X5, X0

  (45) 0x416d88 ADD	X30, X5, X1

  (45) 0x416d8c ADD	X28, X27, X18

  (45) 0x416d90 ADD	X27, X27, X0

  (45) 0x416d94 LD1D	{Z7.D}, P2/Z, [X24, X6,LSL #3]

  (45) 0x416d98 LD1D	{Z3.D}, P2/Z, [X21, X6,LSL #3]

  (45) 0x416d9c LD1D	{Z4.D}, P2/Z, [X21, X7,LSL #3]

  (45) 0x416da0 LD1D	{Z2.D}, P2/Z, [X20, X6,LSL #3]

  (45) 0x416da4 LD1D	{Z17.D}, P2/Z, [X24, X7,LSL #3]

  (45) 0x416da8 LD1D	{Z5.D}, P2/Z, [X21, X28,LSL #3]

  (45) 0x416dac LD1D	{Z6.D}, P2/Z, [X21, X27,LSL #3]

  (45) 0x416db0 LD1D	{Z16.D}, P2/Z, [X24, X28,LSL #3]

  (45) 0x416db4 LD1D	{Z18.D}, P2/Z, [X24, X27,LSL #3]

  (45) 0x416db8 FADD	Z3.D, Z4.D, Z3.D

  (45) 0x416dbc LD1D	{Z4.D}, P2/Z, [X20, X28,LSL #3]

  (45) 0x416dc0 FADD	Z5.D, Z6.D, Z5.D

  (45) 0x416dc4 LD1D	{Z6.D}, P2/Z, [X23, X30,LSL #3]

  (45) 0x416dc8 FADD	Z7.D, Z16.D, Z7.D

  (45) 0x416dcc LD1D	{Z16.D}, P2/Z, [X2, X5,LSL #3]

  (45) 0x416dd0 FADD	Z17.D, Z18.D, Z17.D

  (45) 0x416dd4 FMUL	Z6.D, Z6.D, Z7.D

  (45) 0x416dd8 FMAD	Z2.D, P1/M, Z3.D, Z6.D

  (45) 0x416ddc LD1D	{Z6.D}, P2/Z, [X13, X30,LSL #3]

  (45) 0x416de0 LD1D	{Z3.D}, P2/Z, [X14, X30,LSL #3]

  (45) 0x416de4 FNMLS	Z2.D, P1/M, Z5.D, Z4.D

  (45) 0x416de8 LD1D	{Z4.D}, P2/Z, [X9, X30,LSL #3]

  (45) 0x416dec LD1D	{Z5.D}, P2/Z, [X15, X30,LSL #3]

  (45) 0x416df0 FMLA	Z2.D, P1/M, Z17.D, Z16.D

  (45) 0x416df4 FMUL	Z2.D, Z1.D, Z2.D

  (45) 0x416df8 FADD	Z4.D, Z6.D, Z4.D

  (45) 0x416dfc FMUL	Z5.D, Z5.D, Z3.D

  (45) 0x416e00 LD1D	{Z6.D}, P2/Z, [X19, X30,LSL #3]

  (45) 0x416e04 FMUL	Z4.D, Z4.D, Z2.D

  (45) 0x416e08 FADD	Z2.D, Z2.D, Z3.D

  (45) 0x416e0c FDIVR	Z2.D, P1/M, Z2.D, Z5.D

  (45) 0x416e10 FDIV	Z4.D, P1/M, Z4.D, Z5.D

  (45) 0x416e14 ST1D	{Z2.D}, P2, [X25, X30,LSL #3]

  (45) 0x416e18 FSUB	Z4.D, Z6.D, Z4.D

  (45) 0x416e1c ST1D	{Z4.D}, P2, [X22, X30,LSL #3]

  (45) 0x416e20 WHILELO	P2.D, W4, W17

  (45) 0x416e24 B.MI	416d64

(44) 0x416e28 B	416c00

0x416e2c LDR	W19, [SP, #28]

0x416e30 ADRP	X0,

0x416e34 ADD	X0, X0, #3320

0x416e38 ORR	W1, WZR, W19

0x416e3c BL	410380

0x416e40 ADRP	X0,

0x416e44 ADD	X0, X0, #3344

0x416e48 B	4171d0

0x416e4c STP	W8, WZR, [X29, #484]

0x416e50 MOVZ	W8, #1

0x416e54 ADRP	X0,

0x416e58 ADD	X0, X0, #3272

0x416e5c SUB	X3, X29, #20

0x416e60 STR	WZR, [SP]

0x416e64 SUB	X4, X29, #24

0x416e68 SUB	X5, X29, #28

0x416e6c SUB	X6, X29, #32

0x416e70 MOVZ	W2, #34

0x416e74 STUR	W8, [X29, #480]

0x416e78 MOVZ	W7, #1

0x416e7c BL	410090

0x416e80 LDP	W8, W10, [X29, #484]

0x416e84 LDUR	X30, [X29, #472]

0x416e88 SUB	W8, W8, W10

0x416e8c CMN	W8, #1

0x416e90 STUR	W8, [X29, #464]

0x416e94 B.EQ	4171b4

0x416e98 LDR	W8, [SP, #48]

0x416e9c CNTD	X16, ALL

0x416ea0 FMOV	D0, #0.2500000

0x416ea4 ORR	W9, WZR, WZR

0x416ea8 ADD	W8, W10, W8

0x416eac PTRUE	P1.D, ALL

0x416eb0 STR	W8, [SP, #44]

0x416eb4 LDR	X8, [SP, #16]

0x416eb8 LDR	W11, [X8]

0x416ebc LDR	X8, [SP, #32]

0x416ec0 LDR	W15, [X8]

0x416ec4 SUBS	W12, W15, W11

0x416ec8 CSINC	W13, WZR, WZR, #11

0x416ecc ADDS	W12, W12, #1

0x416ed0 CSEL	W8, WZR, W13, #0

0x416ed4 SUBS	W17, W12, W16

0x416ed8 CSEL	W17, WZR, W17, #3

0x416edc WHILELO	P0.D, WZR, W12

0x416ee0 STR	W8, [SP, #48]

0x416ee4 ADD	W8, W15, #1

0x416ee8 STR	W8, [SP, #32]

0x416eec B	416f10

0x416ef0 HINT	#0

0x416ef4 HINT	#0

0x416ef8 HINT	#0

0x416efc HINT	#0

(41) 0x416f00 LDUR	W8, [X29, #464]

(41) 0x416f04 CMP	W9, W8

(41) 0x416f08 ADD	W9, W9, #1

(41) 0x416f0c B.EQ	4171b4

(41) 0x416f10 LDR	W8, [SP, #48]

(41) 0x416f14 CBZ	W8, 416f00

(41) 0x416f18 LDR	W8, [SP, #44]

(41) 0x416f1c ADD	W0, W8, W9

(41) 0x416f20 LDP	X10, X8, [SP, #64]

(41) 0x416f24 SBFM	X18, X0, #0, #31

(41) 0x416f28 ADD	W0, W0, #1

(41) 0x416f2c SBFM	X0, X0, #0, #31

(41) 0x416f30 SUB	X1, X18, X10

(41) 0x416f34 SUB	X2, X0, X10

(41) 0x416f38 LDUR	X10, [X29, #456]

(41) 0x416f3c MUL	X18, X1, X8

(41) 0x416f40 MUL	X0, X2, X8

(41) 0x416f44 LDR	X8, [SP, #56]

(41) 0x416f48 LDR	D1, [X10]

(41) 0x416f4c LDR	W10, [SP, #32]

(41) 0x416f50 MUL	X2, X2, X8

(41) 0x416f54 MUL	X1, X1, X8

(41) 0x416f58 ADD	W8, W11, #1

(41) 0x416f5c ADD	X2, X23, X2,LSL #3

(41) 0x416f60 CMP	W10, W8

(41) 0x416f64 FMUL	D1, D1, D0

(41) 0x416f68 B.GE	41708c

(41) 0x416f6c LDP	X13, X15, [X29, #952]

(41) 0x416f70 LDR	X8, [SP, #80]

(41) 0x416f74 ORR	W3, WZR, WZR

(41) 0x416f78 HINT	#0

(41) 0x416f7c HINT	#0

  (43) 0x416f80 ADD	W10, W11, W3

  (43) 0x416f84 ADD	W3, W3, #1

  (43) 0x416f88 SBFM	X14, X10, #0, #31

  (43) 0x416f8c ADD	W10, W10, #1

  (43) 0x416f90 CMP	W12, W3

  (43) 0x416f94 SUB	X14, X14, X26

  (43) 0x416f98 SBFM	X10, X10, #0, #31

  (43) 0x416f9c ADD	X4, X14, X18

  (43) 0x416fa0 ADD	X5, X14, X0

  (43) 0x416fa4 SUB	X10, X10, X26

  (43) 0x416fa8 ADD	X7, X14, X1

  (43) 0x416fac LDR	D3, [X21, X4,LSL #3]

  (43) 0x416fb0 LDR	D4, [X21, X5,LSL #3]

  (43) 0x416fb4 LDR	D5, [X27, X4,LSL #3]

  (43) 0x416fb8 LDR	D6, [X27, X5,LSL #3]

  (43) 0x416fbc ADD	X6, X10, X18

  (43) 0x416fc0 ADD	X10, X10, X0

  (43) 0x416fc4 LDR	D17, [X28, X4,LSL #3]

  (43) 0x416fc8 LDR	D18, [X28, X5,LSL #3]

  (43) 0x416fcc LDR	D2, [X20, X4,LSL #3]

  (43) 0x416fd0 LDR	D7, [X27, X10,LSL #3]

  (43) 0x416fd4 LDR	D16, [X24, X6,LSL #3]

  (43) 0x416fd8 FADD	D3, D4, D3

  (43) 0x416fdc FADD	D4, D5, D6

  (43) 0x416fe0 LDR	D6, [X21, X6,LSL #3]

  (43) 0x416fe4 LDR	D5, [X20, X6,LSL #3]

  (43) 0x416fe8 FADD	D3, D3, D4

  (43) 0x416fec LDR	D4, [X21, X10,LSL #3]

  (43) 0x416ff0 FMUL	D2, D3, D2

  (43) 0x416ff4 FADD	D4, D4, D6

  (43) 0x416ff8 LDR	D6, [X27, X6,LSL #3]

  (43) 0x416ffc FADD	D6, D6, D7

  (43) 0x417000 LDR	D7, [X24, X4,LSL #3]

  (43) 0x417004 FADD	D4, D4, D6

  (43) 0x417008 LDR	D6, [X23, X7,LSL #3]

  (43) 0x41700c FMUL	D4, D4, D5

  (43) 0x417010 FADD	D7, D7, D17

  (43) 0x417014 LDR	D17, [X28, X6,LSL #3]

  (43) 0x417018 FADD	D16, D16, D17

  (43) 0x41701c LDR	D17, [X24, X10,LSL #3]

  (43) 0x417020 FADD	D7, D16, D7

  (43) 0x417024 LDR	D16, [X24, X5,LSL #3]

  (43) 0x417028 FMADD	D2, D7, D6, D2

  (43) 0x41702c LDR	D7, [X8, X7,LSL #3]

  (43) 0x417030 LDR	D6, [X13, X7,LSL #3]

  (43) 0x417034 FADD	D16, D16, D18

  (43) 0x417038 LDR	D18, [X28, X10,LSL #3]

  (43) 0x41703c FADD	D17, D17, D18

  (43) 0x417040 LDR	D18, [X2, X14,LSL #3]

  (43) 0x417044 FADD	D5, D17, D16

  (43) 0x417048 FMADD	D3, D5, D18, D4

  (43) 0x41704c LDR	D5, [X15, X7,LSL #3]

  (43) 0x417050 FSUB	D2, D3, S2

  (43) 0x417054 LDR	D3, [X30, X7,LSL #3]

  (43) 0x417058 FMUL	D2, D1, D2

  (43) 0x41705c FADD	D5, D7, D5

  (43) 0x417060 FADD	D4, D2, D3

  (43) 0x417064 FMUL	D2, D5, D2

  (43) 0x417068 FMUL	D3, D6, D3

  (43) 0x41706c LDR	D5, [X19, X7,LSL #3]

  (43) 0x417070 FDIV	D2, D2, D3

  (43) 0x417074 FDIV	D3, D3, D4

  (43) 0x417078 FSUB	D2, D5, S2

  (43) 0x41707c STR	D3, [X25, X7,LSL #3]

  (43) 0x417080 STR	D2, [X22, X7,LSL #3]

  (43) 0x417084 B.HI	416f80

(41) 0x417088 B	416f00

(41) 0x41708c LDP	X13, X15, [X29, #952]

(41) 0x417090 LDR	X8, [SP, #80]

(41) 0x417094 DUP	Z1.D, Z1.D[0]

(41) 0x417098 SUB	X4, XZR, X16

(41) 0x41709c ORR	P2.B, P0/Z, P0.B, P0.B

(41) 0x4170a0 ORR	W3, WZR, W11

  (42) 0x4170a4 SBFM	X5, X3, #0, #31

  (42) 0x4170a8 ADD	W30, W3, #1

  (42) 0x4170ac ADD	W4, W4, W16

  (42) 0x4170b0 ADD	W3, W3, W16

  (42) 0x4170b4 SUB	X5, X5, X26

  (42) 0x4170b8 SBFM	X30, X30, #0, #31

  (42) 0x4170bc ADD	X6, X5, X18

  (42) 0x4170c0 ADD	X7, X5, X0

  (42) 0x4170c4 SUB	X30, X30, X26

  (42) 0x4170c8 ADD	X10, X5, X1

  (42) 0x4170cc LD1D	{Z3.D}, P2/Z, [X21, X6,LSL #3]

  (42) 0x4170d0 LD1D	{Z4.D}, P2/Z, [X21, X7,LSL #3]

  (42) 0x4170d4 LD1D	{Z5.D}, P2/Z, [X27, X7,LSL #3]

  (42) 0x4170d8 ADD	X14, X30, X18

  (42) 0x4170dc ADD	X30, X30, X0

  (42) 0x4170e0 LD1D	{Z16.D}, P2/Z, [X28, X6,LSL #3]

  (42) 0x4170e4 LD1D	{Z18.D}, P2/Z, [X28, X7,LSL #3]

  (42) 0x4170e8 LD1D	{Z2.D}, P2/Z, [X20, X6,LSL #3]

  (42) 0x4170ec LD1D	{Z6.D}, P2/Z, [X21, X30,LSL #3]

  (42) 0x4170f0 LD1D	{Z7.D}, P2/Z, [X27, X30,LSL #3]

  (42) 0x4170f4 LD1D	{Z17.D}, P2/Z, [X24, X30,LSL #3]

  (42) 0x4170f8 FADD	Z3.D, Z4.D, Z3.D

  (42) 0x4170fc LD1D	{Z4.D}, P2/Z, [X27, X6,LSL #3]

  (42) 0x417100 FADD	Z4.D, Z4.D, Z5.D

  (42) 0x417104 LD1D	{Z5.D}, P2/Z, [X21, X14,LSL #3]

  (42) 0x417108 FADD	Z3.D, Z3.D, Z4.D

  (42) 0x41710c LD1D	{Z4.D}, P2/Z, [X20, X14,LSL #3]

  (42) 0x417110 FMUL	Z2.D, Z3.D, Z2.D

  (42) 0x417114 FADD	Z5.D, Z6.D, Z5.D

  (42) 0x417118 LD1D	{Z6.D}, P2/Z, [X27, X14,LSL #3]

  (42) 0x41711c FADD	Z6.D, Z6.D, Z7.D

  (42) 0x417120 LD1D	{Z7.D}, P2/Z, [X24, X14,LSL #3]

  (42) 0x417124 FADD	Z5.D, Z5.D, Z6.D

  (42) 0x417128 LD1D	{Z6.D}, P2/Z, [X24, X6,LSL #3]

  (42) 0x41712c FMUL	Z4.D, Z5.D, Z4.D

  (42) 0x417130 LD1D	{Z5.D}, P2/Z, [X23, X10,LSL #3]

  (42) 0x417134 FADD	Z6.D, Z6.D, Z16.D

  (42) 0x417138 LD1D	{Z16.D}, P2/Z, [X28, X14,LSL #3]

  (42) 0x41713c FADD	Z7.D, Z7.D, Z16.D

  (42) 0x417140 LD1D	{Z16.D}, P2/Z, [X24, X7,LSL #3]

  (42) 0x417144 FADD	Z6.D, Z7.D, Z6.D

  (42) 0x417148 LD1D	{Z7.D}, P2/Z, [X2, X5,LSL #3]

  (42) 0x41714c FMLA	Z2.D, P1/M, Z6.D, Z5.D

  (42) 0x417150 LD1D	{Z6.D}, P2/Z, [X8, X10,LSL #3]

  (42) 0x417154 LD1D	{Z5.D}, P2/Z, [X13, X10,LSL #3]

  (42) 0x417158 FADD	Z16.D, Z16.D, Z18.D

  (42) 0x41715c LD1D	{Z18.D}, P2/Z, [X28, X30,LSL #3]

  (42) 0x417160 LDUR	X30, [X29, #472]

  (42) 0x417164 LD1D	{Z3.D}, P2/Z, [X30, X10,LSL #3]

  (42) 0x417168 FADD	Z17.D, Z17.D, Z18.D

  (42) 0x41716c FADD	Z16.D, Z17.D, Z16.D

  (42) 0x417170 FMLA	Z4.D, P1/M, Z16.D, Z7.D

  (42) 0x417174 FMUL	Z5.D, Z5.D, Z3.D

  (42) 0x417178 FSUB	Z2.D, Z4.D, Z2.D

  (42) 0x41717c LD1D	{Z4.D}, P2/Z, [X15, X10,LSL #3]

  (42) 0x417180 FMUL	Z2.D, Z1.D, Z2.D

  (42) 0x417184 FADD	Z4.D, Z6.D, Z4.D

  (42) 0x417188 LD1D	{Z6.D}, P2/Z, [X19, X10,LSL #3]

  (42) 0x41718c FMUL	Z4.D, Z4.D, Z2.D

  (42) 0x417190 FADD	Z2.D, Z2.D, Z3.D

  (42) 0x417194 FDIVR	Z2.D, P1/M, Z2.D, Z5.D

  (42) 0x417198 FDIV	Z4.D, P1/M, Z4.D, Z5.D

  (42) 0x41719c ST1D	{Z2.D}, P2, [X25, X10,LSL #3]

  (42) 0x4171a0 FSUB	Z4.D, Z6.D, Z4.D

  (42) 0x4171a4 ST1D	{Z4.D}, P2, [X22, X10,LSL #3]

  (42) 0x4171a8 WHILELO	P2.D, W4, W17

  (42) 0x4171ac B.MI	4170a4

(41) 0x4171b0 B	416f00

0x4171b4 LDR	W19, [SP, #28]

0x4171b8 ADRP	X0,

0x4171bc ADD	X0, X0, #3272

0x4171c0 ORR	W1, WZR, W19

0x4171c4 BL	410380

0x4171c8 ADRP	X0,

0x4171cc ADD	X0, X0, #3296

0x4171d0 ORR	W1, WZR, W19

0x4171d4 BL	410050

0x4171d8 LDP	X20, X19, [SP, #240]

0x4171dc LDP	X22, X21, [SP, #224]

0x4171e0 LDP	X24, X23, [SP, #208]

0x4171e4 LDP	X26, X25, [SP, #192]

0x4171e8 LDP	X28, X27, [SP, #176]

0x4171ec LDP	X29, X30, [SP, #160]

0x4171f0 ADD	SP, SP, #256

0x4171f4 RET

0x4171f8 HINT	#0

0x4171fc HINT	#0

Coverage (%)	Name	Module
►98.43+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run armclang_6

Source file and lines	PdV_kernel.f90:69-87,PdV_kernel.f90:95-99,PdV_kernel.f90:107-123,PdV_kernel.f90:131-135
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:69-87,95-99,107-123,131-135.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.83 to 2.00 cycles (12.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 24.83 to 13.08 cycles (1.90x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:71
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:71
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:71
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:107

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 42 bytes.

General properties

nb instructions	160
nb uops	154
loop length	640
used w registers	15
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	37

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.25 cycles
front end	19.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	17.75	17.75	17.75	17.75	0.50	0.50	0.50	0.50	24.83	24.50	24.67	15.50	15.50
cycles	6.50	6.50	17.75	17.75	17.75	17.75	0.50	0.50	0.50	0.50	24.83	24.50	24.67	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.25
Dispatch	24.83
Overall L1	24.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	40%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	40%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.83 cycles. At this rate:

1% of peak load performance is reached (1.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 416aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X14, X13, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48aac8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X14, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X13, [X2, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X12, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X21, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X28, X13, [X2, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X14, [X2, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [X2, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X25, [X2, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X13, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X19, [X2, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X15, X14, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W8, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W0, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STR W9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W9, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W9, 416e4c <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP W8, WZR, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48ab6c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 416e2c <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W9, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STR W9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUBS W12, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDS W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W9, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W17, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W17, WZR, W17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
STUR W9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W9, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W9, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 416c0c <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48ae30>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48ae40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4171d0 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP W8, WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48ae54>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X30, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STUR W8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 4171b4 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W8, W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STR W8, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUBS W12, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDS W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W8, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W17, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W17, WZR, W17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
STR W8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 416f10 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a1b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a1c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run armclang_6

Source file and lines	PdV_kernel.f90:69-87,PdV_kernel.f90:95-99,PdV_kernel.f90:107-123,PdV_kernel.f90:131-135
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:71
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:71
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:71
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:107

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 42 bytes.

General properties

nb instructions	160
nb uops	154
loop length	640
used w registers	15
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	37

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.25 cycles
front end	19.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	17.75	17.75	17.75	17.75	0.50	0.50	0.50	0.50	24.83	24.50	24.67	15.50	15.50
cycles	6.50	6.50	17.75	17.75	17.75	17.75	0.50	0.50	0.50	0.50	24.83	24.50	24.67	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.25
Dispatch	24.83
Overall L1	24.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	40%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	40%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.83 cycles. At this rate:

1% of peak load performance is reached (1.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 416aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X14, X13, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48aac8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X14, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X13, [X2, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X12, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X21, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X28, X13, [X2, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X14, [X2, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [X2, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X25, [X2, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X13, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X19, [X2, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X15, X14, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W8, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W0, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STR W9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W9, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ W9, 416e4c <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP W8, WZR, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48ab6c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 416e2c <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W9, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STR W9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUBS W12, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDS W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W9, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W17, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W17, WZR, W17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
STUR W9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W9, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W9, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 416c0c <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48ae30>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48ae40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4171d0 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP W8, WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48ae54>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X30, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STUR W8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 4171b4 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W8, W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STR W8, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUBS W12, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDS W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W8, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W17, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W17, WZR, W17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
STR W8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 416f10 <_QMpdv_kernel_modulePpdv_kernel..omp_par+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a1b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a1c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼_QMpdv_kernel_modulePpdv_kernel..omp_par–	14.53	19.82
▼Loop 44 - - exec–	0.01	0.02
○Loop 45 - - exec	6.50	8.86
○Loop 46 - - exec	0.00	0.00
▼Loop 41 - - exec–	0.00	0.02
○Loop 42 - - exec	8.02	10.93
○Loop 43 - - exec	0.00	0.00

Report Configuration

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ASM code

Code clean check

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Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code