OV - exec - Function _QMaccelerate_kernel_modulePaccelerate_kernel..omp

	Function: _QMaccelerate_kernel_modulePaccelerate_kernel..omp_par	Module: exec	Source: :0-0 [...]	Coverage (incl. loops): 7.02% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 55 - 75

--------------------------------------------------------------------------------

55:     halfdt=0.5_8*dt

56:

57:     !$OMP PARALLEL

58:

59:     !$OMP DO PRIVATE(j,k,stepbymass_s)

60:     DO k=y_min,y_max+1

61:     !$OMP SIMD

62:       DO j=x_min,x_max+1

63:         stepbymass_s=halfdt/((density0(j-1,k-1)*volume(j-1,k-1)  &

[...]

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

0x417e60 SUB	SP, SP, #208

0x417e64 STP	X29, X30, [SP, #112]

0x417e68 STP	X28, X27, [SP, #128]

0x417e6c STP	X26, X25, [SP, #144]

0x417e70 STP	X24, X23, [SP, #160]

0x417e74 STP	X22, X21, [SP, #176]

0x417e78 STP	X20, X19, [SP, #192]

0x417e7c ADD	X29, SP, #112

0x417e80 LDP	X15, X14, [X2, #64]

0x417e84 LDP	X8, X9, [X2]

0x417e88 ADRP	X0,

0x417e8c ADD	X0, X0, #3584

0x417e90 LDR	X10, [X2, #16]

0x417e94 LDR	X11, [X2, #32]

0x417e98 LDR	X20, [X2, #160]

0x417e9c STUR	X14, [X29, #488]

0x417ea0 LDP	X14, X22, [X2, #80]

0x417ea4 LDR	X24, [X8]

0x417ea8 LDR	X8, [X9]

0x417eac LDR	X9, [X10]

0x417eb0 LDP	X12, X13, [X2, #48]

0x417eb4 STP	X14, X15, [X29, #976]

0x417eb8 LDP	X23, X14, [X2, #96]

0x417ebc LDP	X25, X26, [X2, #112]

0x417ec0 LDP	X27, X28, [X2, #128]

0x417ec4 LDP	X19, X21, [X2, #144]

0x417ec8 STP	X8, X14, [SP, #48]

0x417ecc LDR	X8, [X11]

0x417ed0 STP	X8, X9, [SP, #32]

0x417ed4 LDR	W8, [X13]

0x417ed8 LDR	W9, [X12]

0x417edc ADD	W8, W8, #1

0x417ee0 STR	W9, [SP, #28]

0x417ee4 SUBS	W8, W8, W9

0x417ee8 CSINV	W8, W8, WZR, #10

0x417eec STP	W8, WZR, [X29, #500]

0x417ef0 MOVZ	W8, #1

0x417ef4 STUR	W8, [X29, #496]

0x417ef8 BL	4101f0

0x417efc ORR	W1, WZR, W0

0x417f00 SUB	X3, X29, #4

0x417f04 SUB	X4, X29, #8

0x417f08 SUB	X5, X29, #12

0x417f0c SUB	X6, X29, #16

0x417f10 STR	WZR, [SP]

0x417f14 ADRP	X0,

0x417f18 ADD	X0, X0, #3584

0x417f1c MOVZ	W2, #34

0x417f20 MOVZ	W7, #1

0x417f24 STR	W1, [SP, #16]

0x417f28 BL	410090

0x417f2c LDP	W8, W10, [X29, #500]

0x417f30 SUB	W8, W8, W10

0x417f34 CMN	W8, #1

0x417f38 STUR	W8, [X29, #480]

0x417f3c B.EQ	4182a0

0x417f40 LDR	W8, [SP, #28]

0x417f44 LDUR	X9, [X29, #488]

0x417f48 LDR	X11, [SP, #56]

0x417f4c FMOV	D0, #0.2500000

0x417f50 PTRUE	P1.D, ALL

0x417f54 FDUP	Z1.D, #80

0x417f58 ADD	W8, W10, W8

0x417f5c LDR	W9, [X9]

0x417f60 STUR	WZR, [X29, #484]

0x417f64 STR	W8, [SP, #28]

0x417f68 LDUR	X8, [X29, #472]

0x417f6c ADD	W13, W9, #1

0x417f70 STR	W9, [SP, #24]

0x417f74 LDR	W8, [X8]

0x417f78 SUB	W14, W9, W8

0x417f7c CMP	W13, W8

0x417f80 ORR	W16, WZR, W8

0x417f84 SUB	W8, W8, #1

0x417f88 ADD	W9, W14, #2

0x417f8c STR	W8, [SP, #20]

0x417f90 CNTD	X8, ALL

0x417f94 CCMP	W9, #0, #4, #10

0x417f98 CSINC	W10, WZR, WZR, #0

0x417f9c SUBS	W17, W9, W8

0x417fa0 CSEL	W8, WZR, W17, #3

0x417fa4 WHILELO	P0.D, WZR, W9

0x417fa8 ORR	W17, WZR, W9

0x417fac STUR	W10, [X29, #472]

0x417fb0 STUR	W8, [X29, #488]

0x417fb4 B	417fd4

0x417fb8 HINT	#0

0x417fbc HINT	#0

  (56) 0x417fc0 LDP	W8, W9, [X29, #480]

  (56) 0x417fc4 CMP	W9, W8

  (56) 0x417fc8 ADD	W8, W9, #1

  (56) 0x417fcc STUR	W8, [X29, #484]

  (56) 0x417fd0 B.EQ	4182a0

  (56) 0x417fd4 LDUR	W8, [X29, #472]

  (56) 0x417fd8 CBZ	W8, 417fc0

  (56) 0x417fdc LDUR	W8, [X29, #484]

  (56) 0x417fe0 LDR	W9, [SP, #28]

  (56) 0x417fe4 ADD	W0, W9, W8

  (56) 0x417fe8 LDUR	X8, [X29, #464]

  (56) 0x417fec SUB	W18, W0, #1

  (56) 0x417ff0 SBFM	X0, X0, #0, #31

  (56) 0x417ff4 SBFM	X18, X18, #0, #31

  (56) 0x417ff8 LDR	D2, [X8]

  (56) 0x417ffc LDP	X9, X8, [SP, #40]

  (56) 0x418000 SUB	X2, X18, X9

  (56) 0x418004 SUB	X1, X0, X9

  (56) 0x418008 MUL	X18, X2, X8

  (56) 0x41800c MUL	X0, X1, X8

  (56) 0x418010 LDR	X8, [SP, #32]

  (56) 0x418014 ADD	X3, X26, X18,LSL #3

  (56) 0x418018 ADD	X4, X20, X0,LSL #3

  (56) 0x41801c ADD	X5, X20, X18,LSL #3

  (56) 0x418020 MUL	X1, X1, X8

  (56) 0x418024 MUL	X2, X2, X8

  (56) 0x418028 LDP	W9, W8, [SP, #20]

  (56) 0x41802c ADD	X2, X25, X2,LSL #3

  (56) 0x418030 ADD	X6, X21, X1,LSL #3

  (56) 0x418034 CMP	W8, W9

  (56) 0x418038 B.GE	418160

  (56) 0x41803c LDR	X15, [SP, #56]

  (56) 0x418040 ORR	W7, WZR, WZR

    (58) 0x418044 ADD	W8, W16, W7

    (58) 0x418048 ADD	W7, W7, #1

    (58) 0x41804c SUB	W9, W8, #1

    (58) 0x418050 SBFM	X8, X8, #0, #31

    (58) 0x418054 CMP	W17, W7

    (58) 0x418058 SBFM	X9, X9, #0, #31

    (58) 0x41805c SUB	X30, X8, X24

    (58) 0x418060 SUB	X9, X9, X24

    (58) 0x418064 ADD	X8, X30, X18

    (58) 0x418068 ADD	X12, X30, X0

    (58) 0x41806c ADD	X14, X30, X1

    (58) 0x418070 LDR	D21, [X3, X30,LSL #3]

    (58) 0x418074 LDR	D17, [X2, X30,LSL #3]

    (58) 0x418078 ADD	X10, X9, X18

    (58) 0x41807c LDR	D5, [X23, X8,LSL #3]

    (58) 0x418080 ADD	X13, X9, X0

    (58) 0x418084 LDR	D6, [X26, X12,LSL #3]

    (58) 0x418088 LDR	D18, [X26, X8,LSL #3]

    (58) 0x41808c LDR	D20, [X19, X12,LSL #3]

    (58) 0x418090 LDR	D3, [X22, X10,LSL #3]

    (58) 0x418094 LDR	D4, [X23, X10,LSL #3]

    (58) 0x418098 LDR	D7, [X26, X13,LSL #3]

    (58) 0x41809c LDR	D19, [X26, X10,LSL #3]

    (58) 0x4180a0 FMUL	D3, D4, D3

    (58) 0x4180a4 LDR	D4, [X22, X8,LSL #3]

    (58) 0x4180a8 FSUB	D16, D7, S6

    (58) 0x4180ac FSUB	D18, D19, S18

    (58) 0x4180b0 FSUB	D6, D21, S6

    (58) 0x4180b4 LDR	D21, [X3, X9,LSL #3]

    (58) 0x4180b8 LDR	D19, [X28, X14,LSL #3]

    (58) 0x4180bc FMUL	D6, D6, D20

    (58) 0x4180c0 FMADD	D3, D5, D4, D3

    (58) 0x4180c4 LDR	D4, [X22, X12,LSL #3]

    (58) 0x4180c8 LDR	D5, [X23, X12,LSL #3]

    (58) 0x4180cc FSUB	D7, D21, S7

    (58) 0x4180d0 LDR	D21, [X5, X9,LSL #3]

    (58) 0x4180d4 FMADD	D3, D5, D4, D3

    (58) 0x4180d8 LDR	D4, [X22, X13,LSL #3]

    (58) 0x4180dc LDR	D5, [X23, X13,LSL #3]

    (58) 0x4180e0 FMADD	D3, D5, D4, D3

    (58) 0x4180e4 LDR	D5, [X25, X14,LSL #3]

    (58) 0x4180e8 LDR	D4, [X15, X14,LSL #3]

    (58) 0x4180ec FMUL	D3, D3, D0

    (58) 0x4180f0 FMUL	D16, D16, D5

    (58) 0x4180f4 FDIV	D3, D2, D3

    (58) 0x4180f8 FMADD	D16, D18, D17, D16

    (58) 0x4180fc LDR	D18, [X19, X13,LSL #3]

    (58) 0x418100 FMADD	D6, D7, D18, D6

    (58) 0x418104 LDR	D7, [X4, X30,LSL #3]

    (58) 0x418108 FMADD	D6, D6, D3, D19

    (58) 0x41810c LDR	D19, [X4, X9,LSL #3]

    (58) 0x418110 STR	D6, [X21, X14,LSL #3]

    (58) 0x418114 LDR	D6, [X20, X13,LSL #3]

    (58) 0x418118 FSUB	D7, D19, S7

    (58) 0x41811c LDR	D19, [X5, X30,LSL #3]

    (58) 0x418120 FMADD	D5, D7, D5, D16

    (58) 0x418124 FSUB	D6, D21, S6

    (58) 0x418128 FSUB	D7, D21, S19

    (58) 0x41812c FMADD	D5, D7, D17, D5

    (58) 0x418130 FMADD	D4, D5, D3, D4

    (58) 0x418134 LDR	D5, [X6, X30,LSL #3]

    (58) 0x418138 STR	D4, [X27, X14,LSL #3]

    (58) 0x41813c LDR	D4, [X20, X12,LSL #3]

    (58) 0x418140 FSUB	D4, D19, S4

    (58) 0x418144 FMUL	D4, D4, D20

    (58) 0x418148 FMADD	D4, D6, D18, D4

    (58) 0x41814c FMADD	D3, D4, D3, D5

    (58) 0x418150 STR	D3, [X6, X30,LSL #3]

    (58) 0x418154 B.HI	418044

  (56) 0x418158 B	417fc0

0x41815c HINT	#0

(57) 0x418160 CNTD	X8, ALL

(57) 0x418164 DUP	Z2.D, Z2.D[0]

(57) 0x418168 ORR	W7, WZR, W16

(57) 0x41816c SUB	X30, XZR, X8

(57) 0x418170 ORR	P2.B, P0/Z, P0.B, P0.B

(57) 0x418174 HINT	#0

(57) 0x418178 HINT	#0

(57) 0x41817c HINT	#0

  (55) 0x418180 SUB	W15, W7, #1

  (55) 0x418184 SBFM	X12, X7, #0, #31

  (55) 0x418188 SBFM	X15, X15, #0, #31

  (55) 0x41818c SUB	X12, X12, X24

  (55) 0x418190 SUB	X15, X15, X24

  (55) 0x418194 ADD	X8, X12, X18

  (55) 0x418198 ADD	X14, X12, X0

  (55) 0x41819c ADD	X13, X12, X1

  (55) 0x4181a0 LD1D	{Z20.D}, P2/Z, [X3, X12,LSL #3]

  (55) 0x4181a4 LD1D	{Z17.D}, P2/Z, [X2, X12,LSL #3]

  (55) 0x4181a8 ADD	X10, X15, X18

  (55) 0x4181ac LD1D	{Z5.D}, P2/Z, [X23, X8,LSL #3]

  (55) 0x4181b0 ADD	X9, X15, X0

  (55) 0x4181b4 LD1D	{Z6.D}, P2/Z, [X26, X14,LSL #3]

  (55) 0x4181b8 LD1D	{Z18.D}, P2/Z, [X26, X8,LSL #3]

  (55) 0x4181bc LD1D	{Z21.D}, P2/Z, [X3, X15,LSL #3]

  (55) 0x4181c0 LD1D	{Z3.D}, P2/Z, [X22, X10,LSL #3]

  (55) 0x4181c4 LD1D	{Z4.D}, P2/Z, [X23, X10,LSL #3]

  (55) 0x4181c8 LD1D	{Z7.D}, P2/Z, [X26, X9,LSL #3]

  (55) 0x4181cc LD1D	{Z19.D}, P2/Z, [X26, X10,LSL #3]

  (55) 0x4181d0 FMUL	Z3.D, Z4.D, Z3.D

  (55) 0x4181d4 LD1D	{Z4.D}, P2/Z, [X22, X8,LSL #3]

  (55) 0x4181d8 FSUB	Z16.D, Z7.D, Z6.D

  (55) 0x4181dc FSUB	Z18.D, Z19.D, Z18.D

  (55) 0x4181e0 LD1D	{Z19.D}, P2/Z, [X19, X14,LSL #3]

  (55) 0x4181e4 FSUB	Z6.D, Z20.D, Z6.D

  (55) 0x4181e8 LD1D	{Z20.D}, P2/Z, [X19, X9,LSL #3]

  (55) 0x4181ec FSUB	Z7.D, Z21.D, Z7.D

  (55) 0x4181f0 CNTD	X8, ALL

  (55) 0x4181f4 ADD	W30, W30, W8

  (55) 0x4181f8 ADD	W7, W7, W8

  (55) 0x4181fc LDUR	W8, [X29, #488]

  (55) 0x418200 FMLA	Z3.D, P1/M, Z5.D, Z4.D

  (55) 0x418204 LD1D	{Z4.D}, P2/Z, [X22, X14,LSL #3]

  (55) 0x418208 LD1D	{Z5.D}, P2/Z, [X23, X14,LSL #3]

  (55) 0x41820c FMUL	Z6.D, Z6.D, Z19.D

  (55) 0x418210 FMLA	Z6.D, P1/M, Z7.D, Z20.D

  (55) 0x418214 LD1D	{Z7.D}, P2/Z, [X4, X15,LSL #3]

  (55) 0x418218 FMLA	Z3.D, P1/M, Z5.D, Z4.D

  (55) 0x41821c LD1D	{Z4.D}, P2/Z, [X22, X9,LSL #3]

  (55) 0x418220 LD1D	{Z5.D}, P2/Z, [X23, X9,LSL #3]

  (55) 0x418224 FMLA	Z3.D, P1/M, Z5.D, Z4.D

  (55) 0x418228 LD1D	{Z5.D}, P2/Z, [X25, X13,LSL #3]

  (55) 0x41822c LD1D	{Z4.D}, P2/Z, [X11, X13,LSL #3]

  (55) 0x418230 FMUL	Z3.D, Z3.D, Z1.D

  (55) 0x418234 FMUL	Z16.D, Z16.D, Z5.D

  (55) 0x418238 FDIVR	Z3.D, P1/M, Z3.D, Z2.D

  (55) 0x41823c FMLA	Z16.D, P1/M, Z18.D, Z17.D

  (55) 0x418240 LD1D	{Z18.D}, P2/Z, [X28, X13,LSL #3]

  (55) 0x418244 FMAD	Z6.D, P1/M, Z3.D, Z18.D

  (55) 0x418248 LD1D	{Z18.D}, P2/Z, [X5, X15,LSL #3]

  (55) 0x41824c ST1D	{Z6.D}, P2, [X21, X13,LSL #3]

  (55) 0x418250 LD1D	{Z6.D}, P2/Z, [X4, X12,LSL #3]

  (55) 0x418254 FSUB	Z6.D, Z7.D, Z6.D

  (55) 0x418258 LD1D	{Z7.D}, P2/Z, [X5, X12,LSL #3]

  (55) 0x41825c FMAD	Z5.D, P1/M, Z6.D, Z16.D

  (55) 0x418260 LD1D	{Z6.D}, P2/Z, [X20, X9,LSL #3]

  (55) 0x418264 FSUB	Z21.D, Z18.D, Z7.D

  (55) 0x418268 FMLA	Z5.D, P1/M, Z21.D, Z17.D

  (55) 0x41826c FSUB	Z6.D, Z18.D, Z6.D

  (55) 0x418270 FMLA	Z4.D, P1/M, Z5.D, Z3.D

  (55) 0x418274 LD1D	{Z5.D}, P2/Z, [X20, X14,LSL #3]

  (55) 0x418278 FSUB	Z5.D, Z7.D, Z5.D

  (55) 0x41827c ST1D	{Z4.D}, P2, [X27, X13,LSL #3]

  (55) 0x418280 LD1D	{Z4.D}, P2/Z, [X6, X12,LSL #3]

  (55) 0x418284 FMUL	Z5.D, Z5.D, Z19.D

  (55) 0x418288 FMLA	Z5.D, P1/M, Z6.D, Z20.D

  (55) 0x41828c FMAD	Z3.D, P1/M, Z5.D, Z4.D

  (55) 0x418290 ST1D	{Z3.D}, P2, [X6, X12,LSL #3]

  (55) 0x418294 WHILELO	P2.D, W30, W8

  (55) 0x418298 B.MI	418180

(57) 0x41829c B	417fc0

0x4182a0 LDR	W19, [SP, #16]

0x4182a4 ADRP	X0,

0x4182a8 ADD	X0, X0, #3584

0x4182ac ORR	W1, WZR, W19

0x4182b0 BL	410380

0x4182b4 ADRP	X0,

0x4182b8 ADD	X0, X0, #3608

0x4182bc ORR	W1, WZR, W19

0x4182c0 BL	410050

0x4182c4 LDP	X20, X19, [SP, #192]

0x4182c8 LDP	X22, X21, [SP, #176]

0x4182cc LDP	X24, X23, [SP, #160]

0x4182d0 LDP	X26, X25, [SP, #144]

0x4182d4 LDP	X28, X27, [SP, #128]

0x4182d8 LDP	X29, X30, [SP, #112]

0x4182dc ADD	SP, SP, #208

0x4182e0 RET

0x4182e4 HINT	#0

0x4182e8 HINT	#0

0x4182ec HINT	#0

0x4182f0 HINT	#0

0x4182f4 HINT	#0

0x4182f8 HINT	#0

0x4182fc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	accelerate_kernel	accelerate_kernel.f90:83	exec
○	accelerate	accelerate.f90:41	exec
○	hydro	hydro.f90:58	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_6

Source file and lines	accelerate_kernel.f90:55-63,accelerate_kernel.f90:69-75
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:55-63,69-75.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.67 to 1.00 cycles (17.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 17.67 to 9.85 cycles (1.79x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 18 bytes. The binary function is storing 33 bytes.

General properties

nb instructions	113
nb uops	103
loop length	452
used w registers	13
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	1
nb stack references	23

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.88 cycles
front end	12.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.25	11.25	11.25	11.25	0.50	0.50	0.50	0.50	17.67	17.67	17.67	11.00	11.00
cycles	3.50	3.50	11.25	11.25	11.25	11.25	0.50	0.50	0.50	0.50	17.67	17.67	17.67	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.88
Dispatch	17.67
Overall L1	17.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	43%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

INT+FP

all	29%
load	43%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.67 cycles. At this rate:

1% of peak load performance is reached (1.02 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.87 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 417e60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X15, X14, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48ae88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X14, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X22, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X15, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X14, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X21, [X2, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X8, X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W9, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X3, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADRP X0, <48af14>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STUR W8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 4182a0 <_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z1.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
ADD W8, W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W8, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W13, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W14, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ORR W16, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CCMP W9, #0, #4, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W10, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W17, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W8, WZR, W17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, WZR, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ORR W17, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 417fd4 <_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a2a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a2b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3608	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_6

Source file and lines	accelerate_kernel.f90:55-63,accelerate_kernel.f90:69-75
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 18 bytes. The binary function is storing 33 bytes.

General properties

nb instructions	113
nb uops	103
loop length	452
used w registers	13
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	1
nb stack references	23

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.88 cycles
front end	12.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.25	11.25	11.25	11.25	0.50	0.50	0.50	0.50	17.67	17.67	17.67	11.00	11.00
cycles	3.50	3.50	11.25	11.25	11.25	11.25	0.50	0.50	0.50	0.50	17.67	17.67	17.67	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.88
Dispatch	17.67
Overall L1	17.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	43%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

INT+FP

all	29%
load	43%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.67 cycles. At this rate:

1% of peak load performance is reached (1.02 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.87 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 417e60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X15, X14, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48ae88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X14, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X22, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X15, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X14, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X21, [X2, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X8, X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W9, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X3, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADRP X0, <48af14>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STUR W8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 4182a0 <_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z1.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
ADD W8, W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W8, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W13, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W14, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ORR W16, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CCMP W9, #0, #4, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W10, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W17, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W8, WZR, W17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, WZR, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ORR W17, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 417fd4 <_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a2a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a2b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3608	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par–	7.02	9.58
▼Loop 57 - - exec–	0.00	0.00
○Loop 55 - - exec	7.01	9.56
▼Loop 56 - - exec–	0.00	0.02
○Loop 58 - - exec	0.00	0.00

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Front-end bottlenecks

ASM code