OV - exec - Function _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp

	Function: _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par	Module: exec	Source: :0-0 [...]	Coverage (incl. loops): 18.73% \| (excl. loops): 0.02%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 83 - 261

--------------------------------------------------------------------------------

83:     IF(dir.EQ.g_xdir) THEN

84:

85:       IF(sweep_number.EQ.1)THEN

86:         !$OMP DO

87:         DO k=y_min-2,y_max+2

88:         !$OMP SIMD

89:           DO j=x_min-2,x_max+2

90:             pre_vol(j,k)=volume(j,k)+(vol_flux_x(j+1,k  )-vol_flux_x(j,k)+vol_flux_y(j  ,k+1)-vol_flux_y(j,k))

91:             post_vol(j,k)=pre_vol(j,k)-(vol_flux_x(j+1,k  )-vol_flux_x(j,k))

92:           ENDDO

93:         ENDDO

94:       !$OMP END DO

95:       ELSE

96:         !$OMP DO

97:         DO k=y_min-2,y_max+2

98:         !$OMP SIMD

99:           DO j=x_min-2,x_max+2

100:             pre_vol(j,k)=volume(j,k)+vol_flux_x(j+1,k)-vol_flux_x(j,k)

101:             post_vol(j,k)=volume(j,k)

102:           ENDDO

103:         ENDDO

104:       !$OMP END DO

105:       ENDIF

106:

107:       !$OMP DO PRIVATE(upwind,donor,downwind,dif,sigmat,sigma3,sigma4,sigmav,sigma,sigmam, &

108:       !$OMP            diffuw,diffdw,limiter,wind)

109:       DO k=y_min,y_max

110:         DO j=x_min,x_max+2

111:

112:           IF(vol_flux_x(j,k).GT.0.0)THEN

113:             upwind   =j-2

114:             donor    =j-1

115:             downwind =j

116:             dif      =donor

117:           ELSE

118:             upwind   =MIN(j+1,x_max+2)

[...]

124:           sigmat=ABS(vol_flux_x(j,k))/pre_vol(donor,k)

125:           sigma3=(1.0_8+sigmat)*(vertexdx(j)/vertexdx(dif))

126:           sigma4=2.0_8-sigmat

127:

128:           sigma=sigmat

129:           sigmav=sigmat

130:

131:           diffuw=density1(donor,k)-density1(upwind,k)

132:           diffdw=density1(downwind,k)-density1(donor,k)

133:           wind=1.0_8

134:           IF(diffdw.LE.0.0) wind=-1.0_8

135:           IF(diffuw*diffdw.GT.0.0)THEN

136:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

137:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

138:           ELSE

139:             limiter=0.0

140:           ENDIF

141:           mass_flux_x(j,k)=vol_flux_x(j,k)*(density1(donor,k)+limiter)

142:

143:           sigmam=ABS(mass_flux_x(j,k))/(density1(donor,k)*pre_vol(donor,k))

144:           diffuw=energy1(donor,k)-energy1(upwind,k)

145:           diffdw=energy1(downwind,k)-energy1(donor,k)

146:           wind=1.0_8

147:           IF(diffdw.LE.0.0) wind=-1.0_8

148:           IF(diffuw*diffdw.GT.0.0)THEN

149:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

[...]

155:           ener_flux(j,k)=mass_flux_x(j,k)*(energy1(donor,k)+limiter)

156:

157:         ENDDO

158:       ENDDO

159:       !$OMP END DO

160:

161:       !$OMP DO PRIVATE(pre_mass_s,post_mass_s,post_ener_s,advec_vol_s)

162:       DO k=y_min,y_max

163:       !$OMP SIMD

164:         DO j=x_min,x_max

165:           pre_mass_s=density1(j,k)*pre_vol(j,k)

166:           post_mass_s=pre_mass_s+mass_flux_x(j,k)-mass_flux_x(j+1,k)

167:           post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j+1,k))/post_mass_s

168:           advec_vol_s=pre_vol(j,k)+vol_flux_x(j,k)-vol_flux_x(j+1,k)

169:           density1(j,k)=post_mass_s/advec_vol_s

170:           energy1(j,k)=post_ener_s

[...]

177:       IF(sweep_number.EQ.1)THEN

178:         !$OMP DO

179:         DO k=y_min-2,y_max+2

180:         !$OMP SIMD

181:           DO j=x_min-2,x_max+2

182:             pre_vol(j,k)=volume(j,k)+(vol_flux_y(j  ,k+1)-vol_flux_y(j,k)+vol_flux_x(j+1,k  )-vol_flux_x(j,k))

183:             post_vol(j,k)=pre_vol(j,k)-(vol_flux_y(j  ,k+1)-vol_flux_y(j,k))

184:           ENDDO

185:         ENDDO

186:       !$OMP END DO

187:       ELSE

188:         !$OMP DO

189:         DO k=y_min-2,y_max+2

190:         !$OMP SIMD

191:           DO j=x_min-2,x_max+2

192:             pre_vol(j,k)=volume(j,k)+vol_flux_y(j  ,k+1)-vol_flux_y(j,k)

193:             post_vol(j,k)=volume(j,k)

194:           ENDDO

195:         ENDDO

196:       !$OMP END DO

197:       ENDIF

198:

199:       !$OMP DO PRIVATE(upwind,donor,downwind,dif,sigmat,sigma3,sigma4,sigmav,sigma,sigmam, &

200:       !$OMP            diffuw,diffdw,limiter,wind)

201:       DO k=y_min,y_max+2

202:         DO j=x_min,x_max

203:

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

210:             upwind   =MIN(k+1,y_max+2)

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

247:

248:         ENDDO

249:       ENDDO

250:       !$OMP END DO

251:

252:       !$OMP DO PRIVATE(pre_mass_s,post_mass_s,post_ener_s,advec_vol_s)

253:       DO k=y_min,y_max

254:       !$OMP SIMD

255:         DO j=x_min,x_max

256:           pre_mass_s=density1(j,k)*pre_vol(j,k)

257:           post_mass_s=pre_mass_s+mass_flux_y(j,k)-mass_flux_y(j,k+1)

258:           post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j,k+1))/post_mass_s

259:           advec_vol_s=pre_vol(j,k)+vol_flux_y(j,k)-vol_flux_y(j,k+1)

260:           density1(j,k)=post_mass_s/advec_vol_s

261:           energy1(j,k)=post_ener_s

0x418ae0 SUB	SP, SP, #400

0x418ae4 STP	X29, X30, [SP, #304]

0x418ae8 STP	X28, X27, [SP, #320]

0x418aec STP	X26, X25, [SP, #336]

0x418af0 STP	X24, X23, [SP, #352]

0x418af4 STP	X22, X21, [SP, #368]

0x418af8 STP	X20, X19, [SP, #384]

0x418afc ADD	X29, SP, #304

0x418b00 LDP	X15, X13, [X2, #64]

0x418b04 LDP	X8, X9, [X2]

0x418b08 ADRP	X0,

0x418b0c ADD	X0, X0, #40

0x418b10 LDR	X10, [X2, #16]

0x418b14 LDR	X11, [X2, #32]

0x418b18 STR	X13, [SP, #144]

0x418b1c LDR	X13, [X2, #80]

0x418b20 LDP	X12, X14, [X2, #48]

0x418b24 LDR	X24, [X8]

0x418b28 LDR	X8, [X9]

0x418b2c LDR	W23, [X12]

0x418b30 LDP	X21, X28, [X2, #104]

0x418b34 STR	X13, [SP, #8]

0x418b38 LDP	X13, X20, [X2, #88]

0x418b3c STR	X8, [SP, #136]

0x418b40 LDR	X8, [X10]

0x418b44 LDP	X19, X25, [X2, #168]

0x418b48 STP	X13, X15, [SP, #16]

0x418b4c LDP	X22, X13, [X2, #120]

0x418b50 STP	X14, X13, [SP, #96]

0x418b54 LDP	X27, X13, [X2, #136]

0x418b58 LDP	X26, X14, [X2, #152]

0x418b5c STUR	X13, [X29, #368]

0x418b60 LDR	X13, [X2, #184]

0x418b64 STP	X14, X8, [SP, #112]

0x418b68 LDR	X8, [X11]

0x418b6c STR	X13, [SP, #152]

0x418b70 STR	X8, [SP, #128]

0x418b74 BL	4101f0

0x418b78 CMP	W23, #1

0x418b7c STR	W0, [SP, #36]

0x418b80 B.EQ	418d94

0x418b84 CMP	W23, #2

0x418b88 B.NE	419e00

0x418b8c LDR	X8, [SP, #96]

0x418b90 LDR	W9, [X8]

0x418b94 LDR	X8, [SP, #24]

0x418b98 LDR	W8, [X8]

0x418b9c SUB	W25, W8, #2

0x418ba0 LDR	X8, [SP, #144]

0x418ba4 LDR	W8, [X8]

0x418ba8 ADD	W8, W8, #2

0x418bac SUBS	W8, W8, W25

0x418bb0 CSINV	W8, W8, WZR, #10

0x418bb4 CMP	W9, #1

0x418bb8 B.NE	418fac

0x418bbc LDR	W1, [SP, #36]

0x418bc0 STP	W8, WZR, [X29, #396]

0x418bc4 MOVZ	W8, #1

0x418bc8 ADRP	X0,

0x418bcc ADD	X0, X0, #3800

0x418bd0 SUB	X3, X29, #108

0x418bd4 SUB	X4, X29, #112

0x418bd8 SUB	X5, X29, #116

0x418bdc SUB	X6, X29, #120

0x418be0 MOVZ	W2, #34

0x418be4 STUR	W8, [X29, #392]

0x418be8 STR	WZR, [SP]

0x418bec MOVZ	W7, #1

0x418bf0 BL	410090

0x418bf4 LDP	W8, W9, [X29, #396]

0x418bf8 LDR	X7, [SP, #112]

0x418bfc SUB	W8, W8, W9

0x418c00 CMN	W8, #1

0x418c04 B.EQ	4191c0

0x418c08 LDP	X11, X13, [SP, #8]

0x418c0c ADD	W9, W9, W25

0x418c10 ORR	W10, WZR, WZR

0x418c14 LDR	W11, [X11]

0x418c18 LDR	W14, [X13]

0x418c1c SUB	W12, W11, #2

0x418c20 ADD	W13, W14, #2

0x418c24 SUB	W15, W14, W11

0x418c28 SUB	W16, W11, #1

0x418c2c ADD	W14, W14, #3

0x418c30 CMP	W13, W12

0x418c34 CSINC	W13, WZR, WZR, #11

0x418c38 ADD	W12, W15, #5

0x418c3c CSINC	W15, WZR, WZR, #10

0x418c40 CMP	W12, #0

0x418c44 CSEL	W13, WZR, W13, #0

0x418c48 CMP	W14, W16

0x418c4c CSINC	W14, W15, WZR, #10

0x418c50 CNTD	X15, ALL

0x418c54 SUBS	W16, W12, W15

0x418c58 CSEL	W16, WZR, W16, #3

0x418c5c WHILELO	P0.D, WZR, W12

0x418c60 B	418c70

(81) 0x418c64 CMP	W10, W8

(81) 0x418c68 ADD	W10, W10, #1

(81) 0x418c6c B.EQ	4191c0

(81) 0x418c70 CBZ	W13, 418c64

(81) 0x418c74 LDR	X2, [SP, #120]

(81) 0x418c78 ADD	W18, W9, W10

(81) 0x418c7c LDP	X1, X3, [SP, #128]

(81) 0x418c80 SUB	X4, XZR, X15

(81) 0x418c84 ORR	P1.B, P0/Z, P0.B, P0.B

(81) 0x418c88 SBFM	X17, X18, #0, #31

(81) 0x418c8c ADD	W18, W18, #1

(81) 0x418c90 SBFM	X18, X18, #0, #31

(81) 0x418c94 SUB	X0, X17, X2

(81) 0x418c98 SUB	X18, X18, X2

(81) 0x418c9c MUL	X17, X0, X3

(81) 0x418ca0 MUL	X18, X18, X3

(81) 0x418ca4 MUL	X0, X0, X1

(81) 0x418ca8 SUB	W3, W11, #1

(81) 0x418cac ADD	X18, X27, X18,LSL #3

(81) 0x418cb0 ADD	X1, X19, X0,LSL #3

(81) 0x418cb4 ADD	X2, X27, X17,LSL #3

(81) 0x418cb8 TBZ	W14, #0, 418d2c

(81) 0x418cbc ORR	W3, WZR, WZR

  (83) 0x418cc0 ADD	W4, W11, W3

  (83) 0x418cc4 ADD	W3, W3, #1

  (83) 0x418cc8 SUB	W5, W4, #2

  (83) 0x418ccc SUB	W4, W4, #1

  (83) 0x418cd0 CMP	W12, W3

  (83) 0x418cd4 SBFM	X5, X5, #0, #31

  (83) 0x418cd8 SBFM	X4, X4, #0, #31

  (83) 0x418cdc SUB	X5, X5, X24

  (83) 0x418ce0 SUB	X4, X4, X24

  (83) 0x418ce4 LDR	D1, [X18, X5,LSL #3]

  (83) 0x418ce8 LDR	D3, [X1, X4,LSL #3]

  (83) 0x418cec ADD	X6, X5, X17

  (83) 0x418cf0 ADD	X4, X5, X0

  (83) 0x418cf4 LDR	D0, [X26, X6,LSL #3]

  (83) 0x418cf8 LDR	D2, [X27, X6,LSL #3]

  (83) 0x418cfc LDR	D4, [X19, X4,LSL #3]

  (83) 0x418d00 FADD	D3, D1, D3

  (83) 0x418d04 FADD	D2, D2, D4

  (83) 0x418d08 FADD	D0, D3, D0

  (83) 0x418d0c FSUB	D0, D0, S2

  (83) 0x418d10 LDR	D2, [X2, X5,LSL #3]

  (83) 0x418d14 STR	D0, [X21, X4,LSL #3]

  (83) 0x418d18 FSUB	D1, D2, S1

  (83) 0x418d1c FADD	D0, D1, D0

  (83) 0x418d20 STR	D0, [X7, X4,LSL #3]

  (83) 0x418d24 B.HI	418cc0

(81) 0x418d28 B	418c64

  (82) 0x418d2c SUB	W5, W3, #1

  (82) 0x418d30 ADD	W4, W4, W15

  (82) 0x418d34 SBFM	X5, X5, #0, #31

  (82) 0x418d38 SUB	X5, X5, X24

  (82) 0x418d3c ADD	X6, X5, X17

  (82) 0x418d40 LD1D	{Z1.D}, P1/Z, [X18, X5,LSL #3]

  (82) 0x418d44 LD1D	{Z0.D}, P1/Z, [X26, X6,LSL #3]

  (82) 0x418d48 LD1D	{Z2.D}, P1/Z, [X27, X6,LSL #3]

  (82) 0x418d4c SBFM	X6, X3, #0, #31

  (82) 0x418d50 ADD	W3, W3, W15

  (82) 0x418d54 SUB	X6, X6, X24

  (82) 0x418d58 LD1D	{Z3.D}, P1/Z, [X1, X6,LSL #3]

  (82) 0x418d5c ADD	X6, X5, X0

  (82) 0x418d60 LD1D	{Z4.D}, P1/Z, [X19, X6,LSL #3]

  (82) 0x418d64 FADD	Z3.D, Z1.D, Z3.D

  (82) 0x418d68 FADD	Z2.D, Z2.D, Z4.D

  (82) 0x418d6c FADD	Z0.D, Z3.D, Z0.D

  (82) 0x418d70 FSUB	Z0.D, Z0.D, Z2.D

  (82) 0x418d74 LD1D	{Z2.D}, P1/Z, [X2, X5,LSL #3]

  (82) 0x418d78 ST1D	{Z0.D}, P1, [X21, X6,LSL #3]

  (82) 0x418d7c FSUB	Z1.D, Z2.D, Z1.D

  (82) 0x418d80 FADD	Z0.D, Z1.D, Z0.D

  (82) 0x418d84 ST1D	{Z0.D}, P1, [X7, X6,LSL #3]

  (82) 0x418d88 WHILELO	P1.D, W4, W16

  (82) 0x418d8c B.MI	418d2c

(81) 0x418d90 B	418c64

0x418d94 LDR	X8, [SP, #96]

0x418d98 LDR	W9, [X8]

0x418d9c LDR	X8, [SP, #24]

0x418da0 LDR	W8, [X8]

0x418da4 SUB	W23, W8, #2

0x418da8 LDR	X8, [SP, #144]

0x418dac LDR	W8, [X8]

0x418db0 ADD	W8, W8, #2

0x418db4 SUBS	W8, W8, W23

0x418db8 CSINV	W8, W8, WZR, #10

0x418dbc CMP	W9, #1

0x418dc0 B.NE	4196dc

0x418dc4 LDR	W28, [SP, #36]

0x418dc8 STP	W8, WZR, [X29, #460]

0x418dcc MOVZ	W8, #1

0x418dd0 ADRP	X0,

0x418dd4 ADD	X0, X0, #3992

0x418dd8 SUB	X3, X29, #44

0x418ddc ORR	W1, WZR, W28

0x418de0 SUB	X4, X29, #48

0x418de4 SUB	X5, X29, #52

0x418de8 SUB	X6, X29, #56

0x418dec MOVZ	W2, #34

0x418df0 MOVZ	W7, #1

0x418df4 STUR	W8, [X29, #456]

0x418df8 STR	WZR, [SP]

0x418dfc BL	410090

0x418e00 LDP	W8, W9, [X29, #460]

0x418e04 LDR	X7, [SP, #112]

0x418e08 SUB	W8, W8, W9

0x418e0c CMN	W8, #1

0x418e10 B.EQ	4198e8

0x418e14 LDP	X11, X13, [SP, #8]

0x418e18 ADD	W9, W9, W23

0x418e1c ORR	W10, WZR, WZR

0x418e20 LDR	W11, [X11]

0x418e24 LDR	W14, [X13]

0x418e28 SUB	W12, W11, #2

0x418e2c ADD	W13, W14, #2

0x418e30 SUB	W15, W14, W11

0x418e34 SUB	W16, W11, #1

0x418e38 ADD	W14, W14, #3

0x418e3c CMP	W13, W12

0x418e40 CSINC	W13, WZR, WZR, #11

0x418e44 ADD	W12, W15, #5

0x418e48 CSINC	W15, WZR, WZR, #10

0x418e4c CMP	W12, #0

0x418e50 CSEL	W13, WZR, W13, #0

0x418e54 CMP	W14, W16

0x418e58 CSINC	W14, W15, WZR, #10

0x418e5c CNTD	X15, ALL

0x418e60 SUBS	W16, W12, W15

0x418e64 CSEL	W16, WZR, W16, #3

0x418e68 WHILELO	P0.D, WZR, W12

0x418e6c B	418e8c

0x418e70 HINT	#0

0x418e74 HINT	#0

0x418e78 HINT	#0

0x418e7c HINT	#0

(75) 0x418e80 CMP	W10, W8

(75) 0x418e84 ADD	W10, W10, #1

(75) 0x418e88 B.EQ	4198e8

(75) 0x418e8c CBZ	W13, 418e80

(75) 0x418e90 LDP	X3, X0, [SP, #120]

(75) 0x418e94 ADD	W1, W9, W10

(75) 0x418e98 LDR	X2, [SP, #136]

(75) 0x418e9c ORR	P1.B, P0/Z, P0.B, P0.B

(75) 0x418ea0 SBFM	X17, X1, #0, #31

(75) 0x418ea4 ADD	W1, W1, #1

(75) 0x418ea8 SBFM	X1, X1, #0, #31

(75) 0x418eac SUB	X18, X17, X3

(75) 0x418eb0 SUB	X1, X1, X3

(75) 0x418eb4 SUB	X3, XZR, X15

(75) 0x418eb8 MUL	X17, X18, X2

(75) 0x418ebc MUL	X18, X18, X0

(75) 0x418ec0 MUL	X1, X1, X2

(75) 0x418ec4 SUB	W2, W11, #1

(75) 0x418ec8 ADD	X0, X19, X18,LSL #3

(75) 0x418ecc ADD	X1, X27, X1,LSL #3

(75) 0x418ed0 TBZ	W14, #0, 418f48

(75) 0x418ed4 ORR	W2, WZR, WZR

(75) 0x418ed8 HINT	#0

(75) 0x418edc HINT	#0

  (77) 0x418ee0 ADD	W3, W11, W2

  (77) 0x418ee4 ADD	W2, W2, #1

  (77) 0x418ee8 SUB	W4, W3, #2

  (77) 0x418eec SUB	W3, W3, #1

  (77) 0x418ef0 CMP	W12, W2

  (77) 0x418ef4 SBFM	X4, X4, #0, #31

  (77) 0x418ef8 SBFM	X3, X3, #0, #31

  (77) 0x418efc SUB	X4, X4, X24

  (77) 0x418f00 SUB	X3, X3, X24

  (77) 0x418f04 LDR	D1, [X0, X3,LSL #3]

  (77) 0x418f08 LDR	D3, [X1, X4,LSL #3]

  (77) 0x418f0c ADD	X5, X4, X17

  (77) 0x418f10 ADD	X3, X4, X18

  (77) 0x418f14 LDR	D0, [X26, X5,LSL #3]

  (77) 0x418f18 LDR	D2, [X19, X3,LSL #3]

  (77) 0x418f1c LDR	D4, [X27, X5,LSL #3]

  (77) 0x418f20 FADD	D3, D1, D3

  (77) 0x418f24 FSUB	D1, D2, S1

  (77) 0x418f28 FADD	D0, D3, D0

  (77) 0x418f2c FADD	D3, D2, D4

  (77) 0x418f30 FSUB	D0, D0, S3

  (77) 0x418f34 STR	D0, [X21, X3,LSL #3]

  (77) 0x418f38 FADD	D0, D1, D0

  (77) 0x418f3c STR	D0, [X7, X3,LSL #3]

  (77) 0x418f40 B.HI	418ee0

(75) 0x418f44 B	418e80

  (76) 0x418f48 SUB	W4, W2, #1

  (76) 0x418f4c SBFM	X6, X2, #0, #31

  (76) 0x418f50 ADD	W3, W3, W15

  (76) 0x418f54 ADD	W2, W2, W15

  (76) 0x418f58 SBFM	X4, X4, #0, #31

  (76) 0x418f5c SUB	X6, X6, X24

  (76) 0x418f60 SUB	X4, X4, X24

  (76) 0x418f64 LD1D	{Z1.D}, P1/Z, [X0, X6,LSL #3]

  (76) 0x418f68 LD1D	{Z3.D}, P1/Z, [X1, X4,LSL #3]

  (76) 0x418f6c ADD	X5, X4, X17

  (76) 0x418f70 ADD	X6, X4, X18

  (76) 0x418f74 LD1D	{Z0.D}, P1/Z, [X26, X5,LSL #3]

  (76) 0x418f78 LD1D	{Z2.D}, P1/Z, [X19, X6,LSL #3]

  (76) 0x418f7c LD1D	{Z4.D}, P1/Z, [X27, X5,LSL #3]

  (76) 0x418f80 FADD	Z3.D, Z1.D, Z3.D

  (76) 0x418f84 FSUB	Z1.D, Z2.D, Z1.D

  (76) 0x418f88 FADD	Z0.D, Z3.D, Z0.D

  (76) 0x418f8c FADD	Z3.D, Z2.D, Z4.D

  (76) 0x418f90 FSUB	Z0.D, Z0.D, Z3.D

  (76) 0x418f94 ST1D	{Z0.D}, P1, [X21, X6,LSL #3]

  (76) 0x418f98 FADD	Z0.D, Z1.D, Z0.D

  (76) 0x418f9c ST1D	{Z0.D}, P1, [X7, X6,LSL #3]

  (76) 0x418fa0 WHILELO	P1.D, W3, W16

  (76) 0x418fa4 B.MI	418f48

(75) 0x418fa8 B	418e80

0x418fac LDR	W1, [SP, #36]

0x418fb0 STP	W8, WZR, [X29, #380]

0x418fb4 MOVZ	W8, #1

0x418fb8 ADRP	X0,

0x418fbc ADD	X0, X0, #3752

0x418fc0 SUB	X3, X29, #124

0x418fc4 SUB	X4, X29, #128

0x418fc8 SUB	X5, X29, #132

0x418fcc SUB	X6, X29, #136

0x418fd0 MOVZ	W2, #34

0x418fd4 STUR	W8, [X29, #376]

0x418fd8 STR	WZR, [SP]

0x418fdc MOVZ	W7, #1

0x418fe0 BL	410090

0x418fe4 LDP	W8, W9, [X29, #380]

0x418fe8 LDR	X30, [SP, #112]

0x418fec SUB	W8, W8, W9

0x418ff0 CMN	W8, #1

0x418ff4 B.EQ	4191e0

0x418ff8 LDP	X11, X13, [SP, #8]

0x418ffc CNTD	X17, ALL

0x419000 ADD	W9, W9, W25

0x419004 ORR	W10, WZR, WZR

0x419008 LDR	W11, [X11]

0x41900c LDR	W16, [X13]

0x419010 SUB	W12, W11, #2

0x419014 ADD	W13, W16, #2

0x419018 SUB	W14, W16, W11

0x41901c ADD	W16, W16, #4

0x419020 CMP	W13, W12

0x419024 ADD	W14, W14, #5

0x419028 CCMP	W14, #0, #4, #10

0x41902c AND	W0, W14, #0xfffffffe

0x419030 CSINC	W15, WZR, WZR, #0

0x419034 SUBS	W18, W14, W17

0x419038 CSEL	W18, WZR, W18, #3

0x41903c WHILELO	P0.D, WZR, W14

0x419040 B	41908c

  (73) 0x419044 ORR	W6, WZR, WZR

  (73) 0x419048 ADD	W6, W6, W12

  (73) 0x41904c SBFM	X6, X6, #0, #31

  (73) 0x419050 SUB	X6, X6, X24

  (73) 0x419054 ADD	X4, X6, X4

  (73) 0x419058 LDR	D1, [X2, X6,LSL #3]

  (73) 0x41905c LDR	D0, [X26, X4,LSL #3]

  (73) 0x419060 FADD	D0, D1, D0

  (73) 0x419064 LDR	D1, [X27, X4,LSL #3]

  (73) 0x419068 FSUB	D0, D0, S1

  (73) 0x41906c STR	D0, [X1, X6,LSL #3]

  (73) 0x419070 LDR	D0, [X3, X6,LSL #3]

  (73) 0x419074 STR	D0, [X5, X6,LSL #3]

  (73) 0x419078 HINT	#0

  (73) 0x41907c HINT	#0

  (73) 0x419080 CMP	W10, W8

  (73) 0x419084 ADD	W10, W10, #1

  (73) 0x419088 B.EQ	4191e0

  (73) 0x41908c CBZ	W15, 419080

  (73) 0x419090 LDR	X3, [SP, #120]

  (73) 0x419094 ADD	W1, W9, W10

  (73) 0x419098 CMP	W13, W12

  (73) 0x41909c SUB	W6, W11, #2

  (73) 0x4190a0 SUB	X7, XZR, X17

  (73) 0x4190a4 ORR	P1.B, P0/Z, P0.B, P0.B

  (73) 0x4190a8 ADD	W2, W1, #1

  (73) 0x4190ac SBFM	X1, X1, #0, #31

  (73) 0x4190b0 SBFM	X2, X2, #0, #31

  (73) 0x4190b4 SUB	X1, X1, X3

  (73) 0x4190b8 SUB	X2, X2, X3

  (73) 0x4190bc LDP	X3, X5, [SP, #128]

  (73) 0x4190c0 MUL	X4, X1, X5

  (73) 0x4190c4 MUL	X2, X2, X5

  (73) 0x4190c8 MUL	X5, X1, X3

  (73) 0x4190cc ADD	X2, X27, X2,LSL #3

  (73) 0x4190d0 ADD	X1, X21, X5,LSL #3

  (73) 0x4190d4 ADD	X3, X26, X4,LSL #3

  (73) 0x4190d8 ADD	X5, X30, X5,LSL #3

  (73) 0x4190dc B.GE	419180

  (73) 0x4190e0 CMP	W16, W11

  (73) 0x4190e4 B.EQ	419044

  (73) 0x4190e8 SUB	W7, W11, #1

  (73) 0x4190ec ORR	W6, WZR, WZR

  (73) 0x4190f0 HINT	#0

  (73) 0x4190f4 HINT	#0

  (73) 0x4190f8 HINT	#0

  (73) 0x4190fc HINT	#0

    (74) 0x419100 SUB	W19, W7, #1

    (74) 0x419104 SBFM	X23, X7, #0, #31

    (74) 0x419108 ADD	W6, W6, #2

    (74) 0x41910c ADD	W7, W7, #2

    (74) 0x419110 SBFM	X19, X19, #0, #31

    (74) 0x419114 SUB	X23, X23, X24

    (74) 0x419118 CMP	W0, W6

    (74) 0x41911c SUB	X19, X19, X24

    (74) 0x419120 ADD	X25, X23, X4

    (74) 0x419124 LDR	D0, [X2, X23,LSL #3]

    (74) 0x419128 LDR	D2, [X3, X19,LSL #3]

    (74) 0x41912c ADD	X30, X19, X4

    (74) 0x419130 LDR	D1, [X2, X19,LSL #3]

    (74) 0x419134 STR	D2, [X5, X19,LSL #3]

    (74) 0x419138 LDR	D2, [X26, X25,LSL #3]

    (74) 0x41913c FADD	D0, D0, D2

    (74) 0x419140 LDR	D2, [X26, X30,LSL #3]

    (74) 0x419144 FADD	D1, D1, D2

    (74) 0x419148 LDR	D2, [X27, X25,LSL #3]

    (74) 0x41914c FSUB	D0, D0, S2

    (74) 0x419150 LDR	D2, [X27, X30,LSL #3]

    (74) 0x419154 FSUB	D1, D1, S2

    (74) 0x419158 STR	D1, [X1, X19,LSL #3]

    (74) 0x41915c STR	D0, [X1, X23,LSL #3]

    (74) 0x419160 LDR	D0, [X3, X23,LSL #3]

    (74) 0x419164 STR	D0, [X5, X23,LSL #3]

    (74) 0x419168 B.NE	419100

  (73) 0x41916c LDR	X30, [SP, #112]

  (73) 0x419170 TBNZ	W14, #0, 419048

  (73) 0x419174 B	419080

0x419178 HINT	#0

0x41917c HINT	#0

(72) 0x419180 SBFM	X19, X6, #0, #31

(72) 0x419184 ADD	W7, W7, W17

(72) 0x419188 ADD	W6, W6, W17

(72) 0x41918c SUB	X19, X19, X24

(72) 0x419190 ADD	X23, X19, X4

(72) 0x419194 LD1D	{Z1.D}, P1/Z, [X2, X19,LSL #3]

(72) 0x419198 LD1D	{Z0.D}, P1/Z, [X26, X23,LSL #3]

(72) 0x41919c FADD	Z0.D, Z1.D, Z0.D

(72) 0x4191a0 LD1D	{Z1.D}, P1/Z, [X27, X23,LSL #3]

(72) 0x4191a4 FSUB	Z0.D, Z0.D, Z1.D

(72) 0x4191a8 ST1D	{Z0.D}, P1, [X1, X19,LSL #3]

(72) 0x4191ac LD1D	{Z0.D}, P1/Z, [X3, X19,LSL #3]

(72) 0x4191b0 ST1D	{Z0.D}, P1, [X5, X19,LSL #3]

(72) 0x4191b4 WHILELO	P1.D, W7, W18

(72) 0x4191b8 B.MI	419180

(72) 0x4191bc B	419080

0x4191c0 LDR	W23, [SP, #36]

0x4191c4 ADRP	X0,

0x4191c8 ADD	X0, X0, #3800

0x4191cc ORR	W1, WZR, W23

0x4191d0 BL	410380

0x4191d4 ADRP	X0,

0x4191d8 ADD	X0, X0, #3824

0x4191dc B	4191fc

0x4191e0 LDR	W23, [SP, #36]

0x4191e4 ADRP	X0,

0x4191e8 ADD	X0, X0, #3752

0x4191ec ORR	W1, WZR, W23

0x4191f0 BL	410380

0x4191f4 ADRP	X0,

0x4191f8 ADD	X0, X0, #3776

0x4191fc ORR	W1, WZR, W23

0x419200 BL	410050

0x419204 LDR	X8, [SP, #24]

0x419208 ADRP	X0,

0x41920c ADD	X0, X0, #3848

0x419210 SUB	X3, X29, #92

0x419214 SUB	X4, X29, #96

0x419218 ORR	W1, WZR, W23

0x41921c LDR	W19, [X8]

0x419220 LDR	X8, [SP, #144]

0x419224 SUB	X5, X29, #100

0x419228 SUB	X6, X29, #104

0x41922c MOVZ	W2, #34

0x419230 MOVZ	W7, #1

0x419234 LDR	W8, [X8]

0x419238 STR	WZR, [SP]

0x41923c ADD	W8, W8, #2

0x419240 SUBS	W8, W8, W19

0x419244 CSINV	W8, W8, WZR, #10

0x419248 STP	W8, WZR, [X29, #412]

0x41924c MOVZ	W8, #1

0x419250 STUR	W8, [X29, #408]

0x419254 BL	410090

0x419258 LDP	W9, W8, [X29, #412]

0x41925c LDR	X14, [SP, #120]

0x419260 SUB	W9, W9, W8

0x419264 CMN	W9, #1

0x419268 STR	W9, [SP, #92]

0x41926c B.EQ	41951c

0x419270 LDR	X9, [SP, #8]

0x419274 ADD	W3, W8, W19

0x419278 LDR	X8, [SP, #16]

0x41927c SUB	X10, XZR, X14

0x419280 FMOV	D0, #2.0000000

0x419284 FMOV	D1, #1.0000000

0x419288 STR	WZR, [SP, #152]

0x41928c STR	X10, [SP, #64]

0x419290 LDR	X10, [SP, #128]

0x419294 STR	W3, [SP, #76]

0x419298 UBFM	X10, X10, #61, #60

0x41929c LDRSW	X11, [X9]

0x4192a0 LDRSW	X8, [X8]

0x4192a4 STR	X10, [SP, #56]

0x4192a8 SUB	W10, W3, #1

0x4192ac STR	W10, [SP, #112]

0x4192b0 SUB	X8, X8, X11

0x4192b4 UBFM	X9, X11, #61, #60

0x4192b8 STR	X11, [SP, #80]

0x4192bc STR	X8, [SP, #96]

0x4192c0 SUB	X8, X11, X24

0x4192c4 STR	X8, [SP, #48]

0x4192c8 SUB	X8, X9, X24,LSL #3

0x4192cc LDR	X9, [SP, #104]

0x4192d0 ADD	X18, X21, X8

0x4192d4 ADD	X1, X22, X8

0x4192d8 ADD	X2, X20, X8

0x4192dc ADD	X9, X9, X8

0x4192e0 ORR	X8, XZR, #0x55

0x4192e4 STR	X9, [SP, #40]

0x4192e8 LDR	X9, [SP, #136]

0x4192ec MOVK	X8, #16325

0x4192f0 FMOV	D2, X8

0x4192f4 UBFM	X0, X9, #61, #60

0x4192f8 B	419328

0x4192fc HINT	#0

  (70) 0x419300 LDR	W8, [SP, #92]

  (70) 0x419304 LDR	W9, [SP, #152]

  (70) 0x419308 ADD	W3, W3, #1

  (70) 0x41930c CMP	W9, W8

  (70) 0x419310 ADD	W8, W9, #1

  (70) 0x419314 LDR	W9, [SP, #112]

  (70) 0x419318 STR	W8, [SP, #152]

  (70) 0x41931c ADD	W9, W9, #1

  (70) 0x419320 STR	W9, [SP, #112]

  (70) 0x419324 B.EQ	41951c

  (70) 0x419328 LDR	X8, [SP, #96]

  (70) 0x41932c TBNZ	X8, #63, 419300

(71) 0x419330 LDR	X9, [SP, #64]

(71) 0x419334 LDR	W8, [SP, #112]

(71) 0x419338 LDR	X10, [SP, #136]

(71) 0x41933c ORR	X4, XZR, XZR

(71) 0x419340 ADD	X8, X9, W8,SXTW

(71) 0x419344 LDP	X13, X11, [SP, #40]

(71) 0x419348 MADD	X5, X10, X8, X11

(71) 0x41934c ADD	X8, X9, W3,SXTW

(71) 0x419350 LDR	X9, [SP, #56]

(71) 0x419354 MADD	X6, X9, X8, X13

(71) 0x419358 MADD	X8, X10, X8, X11

(71) 0x41935c LDR	W9, [SP, #152]

(71) 0x419360 LDR	X11, [SP, #128]

(71) 0x419364 ADD	X7, X28, X8,LSL #3

(71) 0x419368 ADD	X25, X27, X8,LSL #3

(71) 0x41936c LDR	W8, [SP, #76]

(71) 0x419370 ADD	W8, W8, W9

(71) 0x419374 SBFM	X9, X8, #0, #31

(71) 0x419378 ADD	W30, W8, #1

(71) 0x41937c SUB	W19, W8, #2

(71) 0x419380 SUB	X9, X9, X14

(71) 0x419384 MUL	X26, X9, X10

(71) 0x419388 SUB	W10, W8, #1

(71) 0x41938c LDUR	X8, [X29, #368]

(71) 0x419390 MUL	X23, X9, X11

(71) 0x419394 LDR	D3, [X8, X9,LSL #3]

(71) 0x419398 SBFM	X8, X10, #0, #31

(71) 0x41939c LDR	X9, [SP, #80]

(71) 0x4193a0 SUB	X16, X8, X14

(71) 0x4193a4 LDR	X8, [SP, #96]

(71) 0x4193a8 MUL	X13, X16, X11

(71) 0x4193ac ADD	X17, X8, #2

(71) 0x4193b0 B	4193dc

0x4193b4 HINT	#0

0x4193b8 HINT	#0

0x4193bc HINT	#0

(71) 0x4193c0 FMUL	D4, D17, D4

(71) 0x4193c4 SUB	X17, X17, #1

(71) 0x4193c8 ADD	X9, X9, #1

(71) 0x4193cc CMP	X17, #1

(71) 0x4193d0 STR	D4, [X6, X4,LSL #3]

(71) 0x4193d4 ADD	X4, X4, #1

(71) 0x4193d8 B.LE	419300

(71) 0x4193dc LDR	D4, [X25, X4,LSL #3]

(71) 0x4193e0 SUB	X8, X9, X24

(71) 0x4193e4 ADD	X10, X8, X26

(71) 0x4193e8 FCMP	D4, #0

(71) 0x4193ec B.LE	419404

(71) 0x4193f0 ADD	X8, X5, X4

(71) 0x4193f4 ORR	X15, XZR, X16

(71) 0x4193f8 ORR	X12, XZR, X13

(71) 0x4193fc ORR	W11, WZR, W19

(71) 0x419400 B	41942c

(71) 0x419404 LDR	X8, [SP, #144]

(71) 0x419408 ORR	X12, XZR, X23

(71) 0x41940c LDR	W8, [X8]

(71) 0x419410 ADD	W8, W8, #2

(71) 0x419414 CMP	W30, W8

(71) 0x419418 CSEL	W11, W30, W8, #11

(71) 0x41941c SBFM	X8, X11, #0, #31

(71) 0x419420 SUB	X15, X8, X14

(71) 0x419424 ORR	X8, XZR, X10

(71) 0x419428 ADD	X10, X5, X4

(71) 0x41942c ADD	X12, X18, X12,LSL #3

(71) 0x419430 FABS	D5, D4

(71) 0x419434 SBFM	X11, X11, #0, #31

(71) 0x419438 LDR	D16, [X20, X8,LSL #3]

(71) 0x41943c LDR	D19, [X20, X10,LSL #3]

(71) 0x419440 LDR	D7, [X12, X4,LSL #3]

(71) 0x419444 LDUR	X12, [X29, #368]

(71) 0x419448 FSUB	D19, D19, S16

(71) 0x41944c FDIV	D17, D5, D7

(71) 0x419450 LDR	D5, [X12, X15,LSL #3]

(71) 0x419454 SUB	X15, X11, X14

(71) 0x419458 MADD	X11, X0, X15, X2

(71) 0x41945c LDR	D18, [X11, X4,LSL #3]

(71) 0x419460 FSUB	D18, D16, S18

(71) 0x419464 FMUL	D20, D19, D18

(71) 0x419468 FCMP	D20, #0

(71) 0x41946c FMOV	D20, D16

(71) 0x419470 FMADD	D6, D17, D3, D3

(71) 0x419474 FDIV	D5, D6, D5

(71) 0x419478 FSUB	D6, D0, S17

(71) 0x41947c B.LE	4194b0

(71) 0x419480 FSUB	D17, D1, S17

(71) 0x419484 FCMP	D19, #0

(71) 0x419488 FABS	D18, D18

(71) 0x41948c FABS	D19, D19

(71) 0x419490 FNEG	D20, D17

(71) 0x419494 FCSEL	D17, D17, D20, #12

(71) 0x419498 FMUL	D20, D18, D5

(71) 0x41949c FMINNM	D18, D18, D19

(71) 0x4194a0 FMADD	D20, D19, D6, D20

(71) 0x4194a4 FMUL	D20, D20, D2

(71) 0x4194a8 FMINNM	D18, D18, D20

(71) 0x4194ac FMADD	D20, D18, D17, D16

(71) 0x4194b0 LDR	D17, [X22, X8,LSL #3]

(71) 0x4194b4 MADD	X8, X0, X15, X1

(71) 0x4194b8 LDR	D19, [X22, X10,LSL #3]

(71) 0x4194bc FMUL	D4, D20, D4

(71) 0x4194c0 LDR	D18, [X8, X4,LSL #3]

(71) 0x4194c4 STR	D4, [X7, X4,LSL #3]

(71) 0x4194c8 FSUB	D19, D19, S17

(71) 0x4194cc FSUB	D18, D17, S18

(71) 0x4194d0 FMUL	D20, D19, D18

(71) 0x4194d4 FCMP	D20, #0

(71) 0x4194d8 B.LE	4193c0

(71) 0x4194dc FMUL	D7, D16, D7

(71) 0x4194e0 FABS	D20, D4

(71) 0x4194e4 FCMP	D19, #0

(71) 0x4194e8 FDIV	D7, D20, D7

(71) 0x4194ec FSUB	D7, D1, S7

(71) 0x4194f0 FNEG	D16, D7

(71) 0x4194f4 FCSEL	D7, D7, D16, #12

(71) 0x4194f8 FABS	D16, D18

(71) 0x4194fc FABS	D18, D19

(71) 0x419500 FMUL	D5, D16, D5

(71) 0x419504 FMADD	D5, D18, D6, D5

(71) 0x419508 FMINNM	D6, D16, D18

(71) 0x41950c FMUL	D5, D5, D2

(71) 0x419510 FMINNM	D5, D6, D5

(71) 0x419514 FMADD	D17, D5, D7, D17

(71) 0x419518 B	4193c0

0x41951c LDR	W23, [SP, #36]

0x419520 ADRP	X0,

0x419524 ADD	X0, X0, #3848

0x419528 ORR	W1, WZR, W23

0x41952c BL	410380

0x419530 ADRP	X0,

0x419534 ADD	X0, X0, #3872

0x419538 ORR	W1, WZR, W23

0x41953c BL	410050

0x419540 LDR	X8, [SP, #24]

0x419544 ADRP	X0,

0x419548 ADD	X0, X0, #3896

0x41954c SUB	X3, X29, #76

0x419550 SUB	X4, X29, #80

0x419554 ORR	W1, WZR, W23

0x419558 LDR	W19, [X8]

0x41955c LDR	X8, [SP, #144]

0x419560 SUB	X5, X29, #84

0x419564 SUB	X6, X29, #88

0x419568 MOVZ	W2, #34

0x41956c MOVZ	W7, #1

0x419570 LDR	W8, [X8]

0x419574 STR	WZR, [SP]

0x419578 SUBS	W8, W8, W19

0x41957c CSINV	W8, W8, WZR, #10

0x419580 STP	W8, WZR, [X29, #428]

0x419584 MOVZ	W8, #1

0x419588 STUR	W8, [X29, #424]

0x41958c BL	410090

0x419590 LDP	W8, W10, [X29, #428]

0x419594 LDR	X7, [SP, #104]

0x419598 SUB	W8, W8, W10

0x41959c CMN	W8, #1

0x4195a0 B.EQ	4196b8

0x4195a4 LDP	X11, X12, [SP, #8]

0x4195a8 PTRUE	P1.D, ALL

0x4195ac ADD	W10, W10, W19

0x4195b0 ORR	W9, WZR, WZR

0x4195b4 LDR	W11, [X11]

0x4195b8 LDR	W12, [X12]

0x4195bc SUBS	W12, W12, W11

0x4195c0 CSINC	W13, WZR, WZR, #11

0x4195c4 ADDS	W15, W12, #1

0x4195c8 CSEL	W12, WZR, W13, #0

0x4195cc CNTD	X13, ALL

0x4195d0 SUBS	W14, W15, W13

0x4195d4 CSEL	W14, WZR, W14, #3

0x4195d8 WHILELO	P0.D, WZR, W15

0x4195dc B	4195ec

(68) 0x4195e0 CMP	W9, W8

(68) 0x4195e4 ADD	W9, W9, #1

(68) 0x4195e8 B.EQ	4196b8

(68) 0x4195ec CBZ	W12, 4195e0

(68) 0x4195f0 LDP	X18, X1, [SP, #120]

(68) 0x4195f4 ADD	W17, W10, W9

(68) 0x4195f8 LDR	X0, [SP, #136]

(68) 0x4195fc SUB	X2, XZR, X13

(68) 0x419600 ORR	P2.B, P0/Z, P0.B, P0.B

(68) 0x419604 SBFM	X15, X17, #0, #31

(68) 0x419608 ADD	W17, W17, #1

(68) 0x41960c SBFM	X17, X17, #0, #31

(68) 0x419610 SUB	X16, X15, X18

(68) 0x419614 SUB	X18, X17, X18

(68) 0x419618 MUL	X15, X16, X0

(68) 0x41961c MUL	X17, X18, X0

(68) 0x419620 MUL	X18, X18, X1

(68) 0x419624 MUL	X16, X16, X1

(68) 0x419628 ORR	W1, WZR, W11

(68) 0x41962c ADD	X18, X7, X18,LSL #3

(68) 0x419630 ADD	X0, X22, X15,LSL #3

(68) 0x419634 HINT	#0

(68) 0x419638 HINT	#0

(68) 0x41963c HINT	#0

  (69) 0x419640 SBFM	X3, X1, #0, #31

  (69) 0x419644 ADD	W2, W2, W13

  (69) 0x419648 ADD	W1, W1, W13

  (69) 0x41964c SUB	X3, X3, X24

  (69) 0x419650 ADD	X4, X3, X15

  (69) 0x419654 ADD	X5, X3, X16

  (69) 0x419658 ADD	X6, X3, X17

  (69) 0x41965c LD1D	{Z0.D}, P2/Z, [X20, X4,LSL #3]

  (69) 0x419660 LD1D	{Z1.D}, P2/Z, [X21, X5,LSL #3]

  (69) 0x419664 LD1D	{Z2.D}, P2/Z, [X28, X4,LSL #3]

  (69) 0x419668 LD1D	{Z3.D}, P2/Z, [X28, X6,LSL #3]

  (69) 0x41966c LD1D	{Z4.D}, P2/Z, [X7, X5,LSL #3]

  (69) 0x419670 FMUL	Z0.D, Z1.D, Z0.D

  (69) 0x419674 FADD	Z2.D, Z0.D, Z2.D

  (69) 0x419678 FSUB	Z2.D, Z2.D, Z3.D

  (69) 0x41967c LD1D	{Z3.D}, P2/Z, [X22, X4,LSL #3]

  (69) 0x419680 FMAD	Z0.D, P1/M, Z3.D, Z4.D

  (69) 0x419684 LD1D	{Z3.D}, P2/Z, [X18, X3,LSL #3]

  (69) 0x419688 FSUB	Z0.D, Z0.D, Z3.D

  (69) 0x41968c LD1D	{Z3.D}, P2/Z, [X27, X4,LSL #3]

  (69) 0x419690 FDIV	Z0.D, P1/M, Z0.D, Z2.D

  (69) 0x419694 FADD	Z1.D, Z3.D, Z1.D

  (69) 0x419698 LD1D	{Z3.D}, P2/Z, [X27, X6,LSL #3]

  (69) 0x41969c FSUB	Z1.D, Z1.D, Z3.D

  (69) 0x4196a0 FDIVR	Z1.D, P1/M, Z1.D, Z2.D

  (69) 0x4196a4 ST1D	{Z0.D}, P2, [X0, X3,LSL #3]

  (69) 0x4196a8 ST1D	{Z1.D}, P2, [X20, X4,LSL #3]

  (69) 0x4196ac WHILELO	P2.D, W2, W14

  (69) 0x4196b0 B.MI	419640

(68) 0x4196b4 B	4195e0

0x4196b8 LDR	W19, [SP, #36]

0x4196bc ADRP	X0,

0x4196c0 ADD	X0, X0, #3896

0x4196c4 ORR	W1, WZR, W19

0x4196c8 BL	410380

0x4196cc ADRP	X0,

0x4196d0 ADD	X0, X0, #3920

0x4196d4 ORR	W1, WZR, W19

0x4196d8 B	419dfc

0x4196dc LDR	W28, [SP, #36]

0x4196e0 STP	W8, WZR, [X29, #444]

0x4196e4 MOVZ	W8, #1

0x4196e8 ADRP	X0,

0x4196ec ADD	X0, X0, #3944

0x4196f0 SUB	X3, X29, #60

0x4196f4 ORR	W1, WZR, W28

0x4196f8 SUB	X4, X29, #64

0x4196fc SUB	X5, X29, #68

0x419700 SUB	X6, X29, #72

0x419704 MOVZ	W2, #34

0x419708 MOVZ	W7, #1

0x41970c STUR	W8, [X29, #440]

0x419710 STR	WZR, [SP]

0x419714 BL	410090

0x419718 LDP	W8, W9, [X29, #444]

0x41971c LDR	X30, [SP, #112]

0x419720 SUB	W8, W8, W9

0x419724 CMN	W8, #1

0x419728 B.EQ	419904

0x41972c LDP	X11, X13, [SP, #8]

0x419730 ADD	W9, W9, W23

0x419734 ORR	W10, WZR, WZR

0x419738 LDR	W11, [X11]

0x41973c LDR	W16, [X13]

0x419740 SUB	W12, W11, #2

0x419744 ADD	W13, W16, #2

0x419748 SUB	W14, W16, W11

0x41974c SUB	W18, W11, #1

0x419750 CMP	W13, W12

0x419754 CSINC	W15, WZR, WZR, #11

0x419758 ADD	W13, W14, #5

0x41975c CSINC	W17, WZR, WZR, #10

0x419760 CMP	W13, #0

0x419764 CSEL	W14, WZR, W15, #0

0x419768 ADD	W15, W16, #4

0x41976c ADD	W16, W16, #3

0x419770 AND	W0, W13, #0xfffffffe

0x419774 CMP	W16, W18

0x419778 CSINC	W16, W17, WZR, #10

0x41977c CNTD	X17, ALL

0x419780 SUBS	W18, W13, W17

0x419784 CSEL	W18, WZR, W18, #3

0x419788 WHILELO	P0.D, WZR, W13

0x41978c B	4197d8

(78) 0x419790 ORR	W5, WZR, WZR

(78) 0x419794 ADD	W5, W5, W12

(78) 0x419798 SBFM	X6, X5, #0, #31

(78) 0x41979c SUB	X6, X6, X24

(78) 0x4197a0 LDR	D0, [X4, X6,LSL #3]

(78) 0x4197a4 ADD	W4, W5, #1

(78) 0x4197a8 ADD	X2, X6, X2

(78) 0x4197ac SBFM	X4, X4, #0, #31

(78) 0x4197b0 LDR	D2, [X19, X2,LSL #3]

(78) 0x4197b4 SUB	X4, X4, X24

(78) 0x4197b8 LDR	D1, [X3, X4,LSL #3]

(78) 0x4197bc STR	D0, [X1, X6,LSL #3]

(78) 0x4197c0 FADD	D1, D1, D0

(78) 0x4197c4 FSUB	D1, D1, S2

(78) 0x4197c8 STR	D1, [X21, X2,LSL #3]

(78) 0x4197cc CMP	W10, W8

(78) 0x4197d0 ADD	W10, W10, #1

(78) 0x4197d4 B.EQ	419904

(78) 0x4197d8 CBZ	W14, 4197cc

(78) 0x4197dc LDR	X2, [SP, #120]

(78) 0x4197e0 ADD	W1, W9, W10

(78) 0x4197e4 SUB	W5, W11, #1

(78) 0x4197e8 SUB	X6, XZR, X17

(78) 0x4197ec ORR	P1.B, P0/Z, P0.B, P0.B

(78) 0x4197f0 SBFM	X1, X1, #0, #31

(78) 0x4197f4 SUB	X1, X1, X2

(78) 0x4197f8 LDR	X2, [SP, #136]

(78) 0x4197fc MUL	X2, X1, X2

(78) 0x419800 ADD	X4, X26, X2,LSL #3

(78) 0x419804 LDR	X2, [SP, #128]

(78) 0x419808 MUL	X2, X1, X2

(78) 0x41980c ADD	X3, X19, X2,LSL #3

(78) 0x419810 ADD	X1, X30, X2,LSL #3

(78) 0x419814 TBZ	W16, #0, 4198a0

(78) 0x419818 CMP	W15, W11

(78) 0x41981c B.EQ	419790

(78) 0x419820 ORR	W5, WZR, WZR

(78) 0x419824 ORR	W6, WZR, W11

  (80) 0x419828 SUB	W7, W6, #2

  (80) 0x41982c SUB	W23, W6, #1

  (80) 0x419830 SBFM	X27, X6, #0, #31

  (80) 0x419834 ADD	W5, W5, #2

  (80) 0x419838 ADD	W6, W6, #2

  (80) 0x41983c SBFM	X7, X7, #0, #31

  (80) 0x419840 SBFM	X23, X23, #0, #31

  (80) 0x419844 SUB	X27, X27, X24

  (80) 0x419848 LDR	D0, [X3, X27,LSL #3]

  (80) 0x41984c SUB	X7, X7, X24

  (80) 0x419850 SUB	X23, X23, X24

  (80) 0x419854 CMP	W0, W5

  (80) 0x419858 LDR	D1, [X4, X7,LSL #3]

  (80) 0x41985c LDR	D2, [X3, X23,LSL #3]

  (80) 0x419860 ADD	X27, X7, X2

  (80) 0x419864 FADD	D2, D2, D1

  (80) 0x419868 STR	D1, [X1, X7,LSL #3]

  (80) 0x41986c LDR	D1, [X19, X27,LSL #3]

  (80) 0x419870 ADD	X7, X23, X2

  (80) 0x419874 FSUB	D1, D2, S1

  (80) 0x419878 LDR	D2, [X4, X23,LSL #3]

  (80) 0x41987c STR	D1, [X21, X27,LSL #3]

  (80) 0x419880 LDR	D1, [X19, X7,LSL #3]

  (80) 0x419884 FADD	D0, D0, D2

  (80) 0x419888 STR	D2, [X1, X23,LSL #3]

  (80) 0x41988c FSUB	D0, D0, S1

  (80) 0x419890 STR	D0, [X21, X7,LSL #3]

  (80) 0x419894 B.NE	419828

(78) 0x419898 TBNZ	W13, #0, 419794

(78) 0x41989c B	4197cc

  (79) 0x4198a0 SUB	W7, W5, #1

  (79) 0x4198a4 SBFM	X23, X5, #0, #31

  (79) 0x4198a8 ADD	W6, W6, W17

  (79) 0x4198ac ADD	W5, W5, W17

  (79) 0x4198b0 SBFM	X7, X7, #0, #31

  (79) 0x4198b4 SUB	X23, X23, X24

  (79) 0x4198b8 SUB	X7, X7, X24

  (79) 0x4198bc LD1D	{Z1.D}, P1/Z, [X3, X23,LSL #3]

  (79) 0x4198c0 LD1D	{Z0.D}, P1/Z, [X4, X7,LSL #3]

  (79) 0x4198c4 ADD	X23, X7, X2

  (79) 0x4198c8 LD1D	{Z2.D}, P1/Z, [X19, X23,LSL #3]

  (79) 0x4198cc FADD	Z1.D, Z1.D, Z0.D

  (79) 0x4198d0 ST1D	{Z0.D}, P1, [X1, X7,LSL #3]

  (79) 0x4198d4 FSUB	Z1.D, Z1.D, Z2.D

  (79) 0x4198d8 ST1D	{Z1.D}, P1, [X21, X23,LSL #3]

  (79) 0x4198dc WHILELO	P1.D, W6, W18

  (79) 0x4198e0 B.MI	4198a0

(78) 0x4198e4 B	4197cc

0x4198e8 ADRP	X0,

0x4198ec ADD	X0, X0, #3992

0x4198f0 ORR	W1, WZR, W28

0x4198f4 BL	410380

0x4198f8 ADRP	X0,

0x4198fc ADD	X0, X0, #4016

0x419900 B	41991c

0x419904 ADRP	X0,

0x419908 ADD	X0, X0, #3944

0x41990c ORR	W1, WZR, W28

0x419910 BL	410380

0x419914 ADRP	X0,

0x419918 ADD	X0, X0, #3968

0x41991c ORR	W1, WZR, W28

0x419920 BL	410050

0x419924 LDR	X8, [SP, #24]

0x419928 ADRP	X0,

0x41992c ADD	X0, X0, #4040

0x419930 SUB	X3, X29, #28

0x419934 SUB	X4, X29, #32

0x419938 ORR	W1, WZR, W28

0x41993c LDR	W26, [X8]

0x419940 LDR	X8, [SP, #144]

0x419944 SUB	X5, X29, #36

0x419948 SUB	X6, X29, #40

0x41994c MOVZ	W2, #34

0x419950 MOVZ	W7, #1

0x419954 LDR	W8, [X8]

0x419958 STR	WZR, [SP]

0x41995c SUBS	W8, W8, W26

0x419960 CSINV	W8, W8, WZR, #10

0x419964 STP	W8, WZR, [X29, #476]

0x419968 MOVZ	W8, #1

0x41996c STUR	W8, [X29, #472]

0x419970 BL	410090

0x419974 LDP	W8, W12, [X29, #476]

0x419978 LDR	X13, [SP, #152]

0x41997c SUB	W8, W8, W12

0x419980 CMN	W8, #1

0x419984 B.EQ	419bbc

0x419988 LDR	X10, [SP, #16]

0x41998c SUB	X14, X13, X24,LSL #3

0x419990 ADD	W2, W12, W26

0x419994 FMOV	D0, #2.0000000

0x419998 FMOV	D1, #1.0000000

0x41999c ORR	W9, WZR, WZR

0x4199a0 STUR	W2, [X29, #368]

0x4199a4 LDR	W11, [X10]

0x4199a8 LDR	X10, [SP, #8]

0x4199ac LDR	W10, [X10]

0x4199b0 ADD	W11, W11, #2

0x4199b4 SBFM	X16, X11, #0, #31

0x4199b8 SBFM	X13, X10, #0, #31

0x4199bc ADD	X14, X14, W10,SXTW #3

0x4199c0 SUB	W0, W10, #1

0x4199c4 SUB	W1, W10, #2

0x4199c8 SUB	X17, X16, X13

0x4199cc LDR	X16, [SP, #120]

0x4199d0 SUB	X15, X13, #1

0x4199d4 SUB	X12, XZR, X16

0x4199d8 ORR	X16, XZR, #0x55

0x4199dc MOVK	X16, #16325

0x4199e0 FMOV	D2, X16

0x4199e4 STR	X12, [SP, #112]

0x4199e8 B	4199fc

    (65) 0x4199ec CMP	W9, W8

    (65) 0x4199f0 ADD	W9, W9, #1

    (65) 0x4199f4 ADD	W2, W2, #1

    (65) 0x4199f8 B.EQ	419bbc

    (65) 0x4199fc TBNZ	X17, #63, 4199ec

  (67) 0x419a00 LDP	X18, X12, [SP, #104]

  (67) 0x419a04 LDR	X7, [SP, #128]

  (67) 0x419a08 ADD	X27, X17, #2

  (67) 0x419a0c ORR	X3, XZR, XZR

  (67) 0x419a10 ORR	X28, XZR, X13

  (67) 0x419a14 ADD	X16, X12, W2,SXTW

  (67) 0x419a18 SUB	X12, X13, X24

  (67) 0x419a1c MADD	X16, X7, X16, X12

  (67) 0x419a20 LDUR	W12, [X29, #368]

  (67) 0x419a24 ADD	X4, X18, X16,LSL #3

  (67) 0x419a28 LDR	X18, [SP, #120]

  (67) 0x419a2c ADD	X5, X25, X16,LSL #3

  (67) 0x419a30 ADD	X6, X19, X16,LSL #3

  (67) 0x419a34 ADD	W16, W12, W9

  (67) 0x419a38 SBFM	X16, X16, #0, #31

  (67) 0x419a3c SUB	X16, X16, X18

  (67) 0x419a40 MUL	X18, X16, X7

  (67) 0x419a44 ADD	X7, X21, X18,LSL #3

  (67) 0x419a48 LDR	X18, [SP, #136]

  (67) 0x419a4c MUL	X26, X16, X18

  (67) 0x419a50 B	419a7c

0x419a54 HINT	#0

0x419a58 HINT	#0

0x419a5c HINT	#0

  (67) 0x419a60 FMUL	D3, D16, D3

  (67) 0x419a64 SUB	X27, X27, #1

  (67) 0x419a68 ADD	X28, X28, #1

  (67) 0x419a6c CMP	X27, #1

  (67) 0x419a70 STR	D3, [X4, X3,LSL #3]

  (67) 0x419a74 ADD	X3, X3, #1

  (67) 0x419a78 B.LE	4199ec

  (67) 0x419a7c LDR	D3, [X6, X3,LSL #3]

  (67) 0x419a80 FCMP	D3, #0

  (67) 0x419a84 B.LE	419aa0

  (67) 0x419a88 ADD	W30, W1, W3

  (67) 0x419a8c SUB	W18, W28, #1

  (67) 0x419a90 ADD	W23, W0, W3

  (67) 0x419a94 ORR	X16, XZR, X28

  (67) 0x419a98 B	419abc

0x419a9c HINT	#0

(66) 0x419aa0 ADD	W16, W10, W3

(66) 0x419aa4 ADD	X18, X10, X3

(66) 0x419aa8 ADD	W23, W16, #1

(66) 0x419aac CMP	W23, W11

(66) 0x419ab0 CSINC	W30, W11, W16, #10

(66) 0x419ab4 ADD	X16, X15, X3

(66) 0x419ab8 ORR	W23, WZR, W30

  (67) 0x419abc SBFM	X18, X18, #0, #31

  (67) 0x419ac0 FABS	D5, D3

  (67) 0x419ac4 LDR	X12, [SP, #152]

  (67) 0x419ac8 SBFM	X23, X23, #0, #31

  (67) 0x419acc SUB	X18, X18, X24

  (67) 0x419ad0 SUB	X23, X23, X24

  (67) 0x419ad4 LDR	D4, [X7, X18,LSL #3]

  (67) 0x419ad8 LDR	D6, [X12, X23,LSL #3]

  (67) 0x419adc ADD	X23, X18, X26

  (67) 0x419ae0 SUB	X18, X26, X24

  (67) 0x419ae4 ADD	X30, X18, W30,SXTW

  (67) 0x419ae8 ADD	X16, X18, W16,SXTW

  (67) 0x419aec LDR	D7, [X20, X23,LSL #3]

  (67) 0x419af0 LDR	D17, [X20, X30,LSL #3]

  (67) 0x419af4 LDR	D18, [X20, X16,LSL #3]

  (67) 0x419af8 FDIV	D16, D5, D4

  (67) 0x419afc LDR	D5, [X14, X3,LSL #3]

  (67) 0x419b00 FSUB	D17, D7, S17

  (67) 0x419b04 FSUB	D18, D18, S7

  (67) 0x419b08 FMUL	D19, D18, D17

  (67) 0x419b0c FCMP	D19, #0

  (67) 0x419b10 FMOV	D19, D7

  (67) 0x419b14 FMADD	D5, D16, D5, D5

  (67) 0x419b18 FDIV	D5, D5, D6

  (67) 0x419b1c FSUB	D6, D0, S16

  (67) 0x419b20 B.LE	419b54

  (67) 0x419b24 FSUB	D16, D1, S16

  (67) 0x419b28 FCMP	D18, #0

  (67) 0x419b2c FABS	D17, D17

  (67) 0x419b30 FABS	D18, D18

  (67) 0x419b34 FNEG	D19, D16

  (67) 0x419b38 FCSEL	D16, D16, D19, #12

  (67) 0x419b3c FMUL	D19, D17, D5

  (67) 0x419b40 FMINNM	D17, D17, D18

  (67) 0x419b44 FMADD	D19, D18, D6, D19

  (67) 0x419b48 FMUL	D19, D19, D2

  (67) 0x419b4c FMINNM	D17, D17, D19

  (67) 0x419b50 FMADD	D19, D17, D16, D7

  (67) 0x419b54 LDR	D16, [X22, X23,LSL #3]

  (67) 0x419b58 LDR	D17, [X22, X30,LSL #3]

  (67) 0x419b5c LDR	D18, [X22, X16,LSL #3]

  (67) 0x419b60 FMUL	D3, D19, D3

  (67) 0x419b64 FSUB	D17, D16, S17

  (67) 0x419b68 FSUB	D18, D18, S16

  (67) 0x419b6c STR	D3, [X5, X3,LSL #3]

  (67) 0x419b70 FMUL	D19, D18, D17

  (67) 0x419b74 FCMP	D19, #0

  (67) 0x419b78 B.LE	419a60

  (67) 0x419b7c FMUL	D4, D7, D4

  (67) 0x419b80 FABS	D19, D3

  (67) 0x419b84 FCMP	D18, #0

  (67) 0x419b88 FDIV	D4, D19, D4

  (67) 0x419b8c FSUB	D4, D1, S4

  (67) 0x419b90 FNEG	D7, D4

  (67) 0x419b94 FCSEL	D4, D4, D7, #12

  (67) 0x419b98 FABS	D7, D17

  (67) 0x419b9c FABS	D17, D18

  (67) 0x419ba0 FMUL	D5, D7, D5

  (67) 0x419ba4 FMADD	D5, D17, D6, D5

  (67) 0x419ba8 FMINNM	D6, D7, D17

  (67) 0x419bac FMUL	D5, D5, D2

  (67) 0x419bb0 FMINNM	D5, D6, D5

  (67) 0x419bb4 FMADD	D16, D5, D4, D16

  (67) 0x419bb8 B	419a60

0x419bbc LDR	W27, [SP, #36]

0x419bc0 ADRP	X0,

0x419bc4 ADD	X0, X0, #4040

0x419bc8 ORR	W1, WZR, W27

0x419bcc BL	410380

0x419bd0 ADRP	X0,

0x419bd4 ADD	X0, X0, #4064

0x419bd8 ORR	W1, WZR, W27

0x419bdc BL	410050

0x419be0 LDR	X8, [SP, #24]

0x419be4 ADRP	X0,

0x419be8 ADD	X0, X0, #4088

0x419bec SUB	X3, X29, #12

0x419bf0 SUB	X4, X29, #16

0x419bf4 ORR	W1, WZR, W27

0x419bf8 LDR	W26, [X8]

0x419bfc LDR	X8, [SP, #144]

0x419c00 SUB	X5, X29, #20

0x419c04 SUB	X6, X29, #24

0x419c08 MOVZ	W2, #34

0x419c0c MOVZ	W7, #1

0x419c10 LDR	W8, [X8]

0x419c14 STR	WZR, [SP]

0x419c18 SUBS	W8, W8, W26

0x419c1c CSINV	W8, W8, WZR, #10

0x419c20 STP	W8, WZR, [X29, #492]

0x419c24 MOVZ	W8, #1

0x419c28 STUR	W8, [X29, #488]

0x419c2c BL	410090

0x419c30 LDP	W8, W10, [X29, #492]

0x419c34 SUB	W8, W8, W10

0x419c38 CMN	W8, #1

0x419c3c B.EQ	419de0

0x419c40 LDP	X11, X12, [SP, #8]

0x419c44 CNTD	X16, ALL

0x419c48 ADD	W10, W10, W26

0x419c4c LDR	X26, [SP, #104]

0x419c50 ORR	W9, WZR, WZR

0x419c54 LDR	W11, [X11]

0x419c58 LDR	W15, [X12]

0x419c5c PTRUE	P1.D, ALL

0x419c60 SUBS	W12, W15, W11

0x419c64 ADD	W14, W11, #1

0x419c68 ADD	W15, W15, #1

0x419c6c CSINC	W13, WZR, WZR, #11

0x419c70 ADDS	W12, W12, #1

0x419c74 CSEL	W13, WZR, W13, #0

0x419c78 SUBS	W17, W12, W16

0x419c7c CSEL	W17, WZR, W17, #3

0x419c80 WHILELO	P0.D, WZR, W12

0x419c84 B	419c94

  (63) 0x419c88 CMP	W9, W8

  (63) 0x419c8c ADD	W9, W9, #1

  (63) 0x419c90 B.EQ	419de0

  (63) 0x419c94 CBZ	W13, 419c88

  (63) 0x419c98 LDP	X0, X1, [SP, #120]

  (63) 0x419c9c ADD	W18, W10, W9

  (63) 0x419ca0 CMP	W15, W14

  (63) 0x419ca4 SUB	X3, XZR, X16

  (63) 0x419ca8 ORR	P2.B, P0/Z, P0.B, P0.B

  (63) 0x419cac ORR	W2, WZR, W11

  (63) 0x419cb0 SBFM	X18, X18, #0, #31

  (63) 0x419cb4 SUB	X0, X18, X0

  (63) 0x419cb8 LDR	X18, [SP, #136]

  (63) 0x419cbc MUL	X18, X0, X18

  (63) 0x419cc0 MUL	X0, X0, X1

  (63) 0x419cc4 ADD	X1, X22, X18,LSL #3

  (63) 0x419cc8 B.GE	419d60

  (63) 0x419ccc SUB	X3, X0, X24

  (63) 0x419cd0 ORR	W2, WZR, WZR

  (63) 0x419cd4 HINT	#0

  (63) 0x419cd8 HINT	#0

  (63) 0x419cdc HINT	#0

    (64) 0x419ce0 ADD	W4, W11, W2

    (64) 0x419ce4 ADD	W2, W2, #1

    (64) 0x419ce8 SBFM	X5, X4, #0, #31

    (64) 0x419cec ADD	W4, W4, #1

    (64) 0x419cf0 CMP	W12, W2

    (64) 0x419cf4 SUB	X5, X5, X24

    (64) 0x419cf8 ADD	X4, X3, W4,SXTW

    (64) 0x419cfc ADD	X6, X5, X18

    (64) 0x419d00 ADD	X7, X5, X0

    (64) 0x419d04 LDR	D0, [X20, X6,LSL #3]

    (64) 0x419d08 LDR	D1, [X21, X7,LSL #3]

    (64) 0x419d0c LDR	D2, [X25, X7,LSL #3]

    (64) 0x419d10 LDR	D3, [X25, X4,LSL #3]

    (64) 0x419d14 LDR	D4, [X22, X6,LSL #3]

    (64) 0x419d18 FMUL	D0, D1, D0

    (64) 0x419d1c FADD	D2, D0, D2

    (64) 0x419d20 FSUB	D2, D2, S3

    (64) 0x419d24 LDR	D3, [X26, X7,LSL #3]

    (64) 0x419d28 FMADD	D0, D4, D0, D3

    (64) 0x419d2c LDR	D3, [X26, X4,LSL #3]

    (64) 0x419d30 FSUB	D0, D0, S3

    (64) 0x419d34 LDR	D3, [X19, X7,LSL #3]

    (64) 0x419d38 FDIV	D0, D0, D2

    (64) 0x419d3c FADD	D1, D3, D1

    (64) 0x419d40 LDR	D3, [X19, X4,LSL #3]

    (64) 0x419d44 FSUB	D1, D1, S3

    (64) 0x419d48 FDIV	D1, D2, D1

    (64) 0x419d4c STR	D0, [X1, X5,LSL #3]

    (64) 0x419d50 STR	D1, [X20, X6,LSL #3]

    (64) 0x419d54 B.HI	419ce0

  (63) 0x419d58 B	419c88

0x419d5c HINT	#0

(62) 0x419d60 SBFM	X4, X2, #0, #31

(62) 0x419d64 ADD	W7, W2, #1

(62) 0x419d68 SUB	X23, X0, X24

(62) 0x419d6c ADD	W3, W3, W16

(62) 0x419d70 ADD	W2, W2, W16

(62) 0x419d74 SUB	X4, X4, X24

(62) 0x419d78 ADD	X7, X23, W7,SXTW

(62) 0x419d7c ADD	X5, X4, X18

(62) 0x419d80 ADD	X6, X4, X0

(62) 0x419d84 LD1D	{Z0.D}, P2/Z, [X20, X5,LSL #3]

(62) 0x419d88 LD1D	{Z1.D}, P2/Z, [X21, X6,LSL #3]

(62) 0x419d8c LD1D	{Z2.D}, P2/Z, [X25, X6,LSL #3]

(62) 0x419d90 LD1D	{Z3.D}, P2/Z, [X25, X7,LSL #3]

(62) 0x419d94 LD1D	{Z4.D}, P2/Z, [X26, X6,LSL #3]

(62) 0x419d98 FMUL	Z0.D, Z1.D, Z0.D

(62) 0x419d9c FADD	Z2.D, Z0.D, Z2.D

(62) 0x419da0 FSUB	Z2.D, Z2.D, Z3.D

(62) 0x419da4 LD1D	{Z3.D}, P2/Z, [X22, X5,LSL #3]

(62) 0x419da8 FMAD	Z0.D, P1/M, Z3.D, Z4.D

(62) 0x419dac LD1D	{Z3.D}, P2/Z, [X26, X7,LSL #3]

(62) 0x419db0 FSUB	Z0.D, Z0.D, Z3.D

(62) 0x419db4 LD1D	{Z3.D}, P2/Z, [X19, X6,LSL #3]

(62) 0x419db8 FDIV	Z0.D, P1/M, Z0.D, Z2.D

(62) 0x419dbc FADD	Z1.D, Z3.D, Z1.D

(62) 0x419dc0 LD1D	{Z3.D}, P2/Z, [X19, X7,LSL #3]

(62) 0x419dc4 FSUB	Z1.D, Z1.D, Z3.D

(62) 0x419dc8 FDIVR	Z1.D, P1/M, Z1.D, Z2.D

(62) 0x419dcc ST1D	{Z0.D}, P2, [X1, X4,LSL #3]

(62) 0x419dd0 ST1D	{Z1.D}, P2, [X20, X5,LSL #3]

(62) 0x419dd4 WHILELO	P2.D, W3, W17

(62) 0x419dd8 B.MI	419d60

(62) 0x419ddc B	419c88

0x419de0 ADRP	X0,

0x419de4 ADD	X0, X0, #4088

0x419de8 ORR	W1, WZR, W27

0x419dec BL	410380

0x419df0 ADRP	X0,

0x419df4 ADD	X0, X0, #16

0x419df8 ORR	W1, WZR, W27

0x419dfc BL	410050

0x419e00 LDP	X20, X19, [SP, #384]

0x419e04 LDP	X22, X21, [SP, #368]

0x419e08 LDP	X24, X23, [SP, #352]

0x419e0c LDP	X26, X25, [SP, #336]

0x419e10 LDP	X28, X27, [SP, #320]

0x419e14 LDP	X29, X30, [SP, #304]

0x419e18 ADD	SP, SP, #400

0x419e1c RET

Coverage (%)	Name	Module
►98.43+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run armclang_6

Source file and lines	advec_cell_kernel.f90:83-118,advec_cell_kernel.f90:124-149,advec_cell_kernel.f90:155-170,advec_cell_kernel.f90:177-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-261
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:83-118,124-149,155-170,177-204,210,216-261.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 78.75 to 2.00 cycles (39.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 78.75 to 41.91 cycles (1.88x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 22 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:161
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:178
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:188
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:178
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:188
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:188
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:199
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:199
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:199
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:252
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:252
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:96
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:96
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:96
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:161
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:161
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:161

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 120 bytes. The binary function is storing 66 bytes.

General properties

nb instructions	519
nb uops	504
loop length	2076
used w registers	23
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	85

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	63.00 cycles
front end	63.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	23.00	23.00	78.75	78.75	78.75	78.75	1.50	1.50	1.50	1.50	53.00	53.00	53.00	26.00	26.00
cycles	23.00	23.00	78.75	78.75	78.75	78.75	1.50	1.50	1.50	1.50	53.00	53.00	53.00	26.00	26.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	63.00
Dispatch	78.75
Overall L1	78.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	21%
load	23%
store	24%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	21%
load	23%
store	24%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 78.75 cycles. At this rate:

1% of peak load performance is reached (1.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 418ae0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X15, X13, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48bb08>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X14, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W23, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X21, X28, [X2, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X20, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X25, [X2, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X13, X15, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X22, X13, [X2, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X13, [X2, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X14, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X13, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X2, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X14, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR W0, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 418d94 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 419e00 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 418fac <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP W8, WZR, [X29, #396]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48abc8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #116	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #396]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4191c0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W9, W9, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W15, W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W16, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W12, W15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W15, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W13, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUBS W16, W12, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, WZR, W16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 418c70 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W23, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 4196dc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xbfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W28, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP W8, WZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48add0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3992	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4198e8 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xe08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W9, W9, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W15, W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W16, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W12, W15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W15, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W13, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUBS W16, W12, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, WZR, W16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 418e8c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP W8, WZR, [X29, #380]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48afb8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #124	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #132	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #380]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4191e0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W9, W9, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W14, W16, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W16, W16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD W14, W14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, #0, #4, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W0, W14, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W15, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W18, W14, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W18, WZR, W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 41908c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x5ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W23, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a1c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a1d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4191fc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x71c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W23, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a1e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a1f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3776	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48a208>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3848	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W19, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #100	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #412]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W9, W8, [X29, #412]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR W9, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 41951c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X10, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D0, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR WZR, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W3, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDRSW X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W10, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X8, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X9, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X8, X11, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X8, X9, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVK X8, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D2, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 419328 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x848>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W23, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a520>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3848	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a530>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48a544>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #76	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W19, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4196b8 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xbd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W12, W12, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDS W15, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W12, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUBS W14, W15, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W14, WZR, W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 4195ec <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a6bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a6cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 419dfc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x131c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W28, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP W8, WZR, [X29, #444]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48a6e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3944	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #68	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #444]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 419904 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W9, W9, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W14, W16, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W18, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W13, W14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W17, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W14, WZR, W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W15, W16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W16, W16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W0, W13, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W16, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, W17, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUBS W18, W13, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W18, WZR, W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 4197d8 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a8e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3992	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a8f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 41991c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xe3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a904>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3944	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a914>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3968	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48a928>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4040	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 419bbc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x10dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X13, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W2, W12, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D0, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W2, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W11, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X16, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X13, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, W10,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB W0, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W1, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X17, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X15, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X16, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X16, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D2, X16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4199fc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W27, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48abc0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4040	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48abd0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48abe4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 419de0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W10, W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X26, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUBS W12, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD W14, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDS W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W13, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W17, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W17, WZR, W17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 419c94 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x11b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
ADRP X0, <48ade0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48bdf0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run armclang_6

Source file and lines	advec_cell_kernel.f90:83-118,advec_cell_kernel.f90:124-149,advec_cell_kernel.f90:155-170,advec_cell_kernel.f90:177-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-261
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 22 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:161
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:178
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:188
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:178
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:188
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:188
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:199
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:199
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:199
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:252
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:252
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:96
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:96
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:96
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:107
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:161
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:161
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:161

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 120 bytes. The binary function is storing 66 bytes.

General properties

nb instructions	519
nb uops	504
loop length	2076
used w registers	23
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	85

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	63.00 cycles
front end	63.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	23.00	23.00	78.75	78.75	78.75	78.75	1.50	1.50	1.50	1.50	53.00	53.00	53.00	26.00	26.00
cycles	23.00	23.00	78.75	78.75	78.75	78.75	1.50	1.50	1.50	1.50	53.00	53.00	53.00	26.00	26.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	63.00
Dispatch	78.75
Overall L1	78.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	21%
load	23%
store	24%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	21%
load	23%
store	24%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 78.75 cycles. At this rate:

1% of peak load performance is reached (1.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 418ae0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X15, X13, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48bb08>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X14, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W23, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X21, X28, [X2, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X20, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X25, [X2, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X13, X15, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X22, X13, [X2, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X13, [X2, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X14, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X13, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X2, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X14, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR W0, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 418d94 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 419e00 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 418fac <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP W8, WZR, [X29, #396]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48abc8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #116	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #396]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4191c0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W9, W9, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W15, W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W16, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W12, W15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W15, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W13, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUBS W16, W12, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, WZR, W16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 418c70 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W23, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 4196dc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xbfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W28, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP W8, WZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48add0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3992	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4198e8 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xe08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W9, W9, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W15, W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W16, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W14, W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W12, W15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W15, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W13, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUBS W16, W12, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, WZR, W16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 418e8c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x3ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP W8, WZR, [X29, #380]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48afb8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #124	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #132	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #380]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4191e0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W9, W9, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W14, W16, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W16, W16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD W14, W14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CCMP W14, #0, #4, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W0, W14, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W15, WZR, WZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W18, W14, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W18, WZR, W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 41908c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x5ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W23, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a1c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a1d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4191fc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x71c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W23, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a1e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a1f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3776	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48a208>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3848	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #92	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W19, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #100	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #412]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W9, W8, [X29, #412]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W9, W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR W9, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.EQ 41951c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X10, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D0, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR WZR, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W3, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDRSW X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W10, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X8, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X9, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X8, X11, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X8, X9, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVK X8, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D2, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 419328 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x848>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W23, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a520>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3848	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a530>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48a544>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #76	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W19, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #428]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4196b8 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xbd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W12, W12, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDS W15, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W12, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUBS W14, W15, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W14, WZR, W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 4195ec <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xb0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48a6bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a6cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 419dfc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x131c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W28, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP W8, WZR, [X29, #444]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48a6e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3944	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #68	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR W8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #444]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 419904 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W9, W9, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W12, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W13, W16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W14, W16, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W18, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W13, W14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W17, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W14, WZR, W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W15, W16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W16, W16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W0, W13, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W16, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, W17, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUBS W18, W13, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W18, WZR, W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 4197d8 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xcf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a8e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3992	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a8f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 41991c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xe3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a904>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3944	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48a914>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3968	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48a928>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4040	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #36	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 419bbc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x10dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X13, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W2, W12, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D0, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W2, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W11, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X16, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X13, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, W10,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB W0, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W1, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X17, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X15, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X16, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X16, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D2, X16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4199fc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W27, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48abc0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4040	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48abd0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48abe4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X5, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W10, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 419de0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W10, W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X26, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUBS W12, W15, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD W14, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W13, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDS W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL W13, WZR, W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W17, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W17, WZR, W17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P0.D, WZR, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 419c94 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x11b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
ADRP X0, <48ade0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #4088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48bdf0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par–	18.73	25.54
▼Loop 71 - - exec–	3.66	4.99
○Loop 70 - - exec	0.00	0.02
▼Loop 62 - - exec–	3.61	4.93
▼Loop 63 - - exec–	0.00	0.02
○Loop 64 - - exec	0.00	0.00
▼Loop 72 - - exec–	1.04	1.42
▼Loop 73 - - exec–	0.00	0.00
○Loop 74 - - exec	0.00	0.00
▼Loop 66 - - exec–	0.05	0.07
▼Loop 67 - - exec–	2.76	3.76
○Loop 65 - - exec	0.00	0.01
▼Loop 68 - - exec–	0.00	0.02
○Loop 69 - - exec	3.99	5.45
▼Loop 81 - - exec–	0.00	0.01
○Loop 82 - - exec	1.29	1.76
○Loop 83 - - exec	0.00	0.00
▼Loop 75 - - exec–	0.00	0.02
○Loop 76 - - exec	1.32	1.80
○Loop 77 - - exec	0.00	0.00
▼Loop 78 - - exec–	0.00	0.02
○Loop 79 - - exec	0.97	1.33
○Loop 80 - - exec	0.00	0.00

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Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code