OV - exec - Function _QMfield_summary_kernel_modulePfield_summary_kernel..omp

	Function: _QMfield_summary_kernel_modulePfield_summary_kernel..omp_par	Module: exec	Source: :0-0	Coverage (incl. loops): 0.33% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 52 - 71

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52:     press=0.0

53:

54:     !$OMP PARALLEL

55:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

56:     DO k=y_min,y_max

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

0x420940 SUB	SP, SP, #288

0x420944 STP	X29, X30, [SP, #192]

0x420948 STP	X28, X27, [SP, #208]

0x42094c STP	X26, X25, [SP, #224]

0x420950 STP	X24, X23, [SP, #240]

0x420954 STP	X22, X21, [SP, #256]

0x420958 STP	X20, X19, [SP, #272]

0x42095c ADD	X29, SP, #192

0x420960 LDP	X15, X14, [X2, #64]

0x420964 LDP	X8, X9, [X2]

0x420968 ADRP	X0,

0x42096c ADD	X0, X0, #2704

0x420970 LDR	X10, [X2, #16]

0x420974 LDR	X11, [X2, #32]

0x420978 LDR	X19, [X2, #160]

0x42097c STP	X15, X14, [SP, #16]

0x420980 LDP	X15, X14, [X2, #80]

0x420984 LDP	X12, X13, [X2, #48]

0x420988 LDR	X21, [X8]

0x42098c LDR	W27, [X12]

0x420990 LDR	W8, [X13]

0x420994 SUBS	W8, W8, W27

0x420998 STP	X15, X14, [SP, #32]

0x42099c LDP	X15, X14, [X2, #96]

0x4209a0 LDR	X22, [X9]

0x4209a4 LDP	X28, X20, [X2, #144]

0x4209a8 LDR	X23, [X10]

0x4209ac LDR	X24, [X11]

0x4209b0 STP	XZR, XZR, [X29, #984]

0x4209b4 STP	XZR, XZR, [X29, #968]

0x4209b8 STUR	XZR, [X29, #448]

0x4209bc CSINV	W8, W8, WZR, #10

0x4209c0 STP	W8, WZR, [X29, #492]

0x4209c4 MOVZ	W8, #1

0x4209c8 STUR	W8, [X29, #488]

0x4209cc STP	X15, X14, [SP, #48]

0x4209d0 LDP	X15, X25, [X2, #112]

0x4209d4 LDP	X26, X14, [X2, #128]

0x4209d8 STP	X15, X14, [SP, #64]

0x4209dc BL	4101f0

0x4209e0 ORR	W1, WZR, W0

0x4209e4 ADRP	X0,

0x4209e8 ADD	X0, X0, #2656

0x4209ec SUB	X3, X29, #12

0x4209f0 SUB	X4, X29, #16

0x4209f4 STR	WZR, [SP]

0x4209f8 SUB	X5, X29, #20

0x4209fc SUB	X6, X29, #24

0x420a00 MOVZ	W2, #34

0x420a04 MOVZ	W7, #1

0x420a08 STR	W1, [SP, #84]

0x420a0c BL	410090

0x420a10 LDP	W8, W12, [X29, #492]

0x420a14 LDR	X30, [SP, #72]

0x420a18 SUB	W8, W8, W12

0x420a1c CMN	W8, #1

0x420a20 B.EQ	420d84

0x420a24 LDP	X10, X11, [SP, #56]

0x420a28 CNTD	X13, ALL

0x420a2c MOVI	D3, #0

0x420a30 FMOV	D0, #0.1250000

0x420a34 MOVI	V1.2D, #0

0x420a38 FDUP	Z2.D, #64

0x420a3c MOVI	D6, #0

0x420a40 PTRUE	P0.D, VL1

0x420a44 MOVI	D4, #0

0x420a48 MOVI	D5, #0

0x420a4c MOVI	D7, #0

0x420a50 ADD	W12, W12, W27

0x420a54 ORR	W9, WZR, WZR

0x420a58 ORR	W17, WZR, W12

0x420a5c LDR	W10, [X10]

0x420a60 LDR	W14, [X11]

0x420a64 CNTW	X11, ALL

0x420a68 PTRUE	P1.D, ALL

0x420a6c SUB	W16, WZR, W11

0x420a70 SUBS	W14, W14, W10

0x420a74 CSINC	W15, WZR, WZR, #11

0x420a78 ADDS	W14, W14, #1

0x420a7c CSEL	W15, WZR, W15, #0

0x420a80 AND	W16, W14, W16

0x420a84 B	420a98

  (193) 0x420a88 CMP	W9, W8

  (193) 0x420a8c ADD	W9, W9, #1

  (193) 0x420a90 ADD	W17, W17, #1

  (193) 0x420a94 B.EQ	420d84

  (193) 0x420a98 CBZ	W15, 420a88

  (193) 0x420a9c ADD	W18, W12, W9

  (193) 0x420aa0 SBFM	X2, X17, #0, #31

  (193) 0x420aa4 CMP	W14, W11

  (193) 0x420aa8 SBFM	X18, X18, #0, #31

  (193) 0x420aac SUB	X2, X2, X23

  (193) 0x420ab0 SUB	X18, X18, X23

  (193) 0x420ab4 MUL	X2, X2, X24

  (193) 0x420ab8 MUL	X18, X18, X22

  (193) 0x420abc ADD	X3, X24, X2

  (193) 0x420ac0 ADD	X0, X30, X18,LSL #3

  (193) 0x420ac4 ADD	X1, X28, X18,LSL #3

  (193) 0x420ac8 B.CS	420ae0

  (193) 0x420acc ORR	W4, WZR, WZR

  (193) 0x420ad0 ORR	W5, WZR, W10

  (193) 0x420ad4 B	420cc0

0x420ad8 HINT	#0

0x420adc HINT	#0

(194) 0x420ae0 SEL	Z3.D, P0, Z3.D, Z1.D

(194) 0x420ae4 SEL	Z6.D, P0, Z6.D, Z1.D

(194) 0x420ae8 MOVI	V20.2D, #0

(194) 0x420aec MOVI	V17.2D, #0

(194) 0x420af0 MOVI	V18.2D, #0

(194) 0x420af4 ORR	W4, WZR, WZR

(194) 0x420af8 SEL	Z4.D, P0, Z4.D, Z1.D

(194) 0x420afc SEL	Z16.D, P0, Z5.D, Z1.D

(194) 0x420b00 MOVI	V19.2D, #0

(194) 0x420b04 SEL	Z5.D, P0, Z7.D, Z1.D

(194) 0x420b08 MOVI	V7.2D, #0

  (192) 0x420b0c ADD	W5, W10, W4

  (192) 0x420b10 ADD	W4, W4, W11

  (192) 0x420b14 SBFM	X5, X5, #0, #31

  (192) 0x420b18 CMP	W16, W4

  (192) 0x420b1c SUB	X5, X5, X21

  (192) 0x420b20 ADD	X6, X5, X2

  (192) 0x420b24 LD1D	{Z27.D}, P1/Z, [X0, X5,LSL #3]

  (192) 0x420b28 ADD	X7, X20, X6,LSL #3

  (192) 0x420b2c LD1D	{Z21.D}, P1/Z, [X20, X6,LSL #3]

  (192) 0x420b30 LD1D	{Z23.D}, P1/Z, [X19, X6,LSL #3]

  (192) 0x420b34 LD1D	{Z22.D}, P1/Z, [X7, X13,LSL #3]

  (192) 0x420b38 ADD	X7, X19, X6,LSL #3

  (192) 0x420b3c ADD	X6, X5, #1

  (192) 0x420b40 LD1D	{Z24.D}, P1/Z, [X7, X13,LSL #3]

  (192) 0x420b44 ADD	X7, X6, X2

  (192) 0x420b48 ADD	X6, X6, X3

  (192) 0x420b4c ADD	X27, X20, X7,LSL #3

  (192) 0x420b50 LD1D	{Z25.D}, P1/Z, [X19, X7,LSL #3]

  (192) 0x420b54 FMUL	Z21.D, Z21.D, Z21.D

  (192) 0x420b58 FMUL	Z23.D, Z23.D, Z23.D

  (192) 0x420b5c FMUL	Z22.D, Z22.D, Z22.D

  (192) 0x420b60 FMUL	Z24.D, Z24.D, Z24.D

  (192) 0x420b64 FADD	Z21.D, Z23.D, Z21.D

  (192) 0x420b68 LD1D	{Z23.D}, P1/Z, [X20, X7,LSL #3]

  (192) 0x420b6c FMUL	Z25.D, Z25.D, Z25.D

  (192) 0x420b70 FADD	Z22.D, Z24.D, Z22.D

  (192) 0x420b74 LD1D	{Z24.D}, P1/Z, [X27, X13,LSL #3]

  (192) 0x420b78 ADD	X27, X19, X7,LSL #3

  (192) 0x420b7c ADD	X7, X5, X3

  (192) 0x420b80 LD1D	{Z26.D}, P1/Z, [X27, X13,LSL #3]

  (192) 0x420b84 ADD	X27, X20, X7,LSL #3

  (192) 0x420b88 FMUL	Z23.D, Z23.D, Z23.D

  (192) 0x420b8c FMUL	Z24.D, Z24.D, Z24.D

  (192) 0x420b90 FMUL	Z26.D, Z26.D, Z26.D

  (192) 0x420b94 FADD	Z23.D, Z25.D, Z23.D

  (192) 0x420b98 LD1D	{Z25.D}, P1/Z, [X19, X7,LSL #3]

  (192) 0x420b9c FADD	Z21.D, Z23.D, Z21.D

  (192) 0x420ba0 LD1D	{Z23.D}, P1/Z, [X20, X7,LSL #3]

  (192) 0x420ba4 FADD	Z24.D, Z26.D, Z24.D

  (192) 0x420ba8 FADD	Z22.D, Z24.D, Z22.D

  (192) 0x420bac LD1D	{Z24.D}, P1/Z, [X27, X13,LSL #3]

  (192) 0x420bb0 ADD	X27, X19, X7,LSL #3

  (192) 0x420bb4 ADD	X7, X20, X6,LSL #3

  (192) 0x420bb8 LD1D	{Z26.D}, P1/Z, [X27, X13,LSL #3]

  (192) 0x420bbc FMUL	Z25.D, Z25.D, Z25.D

  (192) 0x420bc0 FMUL	Z23.D, Z23.D, Z23.D

  (192) 0x420bc4 FMUL	Z24.D, Z24.D, Z24.D

  (192) 0x420bc8 FADD	Z23.D, Z25.D, Z23.D

  (192) 0x420bcc LD1D	{Z25.D}, P1/Z, [X19, X6,LSL #3]

  (192) 0x420bd0 FMUL	Z26.D, Z26.D, Z26.D

  (192) 0x420bd4 FADD	Z21.D, Z23.D, Z21.D

  (192) 0x420bd8 LD1D	{Z23.D}, P1/Z, [X20, X6,LSL #3]

  (192) 0x420bdc FADD	Z24.D, Z26.D, Z24.D

  (192) 0x420be0 FADD	Z22.D, Z24.D, Z22.D

  (192) 0x420be4 LD1D	{Z24.D}, P1/Z, [X7, X13,LSL #3]

  (192) 0x420be8 ADD	X7, X19, X6,LSL #3

  (192) 0x420bec FMUL	Z25.D, Z25.D, Z25.D

  (192) 0x420bf0 ADD	X6, X5, X18

  (192) 0x420bf4 LD1D	{Z26.D}, P1/Z, [X7, X13,LSL #3]

  (192) 0x420bf8 ADD	X7, X25, X6,LSL #3

  (192) 0x420bfc FMUL	Z23.D, Z23.D, Z23.D

  (192) 0x420c00 FADD	Z23.D, Z25.D, Z23.D

  (192) 0x420c04 LD1D	{Z25.D}, P1/Z, [X26, X6,LSL #3]

  (192) 0x420c08 FMUL	Z24.D, Z24.D, Z24.D

  (192) 0x420c0c FMUL	Z26.D, Z26.D, Z26.D

  (192) 0x420c10 FADD	Z21.D, Z23.D, Z21.D

  (192) 0x420c14 LD1D	{Z23.D}, P1/Z, [X25, X6,LSL #3]

  (192) 0x420c18 FMUL	Z21.D, Z21.D, Z2.D

  (192) 0x420c1c FADD	Z24.D, Z26.D, Z24.D

  (192) 0x420c20 FADD	Z22.D, Z24.D, Z22.D

  (192) 0x420c24 LD1D	{Z24.D}, P1/Z, [X7, X13,LSL #3]

  (192) 0x420c28 ADD	X7, X26, X6,LSL #3

  (192) 0x420c2c ADD	X6, X0, X5,LSL #3

  (192) 0x420c30 LD1D	{Z26.D}, P1/Z, [X7, X13,LSL #3]

  (192) 0x420c34 FMUL	Z25.D, Z25.D, Z23.D

  (192) 0x420c38 LD1D	{Z28.D}, P1/Z, [X6, X13,LSL #3]

  (192) 0x420c3c ADD	X6, X1, X5,LSL #3

  (192) 0x420c40 FADD	Z3.D, Z3.D, Z23.D

  (192) 0x420c44 FMUL	Z22.D, Z22.D, Z2.D

  (192) 0x420c48 FMLA	Z16.D, P1/M, Z21.D, Z25.D

  (192) 0x420c4c LD1D	{Z21.D}, P1/Z, [X1, X5,LSL #3]

  (192) 0x420c50 FMLA	Z4.D, P1/M, Z27.D, Z25.D

  (192) 0x420c54 FADD	Z6.D, Z6.D, Z25.D

  (192) 0x420c58 FADD	Z20.D, Z20.D, Z24.D

  (192) 0x420c5c FMUL	Z26.D, Z26.D, Z24.D

  (192) 0x420c60 FMLA	Z19.D, P1/M, Z22.D, Z26.D

  (192) 0x420c64 LD1D	{Z22.D}, P1/Z, [X6, X13,LSL #3]

  (192) 0x420c68 FMLA	Z18.D, P1/M, Z28.D, Z26.D

  (192) 0x420c6c FMLA	Z5.D, P1/M, Z21.D, Z23.D

  (192) 0x420c70 FADD	Z17.D, Z17.D, Z26.D

  (192) 0x420c74 FMLA	Z7.D, P1/M, Z22.D, Z24.D

  (192) 0x420c78 B.NE	420b0c

(194) 0x420c7c FADD	Z3.D, Z20.D, Z3.D

(194) 0x420c80 FADD	Z6.D, Z17.D, Z6.D

(194) 0x420c84 CMP	W14, W16

(194) 0x420c88 ADD	W5, W10, W16

(194) 0x420c8c ORR	W4, WZR, W16

(194) 0x420c90 FADD	Z4.D, Z18.D, Z4.D

(194) 0x420c94 FADD	Z16.D, Z19.D, Z16.D

(194) 0x420c98 FADD	Z7.D, Z7.D, Z5.D

(194) 0x420c9c FADDV	D3, P1, Z3.D

(194) 0x420ca0 FADDV	D6, P1, Z6.D

(194) 0x420ca4 STP	D6, D3, [X29, #984]

(194) 0x420ca8 FADDV	D4, P1, Z4.D

(194) 0x420cac FADDV	D5, P1, Z16.D

(194) 0x420cb0 STP	D5, D4, [X29, #960]

(194) 0x420cb4 FADDV	D7, P1, Z7.D

(194) 0x420cb8 STUR	D7, [X29, #464]

(194) 0x420cbc B.EQ	420a88

    (195) 0x420cc0 SBFM	X6, X5, #0, #31

    (195) 0x420cc4 ADD	W5, W5, #1

    (195) 0x420cc8 SUB	X6, X6, X21

    (195) 0x420ccc ADD	X7, X6, X2

    (195) 0x420cd0 LDR	D16, [X20, X7,LSL #3]

    (195) 0x420cd4 LDR	D17, [X19, X7,LSL #3]

    (195) 0x420cd8 ADD	X7, X6, #1

    (195) 0x420cdc ADD	X6, X6, X3

    (195) 0x420ce0 ADD	X27, X7, X2

    (195) 0x420ce4 LDR	D19, [X20, X6,LSL #3]

    (195) 0x420ce8 LDR	D18, [X19, X27,LSL #3]

    (195) 0x420cec FMUL	D16, D16, D16

    (195) 0x420cf0 FMADD	D16, D17, D17, D16

    (195) 0x420cf4 LDR	D17, [X20, X27,LSL #3]

    (195) 0x420cf8 FMUL	D17, D17, D17

    (195) 0x420cfc FMADD	D17, D18, D18, D17

    (195) 0x420d00 FMUL	D18, D19, D19

    (195) 0x420d04 LDR	D19, [X19, X6,LSL #3]

    (195) 0x420d08 ADD	X6, X7, X3

    (195) 0x420d0c LDR	D20, [X19, X6,LSL #3]

    (195) 0x420d10 FMADD	D18, D19, D19, D18

    (195) 0x420d14 LDR	D19, [X20, X6,LSL #3]

    (195) 0x420d18 ADD	W6, W10, W4

    (195) 0x420d1c ADD	W4, W4, #1

    (195) 0x420d20 SBFM	X6, X6, #0, #31

    (195) 0x420d24 CMP	W14, W4

    (195) 0x420d28 SUB	X6, X6, X21

    (195) 0x420d2c ADD	X7, X6, X18

    (195) 0x420d30 FADD	D16, D18, D16

    (195) 0x420d34 FMUL	D19, D19, D19

    (195) 0x420d38 FMADD	D18, D20, D20, D19

    (195) 0x420d3c LDR	D19, [X25, X7,LSL #3]

    (195) 0x420d40 LDR	D20, [X26, X7,LSL #3]

    (195) 0x420d44 FADD	D17, D18, D17

    (195) 0x420d48 FMUL	D18, D20, D19

    (195) 0x420d4c FADD	D3, D3, D19

    (195) 0x420d50 FADD	D16, D17, D16

    (195) 0x420d54 FMUL	D16, D16, D0

    (195) 0x420d58 FADD	D6, D6, D18

    (195) 0x420d5c FMADD	D5, D16, D18, D5

    (195) 0x420d60 STP	D6, D3, [X29, #984]

    (195) 0x420d64 LDR	D17, [X0, X6,LSL #3]

    (195) 0x420d68 FMADD	D4, D17, D18, D4

    (195) 0x420d6c STP	D5, D4, [X29, #960]

    (195) 0x420d70 LDR	D16, [X1, X6,LSL #3]

    (195) 0x420d74 FMADD	D7, D16, D19, D7

    (195) 0x420d78 STUR	D7, [X29, #464]

    (195) 0x420d7c B.HI	420cc0

  (193) 0x420d80 B	420a88

0x420d84 LDR	W19, [SP, #84]

0x420d88 ADRP	X0,

0x420d8c ADD	X0, X0, #2656

0x420d90 ORR	W1, WZR, W19

0x420d94 BL	410380

0x420d98 ADRP	X0,

0x420d9c ADD	X0, X0, #2680

0x420da0 ORR	W1, WZR, W19

0x420da4 BL	410050

0x420da8 SUB	X8, X29, #32

0x420dac SUB	X9, X29, #40

0x420db0 SUB	X10, X29, #48

0x420db4 ADRP	X6,

0x420db8 ORR	W1, WZR, W19

0x420dbc STP	X8, X9, [SP, #88]

0x420dc0 SUB	X8, X29, #56

0x420dc4 ADRP	X0,

0x420dc8 ADD	X0, X0, #2704

0x420dcc ADRP	X5, 420dcc

0x420dd0 ADD	X5, X5, #3744

0x420dd4 STP	X10, X8, [SP, #104]

0x420dd8 SUB	X8, X29, #64

0x420ddc ADD	X4, SP, #88

0x420de0 MOVZ	W2, #5

0x420de4 STR	X8, [SP, #120]

0x420de8 MOVZ	W3, #40

0x420dec LDR	X6, [X6, #2600]

0x420df0 BL	410040

0x420df4 CMP	W0, #1

0x420df8 B.NE	420e70

0x420dfc LDP	X9, X8, [SP, #16]

0x420e00 LDUR	D1, [X29, #480]

0x420e04 ADRP	X2,

0x420e08 ADRP	X0,

0x420e0c ADD	X0, X0, #2704

0x420e10 ORR	W1, WZR, W19

0x420e14 LDR	D0, [X9]

0x420e18 FADD	D0, D1, D0

0x420e1c STR	D0, [X9]

0x420e20 LDR	D0, [X8]

0x420e24 LDUR	D1, [X29, #472]

0x420e28 FADD	D0, D1, D0

0x420e2c STR	D0, [X8]

0x420e30 LDP	X9, X8, [SP, #32]

0x420e34 LDUR	D1, [X29, #464]

0x420e38 LDR	D0, [X9]

0x420e3c FADD	D0, D1, D0

0x420e40 STR	D0, [X9]

0x420e44 LDR	D0, [X8]

0x420e48 LDUR	D1, [X29, #456]

0x420e4c FADD	D0, D1, D0

0x420e50 STR	D0, [X8]

0x420e54 LDR	X8, [SP, #48]

0x420e58 LDUR	D1, [X29, #448]

0x420e5c LDR	D0, [X8]

0x420e60 FADD	D0, D1, D0

0x420e64 STR	D0, [X8]

0x420e68 LDR	X2, [X2, #2600]

0x420e6c BL	4102b0

0x420e70 ADRP	X0,

0x420e74 ADD	X0, X0, #2728

0x420e78 ORR	W1, WZR, W19

0x420e7c BL	410050

0x420e80 LDP	X20, X19, [SP, #272]

0x420e84 LDP	X22, X21, [SP, #256]

0x420e88 LDP	X24, X23, [SP, #240]

0x420e8c LDP	X26, X25, [SP, #224]

0x420e90 LDP	X28, X27, [SP, #208]

0x420e94 LDP	X29, X30, [SP, #192]

0x420e98 ADD	SP, SP, #288

0x420e9c RET

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.26+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	field_summary_kernel	field_summary_kernel.f90:77	exec
○	field_summary	field_summary.f90:81	exec
○	hydro	hydro.f90:81	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_6

Source file and lines	field_summary_kernel.f90:52-71
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:52-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.17 to 5.17 cycles (4.48x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 23.17 to 11.10 cycles (2.09x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 7 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 15 bytes. The binary function is storing 9 bytes.

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	155
nb uops	153
loop length	620
used w registers	17
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	1
used z registers	1
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.13 cycles
front end	19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	16.75	16.75	16.75	16.75	4.50	4.50	4.50	4.50	23.17	22.83	23.00	10.00	10.00
cycles	5.50	5.50	16.75	16.75	16.75	16.75	4.50	4.50	4.50	4.50	23.17	22.83	23.00	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.13
Dispatch	23.17
Overall L1	23.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	32%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	21%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

INT+FP

all	29%
load	32%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.17 cycles. At this rate:

0% of peak load performance is reached (0.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.39 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 420940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X15, X14, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48b968>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2704	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X15, X14, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X13, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X21, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W27, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W8, W8, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STP X15, X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X28, X20, [X2, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP XZR, XZR, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP X15, X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X25, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X14, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X15, X14, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b9e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X5, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 420d84 <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVI D3, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D0, #0.1250000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDUP Z2.D, #64	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI D4, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD W12, W12, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W17, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB W16, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W14, W14, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDS W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 420a98 <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48bd88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48bd98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2680	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X6, <48fdb4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X8, X9, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X8, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48bdc4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2704	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X5, 420dcc <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x48c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, #3744	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X10, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W3, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X6, [X6, #2600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 420e70 <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR D1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <48fe04>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48be08>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2704	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDUR D1, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X9, X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR D1, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDUR D1, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D1, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #2600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4102b0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48be70>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2728	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_6

Source file and lines	field_summary_kernel.f90:52-71
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.17 to 5.17 cycles (4.48x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 7 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 15 bytes. The binary function is storing 9 bytes.

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	155
nb uops	153
loop length	620
used w registers	17
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	1
used z registers	1
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.13 cycles
front end	19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	16.75	16.75	16.75	16.75	4.50	4.50	4.50	4.50	23.17	22.83	23.00	10.00	10.00
cycles	5.50	5.50	16.75	16.75	16.75	16.75	4.50	4.50	4.50	4.50	23.17	22.83	23.00	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.13
Dispatch	23.17
Overall L1	23.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	32%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	21%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

INT+FP

all	29%
load	32%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.17 cycles. At this rate:

0% of peak load performance is reached (0.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.39 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 420940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X15, X14, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADRP X0, <48b968>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2704	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X15, X14, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X13, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X21, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W27, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W8, W8, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STP X15, X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X28, X20, [X2, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP XZR, XZR, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W8, WZR, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP X15, X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X25, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X14, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X15, X14, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b9e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X4, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB X5, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W1, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W12, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 420d84 <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CNTD X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVI D3, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D0, #0.1250000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDUP Z2.D, #64	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI D4, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD W12, W12, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W17, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB W16, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W14, W14, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDS W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND W16, W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 420a98 <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W19, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <48bd88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48bd98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2680	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X6, <48fdb4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X8, X9, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X8, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48bdc4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2704	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X5, 420dcc <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x48c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, #3744	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X10, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W3, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X6, [X6, #2600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 420e70 <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR D1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <48fe04>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48be08>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2704	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDUR D1, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X9, X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR D1, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDUR D1, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D1, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #2600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4102b0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48be70>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2728	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par–	0.33	0.45
▼Loop 194 - - exec–	0.00	0.00
○Loop 192 - - exec	0.33	0.45
▼Loop 193 - - exec–	0.00	0.00
○Loop 195 - - exec	0.00	0.00

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Code clean check

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Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code