OV - exec - Function _QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp

	Function: _QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par	Module: exec	Source: :0-0 [...]	Coverage (incl. loops): 0.05% \| (excl. loops): 0.02%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 30 - 167

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30:   SUBROUTINE generate_chunk_kernel(x_min,x_max,y_min,y_max, &

[...]

86:     !$OMP DO

87:     DO k=y_min-2,y_max+2

88:     !$OMP SIMD

89:       DO j=x_min-2,x_max+2

90:         energy0(j,k)=state_energy(1)

91:       ENDDO

92:     ENDDO

93:     !$OMP END DO

94:     !$OMP DO

95:     DO k=y_min-2,y_max+2

96:     !$OMP SIMD

97:       DO j=x_min-2,x_max+2

98:         density0(j,k)=state_density(1)

99:       ENDDO

100:     ENDDO

101:     !$OMP END DO

102:     !$OMP DO

103:     DO k=y_min-2,y_max+2

104:     !$OMP SIMD

105:       DO j=x_min-2,x_max+2

106:         xvel0(j,k)=state_xvel(1)

107:       ENDDO

108:     ENDDO

109:     !$OMP END DO

110:     !$OMP DO

111:     DO k=y_min-2,y_max+2

112:     !$OMP SIMD

113:       DO j=x_min-2,x_max+2

114:         yvel0(j,k)=state_yvel(1)

115:       ENDDO

116:     ENDDO

117:     !$OMP END DO

118:

119:     DO state=2,number_of_states

120:

121:       ! Could the velocity setting be thread unsafe?

122:       x_cent=state_xmin(state)

123:       y_cent=state_ymin(state)

124:

125:       !$OMP DO PRIVATE(radius,jt,kt)

126:       DO k=y_min-2,y_max+2

127:       !$OMP SIMD

128:         DO j=x_min-2,x_max+2

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

[...]

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

[...]

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

[...]

167:       ENDDO

0x4221f0 STP	X29, X30, [SP, #928]!

0x4221f4 STP	X28, X27, [SP, #16]

0x4221f8 STP	X26, X25, [SP, #32]

0x4221fc ADD	X29, SP, #0

0x422200 STP	X24, X23, [SP, #48]

0x422204 STP	X22, X21, [SP, #64]

0x422208 STP	X20, X19, [SP, #80]

0x42220c SUB	SP, SP, #400

0x422210 ADDVL	SP, SP, #62

0x422214 LDP	X15, X14, [X2, #72]

0x422218 LDP	X12, X13, [X2, #56]

0x42221c MOVZ	W20, #1

0x422220 ADRP	X0,

0x422224 ADD	X0, X0, #3376

0x422228 LDR	X11, [X2, #40]

0x42222c LDP	X8, X9, [X2, #8]

0x422230 LDR	X10, [X2, #24]

0x422234 STR	X14, [SP, #88]

0x422238 LDR	X14, [X2, #88]

0x42223c STP	X13, X12, [SP, #96]

0x422240 LDR	W12, [X12]

0x422244 LDR	W13, [X13]

0x422248 LDR	X19, [X8]

0x42224c LDR	X8, [X9]

0x422250 SUB	W21, W12, #2

0x422254 STP	X15, X14, [SP, #304]

0x422258 ADD	W12, W13, #2

0x42225c LDP	X14, X27, [X2, #96]

0x422260 STR	X8, [SP, #240]

0x422264 LDR	X8, [X11]

0x422268 LDR	X22, [X10]

0x42226c STR	WZR, [SP, #328]

0x422270 STR	W20, [SP, #320]

0x422274 SUBS	W12, W12, W21

0x422278 CSINV	W12, W12, WZR, #10

0x42227c STR	W12, [SP, #324]

0x422280 STR	X14, [SP, #80]

0x422284 LDP	X15, X14, [X2, #112]

0x422288 STR	X8, [SP, #232]

0x42228c STP	X14, X15, [SP, #48]

0x422290 LDP	X15, X14, [X2, #128]

0x422294 STP	X14, X15, [SP, #176]

0x422298 LDP	X15, X14, [X2, #144]

0x42229c STR	X14, [SP, #280]

0x4222a0 LDP	X23, X14, [X2, #160]

0x4222a4 STR	X14, [SP, #168]

0x4222a8 LDR	X14, [X2, #176]

0x4222ac STR	X14, [SP, #136]

0x4222b0 LDR	X14, [X2, #184]

0x4222b4 STR	X14, [SP, #224]

0x4222b8 LDR	X14, [X2, #192]

0x4222bc STR	X14, [SP, #128]

0x4222c0 LDR	X14, [X2, #200]

0x4222c4 STR	X14, [SP, #216]

0x4222c8 LDP	X14, X28, [X2, #208]

0x4222cc STR	X14, [SP, #120]

0x4222d0 LDP	X14, X24, [X2, #224]

0x4222d4 STR	X14, [SP, #112]

0x4222d8 LDR	X14, [X2, #240]

0x4222dc STP	X15, X14, [SP, #264]

0x4222e0 LDP	X13, X14, [X2, #248]

0x4222e4 STR	X13, [SP, #160]

0x4222e8 LDP	X13, X12, [X2, #264]

0x4222ec STP	X13, X14, [SP, #32]

0x4222f0 STR	X12, [SP, #24]

0x4222f4 BL	4101f0

0x4222f8 ORR	W26, WZR, W0

0x4222fc ADRP	X0,

0x422300 ADD	X0, X0, #3136

0x422304 ADD	X3, SP, #332

0x422308 ADD	X4, SP, #328

0x42230c STR	WZR, [SP]

0x422310 ORR	W1, WZR, W26

0x422314 ADD	X5, SP, #324

0x422318 ADD	X6, SP, #320

0x42231c MOVZ	W2, #34

0x422320 MOVZ	W7, #1

0x422324 BL	410090

0x422328 LDR	W10, [SP, #328]

0x42232c LDR	W8, [SP, #324]

0x422330 SUB	W8, W8, W10

0x422334 CMN	W8, #1

0x422338 B.EQ	422440

0x42233c LDP	X13, X11, [SP, #48]

0x422340 PTRUE	P0.D, ALL

0x422344 ADD	W10, W10, W21

0x422348 ORR	W9, WZR, WZR

0x42234c LDR	W12, [X11]

0x422350 LDR	W13, [X13]

0x422354 SUB	W11, W12, #2

0x422358 ADD	W14, W13, #2

0x42235c SUB	W12, W13, W12

0x422360 CNTW	X13, ALL

0x422364 ADD	W12, W12, #5

0x422368 CMP	W12, W13

0x42236c CSINC	W15, WZR, WZR, #2

0x422370 CMP	W14, W11

0x422374 CSINC	W16, WZR, WZR, #11

0x422378 SUB	W17, WZR, W13

0x42237c CSINC	W14, W15, WZR, #10

0x422380 CMP	W12, #0

0x422384 CSEL	W15, WZR, W16, #0

0x422388 CNTD	X16, ALL

0x42238c AND	W17, W12, W17

0x422390 B	4223ac

0x422394 HINT	#0

0x422398 HINT	#0

0x42239c HINT	#0

(228) 0x4223a0 CMP	W9, W8

(228) 0x4223a4 ADD	W9, W9, #1

(228) 0x4223a8 B.EQ	422440

(228) 0x4223ac CBZ	W15, 4223a0

(228) 0x4223b0 LDR	X0, [SP, #136]

(228) 0x4223b4 ADD	W18, W10, W9

(228) 0x4223b8 SBFM	X18, X18, #0, #31

(228) 0x4223bc SUB	X18, X18, X22

(228) 0x4223c0 LDR	D0, [X0]

(228) 0x4223c4 LDP	X0, X1, [SP, #224]

(228) 0x4223c8 MUL	X18, X18, X1

(228) 0x4223cc ADD	X18, X0, X18,LSL #3

(228) 0x4223d0 ORR	W0, WZR, WZR

(228) 0x4223d4 TBNZ	W14, #0, 422420

(228) 0x4223d8 DUP	Z1.D, Z0.D[0]

(228) 0x4223dc HINT	#0

  (230) 0x4223e0 ADD	W1, W11, W0

  (230) 0x4223e4 ADD	W0, W0, W13

  (230) 0x4223e8 SBFM	X1, X1, #0, #31

  (230) 0x4223ec CMP	W17, W0

  (230) 0x4223f0 SUB	X1, X1, X19

  (230) 0x4223f4 ADD	X2, X18, X1,LSL #3

  (230) 0x4223f8 ST1D	{Z1.D}, P0, [X18, X1,LSL #3]

  (230) 0x4223fc ST1D	{Z1.D}, P0, [X2, X16,LSL #3]

  (230) 0x422400 B.NE	4223e0

(228) 0x422404 CMP	W12, W17

(228) 0x422408 ORR	W0, WZR, W17

(228) 0x42240c B.EQ	4223a0

(228) 0x422410 HINT	#0

(228) 0x422414 HINT	#0

(228) 0x422418 HINT	#0

(228) 0x42241c HINT	#0

  (229) 0x422420 ADD	W1, W11, W0

  (229) 0x422424 ADD	W0, W0, #1

  (229) 0x422428 SBFM	X1, X1, #0, #31

  (229) 0x42242c CMP	W12, W0

  (229) 0x422430 SUB	X1, X1, X19

  (229) 0x422434 STR	D0, [X18, X1,LSL #3]

  (229) 0x422438 B.HI	422420

(228) 0x42243c B	4223a0

0x422440 ADRP	X0,

0x422444 ADD	X0, X0, #3136

0x422448 ORR	W1, WZR, W26

0x42244c BL	410380

0x422450 ADRP	X0,

0x422454 ADD	X0, X0, #3160

0x422458 ORR	W1, WZR, W26

0x42245c BL	410050

0x422460 LDR	X8, [SP, #104]

0x422464 ADRP	X0,

0x422468 ADD	X0, X0, #3184

0x42246c ADD	X3, SP, #348

0x422470 ADD	X4, SP, #344

0x422474 ORR	W1, WZR, W26

0x422478 LDR	W8, [X8]

0x42247c ADD	X5, SP, #340

0x422480 ADD	X6, SP, #336

0x422484 MOVZ	W2, #34

0x422488 MOVZ	W7, #1

0x42248c SUB	W21, W8, #2

0x422490 LDR	X8, [SP, #96]

0x422494 LDR	W8, [X8]

0x422498 STR	WZR, [SP, #344]

0x42249c STR	W20, [SP, #336]

0x4224a0 STR	WZR, [SP]

0x4224a4 ADD	W8, W8, #2

0x4224a8 SUBS	W8, W8, W21

0x4224ac CSINV	W8, W8, WZR, #10

0x4224b0 STR	W8, [SP, #340]

0x4224b4 BL	410090

0x4224b8 LDR	W10, [SP, #344]

0x4224bc LDR	W8, [SP, #340]

0x4224c0 SUB	W8, W8, W10

0x4224c4 CMN	W8, #1

0x4224c8 B.EQ	4225c0

0x4224cc LDP	X13, X11, [SP, #48]

0x4224d0 PTRUE	P0.D, ALL

0x4224d4 ADD	W10, W10, W21

0x4224d8 ORR	W9, WZR, WZR

0x4224dc LDR	W12, [X11]

0x4224e0 LDR	W13, [X13]

0x4224e4 SUB	W11, W12, #2

0x4224e8 ADD	W14, W13, #2

0x4224ec SUB	W12, W13, W12

0x4224f0 CNTW	X13, ALL

0x4224f4 ADD	W12, W12, #5

0x4224f8 CMP	W12, W13

0x4224fc CSINC	W15, WZR, WZR, #2

0x422500 CMP	W14, W11

0x422504 CSINC	W16, WZR, WZR, #11

0x422508 SUB	W17, WZR, W13

0x42250c CSINC	W14, W15, WZR, #10

0x422510 CMP	W12, #0

0x422514 CSEL	W15, WZR, W16, #0

0x422518 CNTD	X16, ALL

0x42251c AND	W17, W12, W17

0x422520 B	422530

(225) 0x422524 CMP	W9, W8

(225) 0x422528 ADD	W9, W9, #1

(225) 0x42252c B.EQ	4225c0

(225) 0x422530 CBZ	W15, 422524

(225) 0x422534 LDR	X0, [SP, #128]

(225) 0x422538 ADD	W18, W10, W9

(225) 0x42253c SBFM	X18, X18, #0, #31

(225) 0x422540 SUB	X18, X18, X22

(225) 0x422544 LDR	D0, [X0]

(225) 0x422548 LDR	X0, [SP, #232]

(225) 0x42254c MUL	X18, X18, X0

(225) 0x422550 LDR	X0, [SP, #216]

(225) 0x422554 ADD	X18, X0, X18,LSL #3

(225) 0x422558 ORR	W0, WZR, WZR

(225) 0x42255c TBNZ	W14, #0, 4225a0

(225) 0x422560 DUP	Z1.D, Z0.D[0]

  (227) 0x422564 ADD	W1, W11, W0

  (227) 0x422568 ADD	W0, W0, W13

  (227) 0x42256c SBFM	X1, X1, #0, #31

  (227) 0x422570 CMP	W17, W0

  (227) 0x422574 SUB	X1, X1, X19

  (227) 0x422578 ADD	X2, X18, X1,LSL #3

  (227) 0x42257c ST1D	{Z1.D}, P0, [X18, X1,LSL #3]

  (227) 0x422580 ST1D	{Z1.D}, P0, [X2, X16,LSL #3]

  (227) 0x422584 B.NE	422564

(225) 0x422588 CMP	W12, W17

(225) 0x42258c ORR	W0, WZR, W17

(225) 0x422590 B.EQ	422524

(225) 0x422594 HINT	#0

(225) 0x422598 HINT	#0

(225) 0x42259c HINT	#0

  (226) 0x4225a0 ADD	W1, W11, W0

  (226) 0x4225a4 ADD	W0, W0, #1

  (226) 0x4225a8 SBFM	X1, X1, #0, #31

  (226) 0x4225ac CMP	W12, W0

  (226) 0x4225b0 SUB	X1, X1, X19

  (226) 0x4225b4 STR	D0, [X18, X1,LSL #3]

  (226) 0x4225b8 B.HI	4225a0

(225) 0x4225bc B	422524

0x4225c0 ADRP	X0,

0x4225c4 ADD	X0, X0, #3184

0x4225c8 ORR	W1, WZR, W26

0x4225cc BL	410380

0x4225d0 ADRP	X0,

0x4225d4 ADD	X0, X0, #3208

0x4225d8 ORR	W1, WZR, W26

0x4225dc BL	410050

0x4225e0 LDR	X8, [SP, #104]

0x4225e4 MOVZ	W20, #1

0x4225e8 ADRP	X0,

0x4225ec ADD	X0, X0, #3232

0x4225f0 ADD	X3, SP, #364

0x4225f4 ORR	W1, WZR, W26

0x4225f8 LDR	W8, [X8]

0x4225fc ADD	X4, SP, #360

0x422600 ADD	X5, SP, #356

0x422604 ADD	X6, SP, #352

0x422608 MOVZ	W2, #34

0x42260c MOVZ	W7, #1

0x422610 SUB	W21, W8, #2

0x422614 LDR	X8, [SP, #96]

0x422618 LDR	W8, [X8]

0x42261c ADD	W8, W8, #2

0x422620 STR	WZR, [SP, #360]

0x422624 STR	W20, [SP, #352]

0x422628 STR	WZR, [SP]

0x42262c SUBS	W8, W8, W21

0x422630 CSINV	W8, W8, WZR, #10

0x422634 STR	W8, [SP, #356]

0x422638 BL	410090

0x42263c LDR	W10, [SP, #360]

0x422640 LDR	W8, [SP, #356]

0x422644 SUB	W8, W8, W10

0x422648 CMN	W8, #1

0x42264c B.EQ	422740

0x422650 LDP	X13, X11, [SP, #48]

0x422654 PTRUE	P0.D, ALL

0x422658 ADD	W10, W10, W21

0x42265c ORR	W9, WZR, WZR

0x422660 LDR	W12, [X11]

0x422664 LDR	W13, [X13]

0x422668 SUB	W11, W12, #2

0x42266c ADD	W14, W13, #2

0x422670 SUB	W12, W13, W12

0x422674 CNTW	X13, ALL

0x422678 ADD	W12, W12, #5

0x42267c CMP	W12, W13

0x422680 CSINC	W15, WZR, WZR, #2

0x422684 CMP	W14, W11

0x422688 CSINC	W16, WZR, WZR, #11

0x42268c SUB	W17, WZR, W13

0x422690 CSINC	W14, W15, WZR, #10

0x422694 CMP	W12, #0

0x422698 CSEL	W15, WZR, W16, #0

0x42269c CNTD	X16, ALL

0x4226a0 AND	W17, W12, W17

0x4226a4 B	4226b4

(222) 0x4226a8 CMP	W9, W8

(222) 0x4226ac ADD	W9, W9, #1

(222) 0x4226b0 B.EQ	422740

(222) 0x4226b4 CBZ	W15, 4226a8

(222) 0x4226b8 LDR	X0, [SP, #120]

(222) 0x4226bc ADD	W18, W10, W9

(222) 0x4226c0 SBFM	X18, X18, #0, #31

(222) 0x4226c4 SUB	X18, X18, X22

(222) 0x4226c8 LDR	D0, [X0]

(222) 0x4226cc LDR	X0, [SP, #240]

(222) 0x4226d0 MUL	X18, X18, X0

(222) 0x4226d4 ORR	W0, WZR, WZR

(222) 0x4226d8 ADD	X18, X28, X18,LSL #3

(222) 0x4226dc TBNZ	W14, #0, 422720

(222) 0x4226e0 DUP	Z1.D, Z0.D[0]

  (224) 0x4226e4 ADD	W1, W11, W0

  (224) 0x4226e8 ADD	W0, W0, W13

  (224) 0x4226ec SBFM	X1, X1, #0, #31

  (224) 0x4226f0 CMP	W17, W0

  (224) 0x4226f4 SUB	X1, X1, X19

  (224) 0x4226f8 ADD	X2, X18, X1,LSL #3

  (224) 0x4226fc ST1D	{Z1.D}, P0, [X18, X1,LSL #3]

  (224) 0x422700 ST1D	{Z1.D}, P0, [X2, X16,LSL #3]

  (224) 0x422704 B.NE	4226e4

(222) 0x422708 CMP	W12, W17

(222) 0x42270c ORR	W0, WZR, W17

(222) 0x422710 B.EQ	4226a8

(222) 0x422714 HINT	#0

(222) 0x422718 HINT	#0

(222) 0x42271c HINT	#0

  (223) 0x422720 ADD	W1, W11, W0

  (223) 0x422724 ADD	W0, W0, #1

  (223) 0x422728 SBFM	X1, X1, #0, #31

  (223) 0x42272c CMP	W12, W0

  (223) 0x422730 SUB	X1, X1, X19

  (223) 0x422734 STR	D0, [X18, X1,LSL #3]

  (223) 0x422738 B.HI	422720

(222) 0x42273c B	4226a8

0x422740 ADRP	X0,

0x422744 ADD	X0, X0, #3232

0x422748 ORR	W1, WZR, W26

0x42274c BL	410380

0x422750 ADRP	X0,

0x422754 ADD	X0, X0, #3256

0x422758 ORR	W1, WZR, W26

0x42275c BL	410050

0x422760 LDR	X8, [SP, #104]

0x422764 ADRP	X0,

0x422768 ADD	X0, X0, #3280

0x42276c ADD	X3, SP, #380

0x422770 ADD	X4, SP, #376

0x422774 ORR	W1, WZR, W26

0x422778 LDR	W8, [X8]

0x42277c ADD	X5, SP, #372

0x422780 ADD	X6, SP, #368

0x422784 MOVZ	W2, #34

0x422788 MOVZ	W7, #1

0x42278c SUB	W21, W8, #2

0x422790 LDR	X8, [SP, #96]

0x422794 LDR	W8, [X8]

0x422798 STR	WZR, [SP, #376]

0x42279c STR	W20, [SP, #368]

0x4227a0 STR	WZR, [SP]

0x4227a4 ADD	W8, W8, #2

0x4227a8 SUBS	W8, W8, W21

0x4227ac CSINV	W8, W8, WZR, #10

0x4227b0 STR	W8, [SP, #372]

0x4227b4 BL	410090

0x4227b8 LDR	W10, [SP, #376]

0x4227bc LDR	W8, [SP, #372]

0x4227c0 SUB	W8, W8, W10

0x4227c4 CMN	W8, #1

0x4227c8 B.EQ	4228c0

0x4227cc LDP	X13, X11, [SP, #48]

0x4227d0 PTRUE	P0.D, ALL

0x4227d4 ADD	W10, W10, W21

0x4227d8 ORR	W9, WZR, WZR

0x4227dc LDR	W12, [X11]

0x4227e0 LDR	W13, [X13]

0x4227e4 SUB	W11, W12, #2

0x4227e8 ADD	W14, W13, #2

0x4227ec SUB	W12, W13, W12

0x4227f0 CNTW	X13, ALL

0x4227f4 ADD	W12, W12, #5

0x4227f8 CMP	W12, W13

0x4227fc CSINC	W15, WZR, WZR, #2

0x422800 CMP	W14, W11

0x422804 CSINC	W16, WZR, WZR, #11

0x422808 SUB	W17, WZR, W13

0x42280c CSINC	W14, W15, WZR, #10

0x422810 CMP	W12, #0

0x422814 CSEL	W15, WZR, W16, #0

0x422818 CNTD	X16, ALL

0x42281c AND	W17, W12, W17

0x422820 B	422830

(219) 0x422824 CMP	W9, W8

(219) 0x422828 ADD	W9, W9, #1

(219) 0x42282c B.EQ	4228c0

(219) 0x422830 CBZ	W15, 422824

(219) 0x422834 LDR	X0, [SP, #112]

(219) 0x422838 ADD	W18, W10, W9

(219) 0x42283c SBFM	X18, X18, #0, #31

(219) 0x422840 SUB	X18, X18, X22

(219) 0x422844 LDR	D0, [X0]

(219) 0x422848 LDR	X0, [SP, #240]

(219) 0x42284c MUL	X18, X18, X0

(219) 0x422850 ORR	W0, WZR, WZR

(219) 0x422854 ADD	X18, X24, X18,LSL #3

(219) 0x422858 TBNZ	W14, #0, 4228a0

(219) 0x42285c DUP	Z1.D, Z0.D[0]

  (221) 0x422860 ADD	W1, W11, W0

  (221) 0x422864 ADD	W0, W0, W13

  (221) 0x422868 SBFM	X1, X1, #0, #31

  (221) 0x42286c CMP	W17, W0

  (221) 0x422870 SUB	X1, X1, X19

  (221) 0x422874 ADD	X2, X18, X1,LSL #3

  (221) 0x422878 ST1D	{Z1.D}, P0, [X18, X1,LSL #3]

  (221) 0x42287c ST1D	{Z1.D}, P0, [X2, X16,LSL #3]

  (221) 0x422880 B.NE	422860

(219) 0x422884 CMP	W12, W17

(219) 0x422888 ORR	W0, WZR, W17

(219) 0x42288c B.EQ	422824

(219) 0x422890 HINT	#0

(219) 0x422894 HINT	#0

(219) 0x422898 HINT	#0

(219) 0x42289c HINT	#0

  (220) 0x4228a0 ADD	W1, W11, W0

  (220) 0x4228a4 ADD	W0, W0, #1

  (220) 0x4228a8 SBFM	X1, X1, #0, #31

  (220) 0x4228ac CMP	W12, W0

  (220) 0x4228b0 SUB	X1, X1, X19

  (220) 0x4228b4 STR	D0, [X18, X1,LSL #3]

  (220) 0x4228b8 B.HI	4228a0

(219) 0x4228bc B	422824

0x4228c0 ADRP	X0,

0x4228c4 ADD	X0, X0, #3280

0x4228c8 STR	X22, [SP, #152]

0x4228cc ORR	W1, WZR, W26

0x4228d0 BL	410380

0x4228d4 ADRP	X0,

0x4228d8 ADD	X0, X0, #3304

0x4228dc ORR	W1, WZR, W26

0x4228e0 BL	410050

0x4228e4 LDR	X8, [SP, #304]

0x4228e8 LDR	W8, [X8]

0x4228ec CMP	W8, #2

0x4228f0 STR	X8, [SP, #72]

0x4228f4 B.LT	422e80

0x4228f8 DUP	Z0.D, X19

0x4228fc MOVZ	W8, #2

0x422900 ADRP	X0,

0x422904 ADD	X0, X0, #3328

0x422908 STR	W26, [SP, #68]

0x42290c STR	Z0, [X29, #511, MUL VL]

0x422910 CNTD	X21, ALL

0x422914 DUP	Z0.D, X21

0x422918 STR	Z0, [X29, #510, MUL VL]

0x42291c B	422960

    (215) 0x422920 LDR	W26, [SP, #68]

    (215) 0x422924 ADRP	X20,

    (215) 0x422928 ADD	X20, X20, #3328

    (215) 0x42292c ORR	X0, XZR, X20

    (215) 0x422930 ORR	W1, WZR, W26

    (215) 0x422934 BL	410380

    (215) 0x422938 ADRP	X0,

    (215) 0x42293c ADD	X0, X0, #3352

    (215) 0x422940 ORR	W1, WZR, W26

    (215) 0x422944 BL	410050

    (215) 0x422948 LDR	X8, [SP, #72]

    (215) 0x42294c LDR	X9, [SP, #144]

    (215) 0x422950 ORR	X0, XZR, X20

    (215) 0x422954 CMP	X9, X8

    (215) 0x422958 ADD	X8, X9, #1

    (215) 0x42295c B.EQ	422e80

    (215) 0x422960 LDR	X10, [SP, #88]

    (215) 0x422964 SUB	X11, X8, #1

    (215) 0x422968 STR	X8, [SP, #144]

    (215) 0x42296c LDP	X9, X8, [SP, #96]

    (215) 0x422970 ADD	X3, SP, #396

    (215) 0x422974 ADD	X4, SP, #392

    (215) 0x422978 STR	X11, [SP, #248]

    (215) 0x42297c ADD	X5, SP, #388

    (215) 0x422980 ADD	X6, SP, #384

    (215) 0x422984 MOVZ	W2, #34

    (215) 0x422988 MOVZ	W7, #1

    (215) 0x42298c ORR	W1, WZR, W26

    (215) 0x422990 ADD	X12, X10, X11,LSL #3

    (215) 0x422994 LDR	X10, [SP, #80]

    (215) 0x422998 LDR	W8, [X8]

    (215) 0x42299c LDR	W9, [X9]

    (215) 0x4229a0 STR	WZR, [SP, #392]

    (215) 0x4229a4 LDR	D0, [X12]

    (215) 0x4229a8 ORR	X25, XZR, X12

    (215) 0x4229ac ADD	X10, X10, X11,LSL #3

    (215) 0x4229b0 LDR	X11, [SP, #312]

    (215) 0x4229b4 SUB	W20, W8, #2

    (215) 0x4229b8 ADD	W8, W9, #2

    (215) 0x4229bc SUBS	W8, W8, W20

    (215) 0x4229c0 ORR	X22, XZR, X10

    (215) 0x4229c4 CSINV	W8, W8, WZR, #10

    (215) 0x4229c8 STR	W8, [SP, #388]

    (215) 0x4229cc MOVZ	W8, #1

    (215) 0x4229d0 STR	D0, [X11]

    (215) 0x4229d4 LDR	D0, [X10]

    (215) 0x4229d8 STR	W8, [SP, #384]

    (215) 0x4229dc STR	D0, [X27]

    (215) 0x4229e0 STR	WZR, [SP]

    (215) 0x4229e4 BL	410090

    (215) 0x4229e8 LDR	W8, [SP, #392]

    (215) 0x4229ec LDR	W9, [SP, #388]

    (215) 0x4229f0 LDR	Z18, [X29, #511, MUL VL]

    (215) 0x4229f4 INDEX	Z20.D, #0, #1

    (215) 0x4229f8 LDR	Z19, [X29, #510, MUL VL]

    (215) 0x4229fc LDR	X1, [SP, #264]

    (215) 0x422a00 MOVI	V21.2D, #0

    (215) 0x422a04 SUB	W9, W9, W8

    (215) 0x422a08 CMN	W9, #1

    (215) 0x422a0c STR	W9, [SP, #260]

    (215) 0x422a10 B.EQ	422920

  (216) 0x422a14 ADD	W18, W8, W20

  (216) 0x422a18 LDP	X10, X8, [SP, #48]

  (216) 0x422a1c LDR	X14, [SP, #248]

  (216) 0x422a20 ORR	W9, WZR, WZR

  (216) 0x422a24 ORR	W4, WZR, W18

  (216) 0x422a28 STR	W18, [SP, #212]

  (216) 0x422a2c LDR	W8, [X8]

  (216) 0x422a30 LDR	W10, [X10]

  (216) 0x422a34 SUB	W2, W8, #2

  (216) 0x422a38 ADD	W11, W10, #2

  (216) 0x422a3c SUB	W12, W10, W8

  (216) 0x422a40 SUB	W8, W8, #1

  (216) 0x422a44 ADD	W10, W10, #3

  (216) 0x422a48 CMP	W11, W2

  (216) 0x422a4c CSINC	W11, WZR, WZR, #11

  (216) 0x422a50 ADD	W12, W12, #5

  (216) 0x422a54 DUP	Z0.D, X2

  (216) 0x422a58 STR	X2, [SP, #200]

  (216) 0x422a5c CSINC	W13, WZR, WZR, #10

  (216) 0x422a60 CMP	W12, #0

  (216) 0x422a64 CSEL	W11, WZR, W11, #0

  (216) 0x422a68 CMP	W10, W8

  (216) 0x422a6c STR	W11, [SP, #256]

  (216) 0x422a70 LDR	X11, [SP, #136]

  (216) 0x422a74 CSINC	W8, W13, WZR, #10

  (216) 0x422a78 STR	W8, [SP, #196]

  (216) 0x422a7c SUBS	W8, W12, W21

  (216) 0x422a80 CSEL	W3, WZR, W8, #3

  (216) 0x422a84 WHILELO	P8.D, WZR, W12

  (216) 0x422a88 ADD	X11, X11, X14,LSL #3

  (216) 0x422a8c STR	X11, [SP, #304]

  (216) 0x422a90 LDR	X11, [SP, #128]

  (216) 0x422a94 ADD	X15, X11, X14,LSL #3

  (216) 0x422a98 LDR	X11, [SP, #120]

  (216) 0x422a9c ADD	X16, X11, X14,LSL #3

  (216) 0x422aa0 LDR	X11, [SP, #112]

  (216) 0x422aa4 ADD	X17, X11, X14,LSL #3

  (216) 0x422aa8 LDR	X11, [SP, #40]

  (216) 0x422aac ADD	X11, X11, X14,LSL #3

  (216) 0x422ab0 STR	X11, [SP, #296]

  (216) 0x422ab4 LDR	X11, [SP, #32]

  (216) 0x422ab8 ADD	X0, X11, X14,LSL #3

  (216) 0x422abc LDR	X11, [SP, #24]

  (216) 0x422ac0 ADD	X11, X11, X14,LSL #3

  (216) 0x422ac4 STR	X11, [SP, #288]

  (216) 0x422ac8 B	422ae0

  (216) 0x422acc LDR	W8, [SP, #260]

  (216) 0x422ad0 ADD	W4, W4, #1

  (216) 0x422ad4 CMP	W9, W8

  (216) 0x422ad8 ADD	W9, W9, #1

  (216) 0x422adc B.EQ	422920

  (216) 0x422ae0 LDR	W8, [SP, #256]

  (216) 0x422ae4 CBZ	W8, 422acc

  (216) 0x422ae8 LDR	W8, [SP, #212]

  (216) 0x422aec LDR	X11, [SP, #248]

  (216) 0x422af0 LDR	X20, [SP, #152]

  (216) 0x422af4 SBFM	X13, X4, #0, #31

  (216) 0x422af8 ADD	W10, W8, W9

  (216) 0x422afc LDR	X8, [SP, #184]

  (216) 0x422b00 LDP	X6, X18, [SP, #224]

  (216) 0x422b04 LDR	X7, [SP, #216]

  (216) 0x422b08 LDR	W2, [X8, X11,LSL #2]

  (216) 0x422b0c SBFM	X11, X10, #0, #31

  (216) 0x422b10 LDP	X14, X8, [SP, #168]

  (216) 0x422b14 ADD	W10, W10, #1

  (216) 0x422b18 SUB	X11, X11, X20

  (216) 0x422b1c SBFM	X10, X10, #0, #31

  (216) 0x422b20 MUL	X18, X11, X18

  (216) 0x422b24 SUB	X10, X10, X20

  (216) 0x422b28 ADD	X6, X6, X18,LSL #3

  (216) 0x422b2c ADD	X7, X7, X18,LSL #3

  (216) 0x422b30 LDR	X18, [SP, #160]

  (216) 0x422b34 LDR	W8, [X8]

  (216) 0x422b38 ADD	X5, X14, X11,LSL #3

  (216) 0x422b3c ADD	X10, X14, X10,LSL #3

  (216) 0x422b40 ADD	X30, X18, X11,LSL #3

  (216) 0x422b44 LDR	W11, [SP, #196]

  (216) 0x422b48 CBZ	W11, 422cc0

  (216) 0x422b4c LDR	X14, [SP, #240]

  (216) 0x422b50 SUB	X13, X13, X20

  (216) 0x422b54 ORR	W11, WZR, WZR

  (216) 0x422b58 LDR	X18, [SP, #200]

  (216) 0x422b5c MUL	X13, X13, X14

  (216) 0x422b60 ADD	X26, X14, X13

  (216) 0x422b64 B	422bd0

    (218) 0x422b68 LDR	X14, [SP, #304]

    (218) 0x422b6c LDR	D2, [X15]

    (218) 0x422b70 SUB	X1, X20, X19

    (218) 0x422b74 LDR	D1, [X14]

    (218) 0x422b78 ADD	X14, X1, X13

    (218) 0x422b7c STR	D2, [X7, X18,LSL #3]

    (218) 0x422b80 LDR	D2, [X17]

    (218) 0x422b84 STR	D1, [X6, X18,LSL #3]

    (218) 0x422b88 LDR	D1, [X16]

    (218) 0x422b8c STR	D2, [X24, X14,LSL #3]

    (218) 0x422b90 STR	D1, [X28, X14,LSL #3]

    (218) 0x422b94 ADD	X14, X1, #1

    (218) 0x422b98 ADD	X18, X14, X13

    (218) 0x422b9c ADD	X14, X14, X26

    (218) 0x422ba0 STR	D1, [X28, X18,LSL #3]

    (218) 0x422ba4 STR	D2, [X24, X18,LSL #3]

    (218) 0x422ba8 ADD	X18, X1, X26

    (218) 0x422bac LDR	X1, [SP, #264]

    (218) 0x422bb0 STR	D1, [X28, X18,LSL #3]

    (218) 0x422bb4 STR	D2, [X24, X18,LSL #3]

    (218) 0x422bb8 STR	D1, [X28, X14,LSL #3]

    (218) 0x422bbc STR	D2, [X24, X14,LSL #3]

    (218) 0x422bc0 ADD	W11, W11, #1

    (218) 0x422bc4 ADD	W18, W20, #1

    (218) 0x422bc8 CMP	W12, W11

    (218) 0x422bcc B.LS	422acc

    (218) 0x422bd0 SBFM	X20, X18, #0, #31

    (218) 0x422bd4 CMP	W2, W8

    (218) 0x422bd8 B.NE	422c2c

    (218) 0x422bdc ADD	W14, W20, #1

    (218) 0x422be0 LDR	D2, [X25]

    (218) 0x422be4 SUB	X18, X20, X19

    (218) 0x422be8 LDR	D4, [X0]

    (218) 0x422bec SBFM	X14, X14, #0, #31

    (218) 0x422bf0 LDR	D3, [X23, X18,LSL #3]

    (218) 0x422bf4 SUB	X14, X14, X19

    (218) 0x422bf8 LDR	D1, [X23, X14,LSL #3]

    (218) 0x422bfc FCMP	D1, D2

    (218) 0x422c00 FCCMP	D3, D4, #0, #10

    (218) 0x422c04 B.GE	422bc0

    (218) 0x422c08 LDR	X14, [SP, #288]

    (218) 0x422c0c LDR	D1, [X10]

    (218) 0x422c10 LDR	D2, [X22]

    (218) 0x422c14 FCMP	D1, D2

    (218) 0x422c18 LDR	D3, [X5]

    (218) 0x422c1c LDR	D4, [X14]

    (218) 0x422c20 FCCMP	D3, D4, #0, #10

    (218) 0x422c24 B.LT	422b68

    (218) 0x422c28 B	422bc0

    (218) 0x422c2c LDR	W18, [X1]

    (218) 0x422c30 CMP	W2, W18

    (218) 0x422c34 B.NE	422c80

    (218) 0x422c38 LDR	X14, [SP, #272]

    (218) 0x422c3c SUB	X18, X20, X19

    (218) 0x422c40 LDR	D3, [X27]

    (218) 0x422c44 LDR	D1, [X14, X18,LSL #3]

    (218) 0x422c48 LDR	X14, [SP, #312]

    (218) 0x422c4c LDR	D2, [X14]

    (218) 0x422c50 LDR	X14, [SP, #296]

    (218) 0x422c54 FSUB	D1, D1, S2

    (218) 0x422c58 LDR	D2, [X30]

    (218) 0x422c5c FMUL	D1, D1, D1

    (218) 0x422c60 FSUB	D2, D2, S3

    (218) 0x422c64 FMADD	D1, D2, D2, D1

    (218) 0x422c68 LDR	D2, [X14]

    (218) 0x422c6c FSQRT	D1, D1

    (218) 0x422c70 FCMP	D1, D2

    (218) 0x422c74 B.LE	422b68

    (218) 0x422c78 B	422bc0

0x422c7c HINT	#0

    (218) 0x422c80 LDR	X14, [SP, #280]

    (218) 0x422c84 LDR	W18, [X14]

    (218) 0x422c88 CMP	W2, W18

    (218) 0x422c8c B.NE	422bc0

    (218) 0x422c90 LDR	X14, [SP, #312]

    (218) 0x422c94 SUB	X18, X20, X19

    (218) 0x422c98 LDR	D3, [X5]

    (218) 0x422c9c LDR	D4, [X27]

    (218) 0x422ca0 LDR	D1, [X23, X18,LSL #3]

    (218) 0x422ca4 LDR	D2, [X14]

    (218) 0x422ca8 FCMP	D1, D2

    (218) 0x422cac FCCMP	D3, D4, #0, #0

    (218) 0x422cb0 B.EQ	422b68

    (218) 0x422cb4 B	422bc0

0x422cb8 HINT	#0

0x422cbc HINT	#0

(217) 0x422cc0 CMP	W2, W8

(217) 0x422cc4 CSINC	W8, WZR, WZR, #0

(217) 0x422cc8 DUP	Z1.D, X2

(217) 0x422ccc ORR	Z2.D, Z20.D, Z20.D

(217) 0x422cd0 LDR	X2, [SP, #200]

(217) 0x422cd4 CSINC	W11, WZR, WZR, #1

(217) 0x422cd8 SBFM	X8, X8, #0, #0

(217) 0x422cdc ORR	P3.B, P8/Z, P8.B, P8.B

(217) 0x422ce0 SBFM	X11, X11, #0, #0

(217) 0x422ce4 WHILELO	P11.D, XZR, X8

(217) 0x422ce8 SUB	X8, XZR, X21

(217) 0x422cec AND	Z1.D, Z1.D, #0x0

(217) 0x422cf0 WHILELO	P9.D, XZR, X11

(217) 0x422cf4 SUB	X11, X13, X20

(217) 0x422cf8 LDR	X13, [SP, #240]

(217) 0x422cfc MUL	X11, X11, X13

(217) 0x422d00 ADD	X13, X13, X11

  (214) 0x422d04 AND	P5.B, P3/Z, P3.B, P11.B

  (214) 0x422d08 ADD	Z4.D, Z2.D, Z0.D

  (214) 0x422d0c LDR	X14, [SP, #280]

  (214) 0x422d10 LDR	X26, [SP, #312]

  (214) 0x422d14 ADD	W8, W8, W21

  (214) 0x422d18 ADD	Z2.D, Z2.D, Z19.D

  (214) 0x422d1c FMOV	W20, S4

  (214) 0x422d20 PTRUE	P2.D, ALL

  (214) 0x422d24 LD1W	{Z3.D}, P5/Z, [X1, Z21.D,LSL #2]

  (214) 0x422d28 MOVPRFX	Z5, Z4

  (214) 0x422d2c SXTW	Z5.D, P2/M, Z4.D

  (214) 0x422d30 AND	P0.B, P3/Z, P3.B, P9.B

  (214) 0x422d34 ADD	W20, W20, #1

  (214) 0x422d38 SUB	Z5.D, Z5.D, Z18.D

  (214) 0x422d3c LD1D	{Z6.D}, P0/Z, [X25, Z21.D,LSL #3]

  (214) 0x422d40 LD1D	{Z7.D}, P0/Z, [X0, Z21.D,LSL #3]

  (214) 0x422d44 SBFM	X20, X20, #0, #31

  (214) 0x422d48 SUB	X20, X20, X19

  (214) 0x422d4c FMOV	X18, D5

  (214) 0x422d50 LD1D	{Z4.D}, P0/Z, [X23, X20,LSL #3]

  (214) 0x422d54 LD1D	{Z17.D}, P0/Z, [X23, X18,LSL #3]

  (214) 0x422d58 AND	Z3.D, Z3.D, #0x0

  (214) 0x422d5c CMPEQ	P4.D, P2/Z, Z1.D, Z3.D

  (214) 0x422d60 CMPNE	P7.D, P2/Z, Z1.D, Z3.D

  (214) 0x422d64 FCMGE	P1.D, P2/Z, Z4.D, Z6.D

  (214) 0x422d68 FCMGT	P1.D, P1/Z, Z7.D, Z17.D

  (214) 0x422d6c AND	P6.B, P5/Z, P5.B, P4.B

  (214) 0x422d70 AND	P5.B, P5/Z, P5.B, P7.B

  (214) 0x422d74 AND	P4.B, P11/Z, P11.B, P4.B

  (214) 0x422d78 AND	P0.B, P0/Z, P0.B, P1.B

  (214) 0x422d7c LD1W	{Z3.D}, P5/Z, [X14, Z21.D,LSL #2]

  (214) 0x422d80 LDR	X14, [SP, #272]

  (214) 0x422d84 AND	P1.B, P9/Z, P9.B, P1.B

  (214) 0x422d88 LD1D	{Z7.D}, P6/Z, [X14, X18,LSL #3]

  (214) 0x422d8c LDR	X14, [SP, #296]

  (214) 0x422d90 LD1D	{Z16.D}, P6/Z, [X26, Z21.D,LSL #3]

  (214) 0x422d94 LD1D	{Z4.D}, P6/Z, [X30, Z21.D,LSL #3]

  (214) 0x422d98 LD1D	{Z6.D}, P6/Z, [X27, Z21.D,LSL #3]

  (214) 0x422d9c FSUB	Z4.D, Z4.D, Z6.D

  (214) 0x422da0 AND	Z3.D, Z3.D, #0x0

  (214) 0x422da4 FSUB	Z7.D, Z7.D, Z16.D

  (214) 0x422da8 FMUL	Z6.D, Z7.D, Z7.D

  (214) 0x422dac LD1D	{Z16.D}, P0/Z, [X10, Z21.D,LSL #3]

  (214) 0x422db0 CMPEQ	P10.D, P2/Z, Z1.D, Z3.D

  (214) 0x422db4 FMAD	Z4.D, P2/M, Z4.D, Z6.D

  (214) 0x422db8 FSQRT	Z4.D, P2/M, Z4.D

  (214) 0x422dbc LD1D	{Z6.D}, P0/Z, [X22, Z21.D,LSL #3]

  (214) 0x422dc0 LD1D	{Z3.D}, P6/Z, [X14, Z21.D,LSL #3]

  (214) 0x422dc4 LDR	X14, [SP, #288]

  (214) 0x422dc8 LD1D	{Z7.D}, P0/Z, [X14, Z21.D,LSL #3]

  (214) 0x422dcc LDR	X14, [SP, #304]

  (214) 0x422dd0 FCMGE	P6.D, P2/Z, Z16.D, Z6.D

  (214) 0x422dd4 LD1D	{Z6.D}, P0/Z, [X5, Z21.D,LSL #3]

  (214) 0x422dd8 AND	P0.B, P5/Z, P5.B, P10.B

  (214) 0x422ddc FCMGT	P5.D, P6/Z, Z7.D, Z6.D

  (214) 0x422de0 LD1D	{Z7.D}, P0/Z, [X23, X18,LSL #3]

  (214) 0x422de4 SBFM	X18, X2, #0, #31

  (214) 0x422de8 LD1D	{Z6.D}, P0/Z, [X26, Z21.D,LSL #3]

  (214) 0x422dec ADD	W2, W2, W21

  (214) 0x422df0 SUB	X18, X18, X19

  (214) 0x422df4 AND	P1.B, P1/Z, P1.B, P5.B

  (214) 0x422df8 ADD	X20, X18, X11

  (214) 0x422dfc FCMEQ	P6.D, P2/Z, Z7.D, Z6.D

  (214) 0x422e00 LD1D	{Z6.D}, P0/Z, [X5, Z21.D,LSL #3]

  (214) 0x422e04 LD1D	{Z7.D}, P0/Z, [X27, Z21.D,LSL #3]

  (214) 0x422e08 FCMGE	P0.D, P2/Z, Z3.D, Z4.D

  (214) 0x422e0c SEL	P0.B, P1, P1.B, P0.B

  (214) 0x422e10 SEL	P0.B, P4, P0.B, P1.B

  (214) 0x422e14 FCMEQ	P5.D, P6/Z, Z6.D, Z7.D

  (214) 0x422e18 AND	P6.B, P11/Z, P11.B, P7.B

  (214) 0x422e1c AND	P1.B, P6/Z, P6.B, P10.B

  (214) 0x422e20 SEL	P4.B, P0, P0.B, P5.B

  (214) 0x422e24 SEL	P0.B, P1, P4.B, P0.B

  (214) 0x422e28 AND	P0.B, P3/Z, P3.B, P0.B

  (214) 0x422e2c WHILELO	P3.D, W8, W3

  (214) 0x422e30 LD1D	{Z3.D}, P0/Z, [X14, Z21.D,LSL #3]

  (214) 0x422e34 ST1D	{Z3.D}, P0, [X6, Z5.D,LSL #3]

  (214) 0x422e38 LD1D	{Z3.D}, P0/Z, [X15, Z21.D,LSL #3]

  (214) 0x422e3c ST1D	{Z3.D}, P0, [X7, Z5.D,LSL #3]

  (214) 0x422e40 LD1D	{Z3.D}, P0/Z, [X16, Z21.D,LSL #3]

  (214) 0x422e44 LD1D	{Z4.D}, P0/Z, [X17, Z21.D,LSL #3]

  (214) 0x422e48 ST1D	{Z3.D}, P0, [X28, X20,LSL #3]

  (214) 0x422e4c ST1D	{Z4.D}, P0, [X24, X20,LSL #3]

  (214) 0x422e50 ADD	X20, X18, #1

  (214) 0x422e54 ADD	X18, X18, X13

  (214) 0x422e58 ADD	X26, X20, X11

  (214) 0x422e5c ADD	X20, X20, X13

  (214) 0x422e60 ST1D	{Z3.D}, P0, [X28, X26,LSL #3]

  (214) 0x422e64 ST1D	{Z4.D}, P0, [X24, X26,LSL #3]

  (214) 0x422e68 ST1D	{Z3.D}, P0, [X28, X18,LSL #3]

  (214) 0x422e6c ST1D	{Z4.D}, P0, [X24, X18,LSL #3]

  (214) 0x422e70 ST1D	{Z3.D}, P0, [X28, X20,LSL #3]

  (214) 0x422e74 ST1D	{Z4.D}, P0, [X24, X20,LSL #3]

  (214) 0x422e78 B.MI	422d04

(217) 0x422e7c B	422acc

0x422e80 ADDVL	SP, SP, #2

0x422e84 ADD	SP, SP, #400

0x422e88 LDP	X20, X19, [SP, #80]

0x422e8c LDP	X22, X21, [SP, #64]

0x422e90 LDP	X24, X23, [SP, #48]

0x422e94 LDP	X26, X25, [SP, #32]

0x422e98 LDP	X28, X27, [SP, #16]

0x422e9c LDP	X29, X30, [SP], #96

0x422ea0 RET

0x422ea4 HINT	#0

0x422ea8 HINT	#0

0x422eac HINT	#0

0x422eb0 HINT	#0

0x422eb4 HINT	#0

0x422eb8 HINT	#0

0x422ebc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.33+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.67+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:50	exec
○	start	start.f90:106	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run armclang_6

Source file and lines	generate_chunk_kernel.f90:30-30,generate_chunk_kernel.f90:86-131,generate_chunk_kernel.f90:142-144,generate_chunk_kernel.f90:154-155,generate_chunk_kernel.f90:167-167
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:30,86-131,142-144,154-155,167.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 46.75 to 8.00 cycles (5.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 46.75 to 23.50 cycles (1.99x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
4% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 13 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:125
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 75 bytes. The binary function is storing 115 bytes.

General properties

nb instructions	323
nb uops	310
loop length	1292
used w registers	18
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	70

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.75 cycles
front end	38.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	46.75	46.75	46.75	46.75	0.50	0.50	0.50	0.50	37.83	37.50	37.67	22.50	22.50
cycles	12.00	12.00	46.75	46.75	46.75	46.75	0.50	0.50	0.50	0.50	37.83	37.50	37.67	22.50	22.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.75
Dispatch	46.75
Overall L1	46.75

Vectorization ratios

all	1%
load	0%
store	4%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	40%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.75 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.46 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4221f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #62	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP X15, X14, [X2, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X13, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b220>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X11, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X9, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X13, X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W21, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X15, X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W12, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X14, X27, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR WZR, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W20, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W12, W12, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W12, W12, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W12, [SP, #324]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X14, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X14, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X14, X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X23, X14, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X28, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X24, [X2, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X15, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X13, X14, [X2, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X13, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X12, [X2, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X13, X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W26, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b2fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #332	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, SP, #328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X5, SP, #324	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [SP, #324]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 422440 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W12, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W12, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND W17, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 4223ac <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <48b440>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b450>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48b464>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #348	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, SP, #344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, SP, #340	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W20, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #340]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [SP, #340]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4225c0 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W12, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W12, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND W17, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 422530 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b5c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b5d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b5e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #364	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, SP, #360	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, SP, #356	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR WZR, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W20, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #356]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [SP, #356]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 422740 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W12, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W12, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND W17, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 4226b4 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b740>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b750>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48b764>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #380	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, SP, #376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, SP, #372	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W20, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #372]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [SP, #372]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4228c0 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W12, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W12, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND W17, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 422830 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b8c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X22, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b8d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 422e80 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0xc90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48b900>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W26, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR Z0, [X29, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X21, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z0.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X29, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 422960 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADDVL SP, SP, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run armclang_6

Source file and lines	generate_chunk_kernel.f90:30-30,generate_chunk_kernel.f90:86-131,generate_chunk_kernel.f90:142-144,generate_chunk_kernel.f90:154-155,generate_chunk_kernel.f90:167-167
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 46.75 to 8.00 cycles (5.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
4% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 13 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:125
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:94
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:102
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:110

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 75 bytes. The binary function is storing 115 bytes.

General properties

nb instructions	323
nb uops	310
loop length	1292
used w registers	18
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	70

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.75 cycles
front end	38.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	46.75	46.75	46.75	46.75	0.50	0.50	0.50	0.50	37.83	37.50	37.67	22.50	22.50
cycles	12.00	12.00	46.75	46.75	46.75	46.75	0.50	0.50	0.50	0.50	37.83	37.50	37.67	22.50	22.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.75
Dispatch	46.75
Overall L1	46.75

Vectorization ratios

all	1%
load	0%
store	4%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	40%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.75 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.46 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4221f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #62	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP X15, X14, [X2, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X13, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b220>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X11, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X9, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X13, X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W21, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X15, X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W12, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X14, X27, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR WZR, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W20, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W12, W12, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W12, W12, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W12, [SP, #324]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X14, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X14, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X14, X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X14, [X2, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X23, X14, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X28, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X24, [X2, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X2, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X15, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X13, X14, [X2, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X13, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X12, [X2, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X13, X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W26, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b2fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #332	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, SP, #328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X5, SP, #324	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [SP, #324]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 422440 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W12, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W12, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND W17, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 4223ac <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <48b440>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b450>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48b464>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #348	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, SP, #344	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, SP, #340	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W20, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #340]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [SP, #340]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4225c0 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W12, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W12, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND W17, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 422530 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b5c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b5d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <48b5e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #364	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, SP, #360	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, SP, #356	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR WZR, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W20, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUBS W8, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #356]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [SP, #356]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 422740 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W12, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W12, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND W17, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 4226b4 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b740>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b750>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <48b764>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #380	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, SP, #376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, SP, #372	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W21, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR WZR, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W20, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR WZR, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSINV W8, W8, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #372]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [SP, #372]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMN W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4228c0 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD W10, W10, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W14, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W12, W13, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W12, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W12, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W15, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSINC W16, WZR, WZR, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W17, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSINC W14, W15, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W15, WZR, W16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND W17, W12, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 422830 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b8c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3280	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X22, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410380 <@plt_start@+0x360>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <48b8d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 422e80 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0xc90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <48b900>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W26, [SP, #68]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR Z0, [X29, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X21, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z0.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X29, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 422960 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0x770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADDVL SP, SP, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par–	0.05	0.07
▼Loop 228 - - exec–	0.00	0.00
○Loop 229 - - exec	0.00	0.00
○Loop 230 - - exec	0.00	0.00
▼Loop 217 - - exec–	0.00	0.00
○Loop 214 - - exec	0.03	0.04
▼Loop 216 - - exec–	0.00	0.00
○Loop 215 - - exec	0.00	0.00
○Loop 218 - - exec	0.00	0.00
▼Loop 222 - - exec–	0.00	0.00
○Loop 223 - - exec	0.00	0.00
○Loop 224 - - exec	0.00	0.00
▼Loop 225 - - exec–	0.00	0.00
○Loop 226 - - exec	0.00	0.00
○Loop 227 - - exec	0.00	0.00
▼Loop 219 - - exec–	0.00	0.00
○Loop 221 - - exec	0.00	0.00
○Loop 220 - - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

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Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code