OV - exec - Loop 1061

	Loop Id: 1061	Module: exec	Source: viscosity_kernel.f90:54-89	Coverage: 2.43%

0x449aa0 ADD	W7, W5, #1

0x449aa4 SUB	W30, W5, #1

0x449aa8 SBFM	X10, X5, #0, #31

0x449aac ADD	W6, W6, W15

0x449ab0 ADD	W5, W5, W15

0x449ab4 SBFM	X14, X7, #0, #31

0x449ab8 SBFM	X30, X30, #0, #31

0x449abc SUB	X7, X10, X28

0x449ac0 LD1D	{Z16.D}, P2/Z, [X23, X7,LSL #3]    [3]

0x449ac4 SUB	X10, X14, X28

0x449ac8 SUB	X14, X30, X28

0x449acc ADD	X30, X7, X18

0x449ad0 LD1D	{Z21.D}, P2/Z, [X2, X7,LSL #3]    [7]

0x449ad4 LD1D	{Z22.D}, P2/Z, [X3, X7,LSL #3]    [8]

0x449ad8 LD1D	{Z17.D}, P2/Z, [X1, X10,LSL #3]    [5]

0x449adc LD1D	{Z18.D}, P2/Z, [X1, X14,LSL #3]    [5]

0x449ae0 LD1D	{Z19.D}, P2/Z, [X23, X10,LSL #3]    [3]

0x449ae4 ADD	X14, X7, X17

0x449ae8 ADD	X19, X10, X18

0x449aec ADD	X10, X10, X17

0x449af0 LD1D	{Z24.D}, P2/Z, [X21, X30,LSL #3]    [1]

0x449af4 LD1D	{Z20.D}, P2/Z, [X22, X14,LSL #3]    [2]

0x449af8 LD1D	{Z23.D}, P2/Z, [X21, X14,LSL #3]    [1]

0x449afc LD1D	{Z25.D}, P2/Z, [X21, X10,LSL #3]    [1]

0x449b00 FSUB	Z21.D, Z21.D, Z22.D

0x449b04 LD1D	{Z26.D}, P2/Z, [X21, X19,LSL #3]    [1]

0x449b08 FSUB	Z17.D, Z17.D, Z18.D

0x449b0c FADD	Z18.D, Z19.D, Z16.D

0x449b10 LD1D	{Z19.D}, P2/Z, [X22, X30,LSL #3]    [2]

0x449b14 FADD	Z22.D, Z23.D, Z24.D

0x449b18 FMUL	Z21.D, Z21.D, Z7.D

0x449b1c FDIVR	Z18.D, P1/M, Z18.D, Z17.D

0x449b20 LD1D	{Z17.D}, P2/Z, [X22, X19,LSL #3]    [2]

0x449b24 FADD	Z27.D, Z19.D, Z20.D

0x449b28 FADD	Z19.D, Z17.D, Z19.D

0x449b2c FSUB	Z27.D, Z17.D, Z27.D

0x449b30 FADD	Z17.D, Z26.D, Z25.D

0x449b34 FSUB	Z17.D, Z17.D, Z22.D

0x449b38 LD1D	{Z22.D}, P2/Z, [X22, X10,LSL #3]    [2]

0x449b3c ADD	X10, X7, X0

0x449b40 FADD	Z27.D, Z27.D, Z22.D

0x449b44 FADD	Z20.D, Z20.D, Z22.D

0x449b48 FADD	Z22.D, Z25.D, Z23.D

0x449b4c MOVPRFX	Z23, Z21

0x449b50 FABS	Z23.D, P1/M, Z21.D

0x449b54 MOVPRFX	Z25, Z18

0x449b58 FABS	Z25.D, P1/M, Z18.D

0x449b5c FCMLT	P3.D, P1/Z, Z18.D, #0.0000000

0x449b60 FMUL	Z27.D, P1/M, Z27.D, #0.0000000

0x449b64 FSUB	Z22.D, Z26.D, Z22.D

0x449b68 FMAXNM	Z23.D, P1/M, Z23.D, Z3.D

0x449b6c FSUB	Z19.D, Z19.D, Z20.D

0x449b70 FMUL	Z20.D, Z21.D, Z21.D

0x449b74 FMAXNM	Z25.D, P1/M, Z25.D, Z3.D

0x449b78 FADD	Z22.D, Z22.D, Z24.D

0x449b7c FNEG	Z23.D, P3/M, Z23.D

0x449b80 MOVPRFX	Z24, Z17

0x449b84 FMUL	Z24.D, P1/M, Z24.D, #0.0000000

0x449b88 FDIV	Z27.D, P1/M, Z27.D, Z16.D

0x449b8c FNEG	Z25.D, P3/M, Z25.D

0x449b90 FMUL	Z22.D, P1/M, Z22.D, #0.0000000

0x449b94 FMUL	Z26.D, Z23.D, Z23.D

0x449b98 FMAD	Z22.D, P1/M, Z6.D, Z27.D

0x449b9c FMUL	Z27.D, Z25.D, Z25.D

0x449ba0 FADD	Z26.D, Z26.D, Z27.D

0x449ba4 FMUL	Z27.D, Z18.D, Z18.D

0x449ba8 FMUL	Z18.D, Z18.D, Z22.D

0x449bac MOVPRFX	Z22, Z19

0x449bb0 FMUL	Z22.D, P1/M, Z22.D, #0.0000000

0x449bb4 FSQRT	Z26.D, P1/M, Z26.D

0x449bb8 FMUL	Z24.D, Z24.D, Z27.D

0x449bbc FDIV	Z24.D, P1/M, Z24.D, Z16.D

0x449bc0 FMAD	Z18.D, P1/M, Z21.D, Z24.D

0x449bc4 FMUL	Z21.D, Z22.D, Z20.D

0x449bc8 FADD	Z20.D, Z20.D, Z27.D

0x449bcc FMUL	Z22.D, Z26.D, Z5.D

0x449bd0 FMAXNM	Z20.D, P1/M, Z20.D, Z3.D

0x449bd4 FMLA	Z18.D, P1/M, Z21.D, Z6.D

0x449bd8 FMUL	Z21.D, Z26.D, Z16.D

0x449bdc FDIV	Z22.D, P1/M, Z22.D, Z23.D

0x449be0 FMUL	Z16.D, Z16.D, Z17.D

0x449be4 FDIV	Z21.D, P1/M, Z21.D, Z25.D

0x449be8 FMLA	Z16.D, P1/M, Z5.D, Z19.D

0x449bec FDIV	Z18.D, P1/M, Z18.D, Z20.D

0x449bf0 FCMGE	P3.D, P1/Z, Z16.D, #0.0000000

0x449bf4 FABS	Z22.D, P1/M, Z22.D

0x449bf8 FABS	Z21.D, P1/M, Z21.D

0x449bfc FCMGT	P4.D, P1/Z, Z18.D, #0.0000000

0x449c00 FMINNM	Z21.D, P1/M, Z21.D, Z22.D

0x449c04 SEL	P3.B, P3, P3.B, P4.B

0x449c08 BIC	P4.B, P2/Z, P2.B, P3.B

0x449c0c FMUL	Z17.D, Z21.D, Z18.D

0x449c10 AND	P2.B, P2/Z, P2.B, P3.B

0x449c14 LD1D	{Z16.D}, P4/Z, [X26, X10,LSL #3]    [4]

0x449c18 FMUL	Z17.D, Z17.D, Z17.D

0x449c1c FADD	Z16.D, Z16.D, Z16.D

0x449c20 FMUL	Z16.D, Z17.D, Z16.D

0x449c24 ST1D	{Z16.D}, P4, [X27, X10,LSL #3]    [6]

0x449c28 ST1D	{Z4.D}, P2, [X4, X7,LSL #3]    [9]

0x449c2c WHILELO	P2.D, W6, W16

0x449c30 B.MI	449aa0

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 54 - 89

--------------------------------------------------------------------------------

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Coverage (%)	Name	Source Location	Module
►98.41+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.59+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	viscosity_kernel	viscosity_kernel.f90:98	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53 - 3.08
Bottlenecks	P6, P8,
Function	_QMviscosity_kernel_modulePviscosity_kernel..omp_par
Source	viscosity_kernel.f90:54-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	48.95 - 98.59
CQA cycles if no scalar integer	48.95 - 98.59
CQA cycles if FP arith vectorized	48.95 - 98.59
CQA cycles if fully vectorized	48.95 - 98.59
Front-end cycles	12.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	4.75
P6 cycles	32.00
P7 cycles	32.00
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	8.50
P11 cycles	8.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	48.95 - 98.59
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	101.00
Nb uops	101.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	4.17 - 2.07
Nb FLOP add-sub	72.00
Nb FLOP mul	72.00
Nb FLOP fma	16.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.52 - 11.11
Bytes prefetched	0.00
Bytes loaded	480.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	9.00
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.74
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	80.00
Vector-efficiency ratio all	96.91
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.39
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	91.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53 - 3.08
Bottlenecks	P6, P8,
Function	_QMviscosity_kernel_modulePviscosity_kernel..omp_par
Source	viscosity_kernel.f90:54-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	48.95 - 98.59
CQA cycles if no scalar integer	48.95 - 98.59
CQA cycles if FP arith vectorized	48.95 - 98.59
CQA cycles if fully vectorized	48.95 - 98.59
Front-end cycles	12.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	4.75
P6 cycles	32.00
P7 cycles	32.00
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	8.50
P11 cycles	8.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	48.95 - 98.59
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	101.00
Nb uops	101.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	4.17 - 2.07
Nb FLOP add-sub	72.00
Nb FLOP mul	72.00
Nb FLOP fma	16.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.52 - 11.11
Bytes prefetched	0.00
Bytes loaded	480.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	9.00
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.74
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	80.00
Vector-efficiency ratio all	96.91
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.39
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	91.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMviscosity_kernel_modulePviscosity_kernel..omp_par
Source file and lines	viscosity_kernel.f90:54-89
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:54-89.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 96% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU addition or subtraction instructions are used in vector version.
80% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 98.59 to 28.50 cycles (3.46x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 204 FP arithmetical operations:

88: addition or subtraction (16 inside FMA instructions)
88: multiply (16 inside FMA instructions)
24: divide
4: square root

The binary loop is loading 480 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	101
nb uops	101
loop length	404
used w registers	6
used x registers	19
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	17
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.75	4.75	4.75	4.75	32.00	32.00	1.00	1.00	8.50	8.50	0.00	0.00	0.00
cycles	0.50	0.50	4.75	4.75	4.75	4.75	32.00	32.00	20.00	20.00	8.50	8.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	48.95-98.59
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.63
Dispatch	32.00
DIV/SQRT	48.95-98.59
Data deps.	1.00
Overall L1	48.95-98.59

Vectorization ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	80%

Vector efficiency ratios

INT

all	89%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	75%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	91%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 98.59 cycles. At this rate:

5% of peak load performance is reached (4.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 449aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD W7, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB W30, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X10, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W6, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W5, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X14, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X30, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X10, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z16.D}, P2/Z, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUB X10, X14, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z21.D}, P2/Z, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X3, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X1, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X23, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X14, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X10, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P2/Z, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P2/Z, [X21, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z26.D}, P2/Z, [X21, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z18.D, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z18.D, P1/M, Z18.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X22, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z27.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, Z17.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z27.D, Z17.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z17.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z17.D, Z17.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X10, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z20.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z23, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z23.D, P1/M, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z25, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z25.D, P1/M, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P3.D, P1/Z, Z18.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z27.D, P1/M, Z27.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z22.D, Z26.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z23.D, P1/M, Z23.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z20.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAXNM Z25.D, P1/M, Z25.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FNEG Z23.D, P3/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z24, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z24.D, P1/M, Z24.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z27.D, P1/M, Z27.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FNEG Z25.D, P3/M, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, P1/M, Z22.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z26.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z22.D, P1/M, Z6.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z27.D, Z18.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z22, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z22.D, P1/M, Z22.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSQRT Z26.D, P1/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z24.D, Z24.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z24.D, P1/M, Z24.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAD Z18.D, P1/M, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z21.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z20.D, Z20.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, Z26.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAXNM Z20.D, P1/M, Z20.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z21.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z21.D, Z26.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z22.D, P1/M, Z22.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z21.D, P1/M, Z21.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLA Z16.D, P1/M, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z18.D, P1/M, Z18.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCMGE P3.D, P1/Z, Z16.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FABS Z22.D, P1/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FABS Z21.D, P1/M, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P4.D, P1/Z, Z18.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMINNM Z21.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL P3.B, P3, P3.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
BIC P4.B, P2/Z, P2.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMUL Z17.D, Z21.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
AND P2.B, P2/Z, P2.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z16.D}, P4/Z, [X26, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z16.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z16.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z16.D}, P4, [X27, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z4.D}, P2, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W6, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 449aa0 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMviscosity_kernel_modulePviscosity_kernel..omp_par
Source file and lines	viscosity_kernel.f90:54-89
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 96% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU addition or subtraction instructions are used in vector version.
80% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 98.59 to 28.50 cycles (3.46x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 204 FP arithmetical operations:

88: addition or subtraction (16 inside FMA instructions)
88: multiply (16 inside FMA instructions)
24: divide
4: square root

The binary loop is loading 480 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	101
nb uops	101
loop length	404
used w registers	6
used x registers	19
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	17
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.75	4.75	4.75	4.75	32.00	32.00	1.00	1.00	8.50	8.50	0.00	0.00	0.00
cycles	0.50	0.50	4.75	4.75	4.75	4.75	32.00	32.00	20.00	20.00	8.50	8.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	48.95-98.59
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.63
Dispatch	32.00
DIV/SQRT	48.95-98.59
Data deps.	1.00
Overall L1	48.95-98.59

Vectorization ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	80%

Vector efficiency ratios

INT

all	89%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	75%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	91%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 98.59 cycles. At this rate:

5% of peak load performance is reached (4.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 449aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD W7, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB W30, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X10, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W6, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W5, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X14, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X30, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X10, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z16.D}, P2/Z, [X23, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUB X10, X14, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z21.D}, P2/Z, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X3, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X1, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X23, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X14, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X10, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P2/Z, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P2/Z, [X21, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z26.D}, P2/Z, [X21, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z18.D, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z18.D, P1/M, Z18.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X22, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z27.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, Z17.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z27.D, Z17.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z17.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z17.D, Z17.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z22.D}, P2/Z, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X10, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z20.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z23, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z23.D, P1/M, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z25, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z25.D, P1/M, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P3.D, P1/Z, Z18.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z27.D, P1/M, Z27.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z22.D, Z26.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z23.D, P1/M, Z23.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z20.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAXNM Z25.D, P1/M, Z25.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FNEG Z23.D, P3/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z24, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z24.D, P1/M, Z24.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z27.D, P1/M, Z27.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FNEG Z25.D, P3/M, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, P1/M, Z22.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z26.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z22.D, P1/M, Z6.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z27.D, Z18.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z18.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z22, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z22.D, P1/M, Z22.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSQRT Z26.D, P1/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z24.D, Z24.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z24.D, P1/M, Z24.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAD Z18.D, P1/M, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z21.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z20.D, Z20.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, Z26.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAXNM Z20.D, P1/M, Z20.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z21.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z21.D, Z26.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z22.D, P1/M, Z22.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z21.D, P1/M, Z21.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLA Z16.D, P1/M, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z18.D, P1/M, Z18.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCMGE P3.D, P1/Z, Z16.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FABS Z22.D, P1/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FABS Z21.D, P1/M, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P4.D, P1/Z, Z18.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMINNM Z21.D, P1/M, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL P3.B, P3, P3.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
BIC P4.B, P2/Z, P2.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMUL Z17.D, Z21.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
AND P2.B, P2/Z, P2.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z16.D}, P4/Z, [X26, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z17.D, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z16.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z16.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z16.D}, P4, [X27, X10,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z4.D}, P2, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W6, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 449aa0 <_QMviscosity_kernel_modulePviscosity_kernel..omp_par+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code