OV - exec - Loop 119

	Loop Id: 119	Module: exec	Source: advec_mom_kernel.f90:212-240 [...]	Coverage: 3.80%

  (118) 0x41c820 CMP	W10, W9

  (118) 0x41c824 ADD	W10, W10, #1

  (118) 0x41c828 ADD	W17, W17, #1

  (118) 0x41c82c B.EQ	41c968

  (118) 0x41c830 TBNZ	X13, #63, 41c820

0x41c834 SUB	X16, XZR, X26

0x41c838 ADD	W6, W10, W8

0x41c83c ORR	X0, XZR, XZR

0x41c840 ORR	X28, XZR, X18

0x41c844 ADD	X1, X16, W17,SXTW

0x41c848 LDR	X16, [SP, #128]

0x41c84c MADD	X2, X16, X1, X12

0x41c850 LDR	X16, [SP, #120]

0x41c854 ADD	X1, X22, X2,LSL #3

0x41c858 ADD	X2, X16, X2,LSL #3

0x41c85c SUB	W16, W25, #1

0x41c860 ADD	W3, W6, W16

0x41c864 ADD	W6, W6, W25

0x41c868 SBFM	X4, X3, #0, #31

0x41c86c SUB	W5, W3, #1

0x41c870 ADD	W7, W3, #2

0x41c874 SUB	X4, X4, X26

0x41c878 B	41c8a0

0x41c880 FSUB	D4, D2, S4

0x41c884 SUB	X28, X28, #1

0x41c888 CMP	X28, #1

0x41c88c FMADD	D4, D16, D4, D5

0x41c890 FMUL	D3, D4, D3

0x41c894 STR	D3, [X1, X0]

0x41c898 ADD	X0, X0, #8

0x41c89c B.LE	41c820

0x41c8a0 LDR	D3, [X2, X0]

0x41c8a4 MOVI	D16, #0

0x41c8a8 FCMP	D3, #0

0x41c8ac FABS	D4, D3

0x41c8b0 CSEL	W19, W6, W3, #11

0x41c8b4 CSEL	W27, W7, W5, #11

0x41c8b8 CSEL	W30, W3, W6, #11

0x41c8bc SBFM	X19, X19, #0, #31

0x41c8c0 SUB	X19, X19, X26

0x41c8c4 MADD	X16, X11, X19, X15

0x41c8c8 LDR	D5, [X16, X0]

0x41c8cc MADD	X16, X11, X19, X14

0x41c8d0 FDIV	D4, D4, D5

0x41c8d4 LDR	D5, [X16, X0]

0x41c8d8 SBFM	X16, X27, #0, #31

0x41c8dc SUB	X16, X16, X26

0x41c8e0 MADD	X16, X11, X16, X14

0x41c8e4 LDR	D6, [X16, X0]

0x41c8e8 SBFM	X16, X30, #0, #31

0x41c8ec SUB	X16, X16, X26

0x41c8f0 MADD	X16, X11, X16, X14

0x41c8f4 FSUB	D7, D5, S6

0x41c8f8 LDR	D6, [X16, X0]

0x41c8fc FSUB	D6, D6, S5

0x41c900 FMUL	D17, D6, D7

0x41c904 FCMP	D17, #0

0x41c908 B.LE	41c880

0x41c90c FCMP	D3, #0

0x41c910 LDR	X19, [SP, #136]

0x41c914 FABS	D7, D7

0x41c918 FABS	D17, D6

0x41c91c FSUB	D18, D1, S4

0x41c920 CSEL	W16, W6, W5, #11

0x41c924 FMADD	D19, D4, D7, D7

0x41c928 FMUL	D18, D17, D18

0x41c92c FCMP	D6, #0

0x41c930 SBFM	X16, X16, #0, #31

0x41c934 SUB	X16, X16, X26

0x41c938 LDR	D16, [X19, X4,LSL #3]

0x41c93c LDR	D20, [X19, X16,LSL #3]

0x41c940 FDIV	D18, D18, D16

0x41c944 FMUL	D16, D16, D0

0x41c948 FDIV	D19, D19, D20

0x41c94c FADD	D18, D19, D18

0x41c950 FMUL	D16, D16, D18

0x41c954 FMINNM	D7, D16, D7

0x41c958 FMINNM	D7, D7, D17

0x41c95c FNEG	D16, D7

0x41c960 FCSEL	D16, D7, D16, #12

0x41c964 B	41c880

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 212 - 240

--------------------------------------------------------------------------------

212:       !$OMP DO PRIVATE(upwind,donor,downwind,dif,sigma,width,limiter,vdiffuw,vdiffdw,auw,adw,wind,advec_vel_s)

213:       DO k=y_min-1,y_max+1

214:         DO j=x_min,x_max+1

215:           IF(node_flux(j,k).LT.0.0)THEN

[...]

227:           sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor))

228:           width=celldy(k)

229:           vdiffuw=vel1(j,donor)-vel1(j,upwind)

230:           vdiffdw=vel1(j,downwind)-vel1(j,donor)

231:           limiter=0.0

232:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

233:             auw=ABS(vdiffuw)

234:             adw=ABS(vdiffdw)

235:             wind=1.0_8

236:             IF(vdiffdw.LE.0.0) wind=-1.0_8

237:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw)

238:           ENDIF

239:           advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter

240:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

Coverage (%)	Name	Module
►98.42+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.71 - 1.50
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	3.62 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12 - 1.10
Bottlenecks	P6, P8,
Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source	advec_mom_kernel.f90:214-215,advec_mom_kernel.f90:227-234,advec_mom_kernel.f90:237-240
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50 - 10.49
CQA cycles if no scalar integer	3.50 - 6.99
CQA cycles if FP arith vectorized	5.09 - 5.24
CQA cycles if fully vectorized	2.63 - 5.24
Front-end cycles	9.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	8.50
P3 cycles	8.50
P4 cycles	8.50
P5 cycles	8.50
P6 cycles	7.00
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	3.83
P11 cycles	3.50
P12 cycles	3.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	76.00
Nb loads	NA
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.79 - 1.62
Nb FLOP add-sub	5.00
Nb FLOP mul	5.00
Nb FLOP fma	2.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.06
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	19.32
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	23.44

Metric	Value
CQA speedup if no scalar integer	2.71 - 1.50
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	3.62 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12 - 1.10
Bottlenecks	P6, P8,
Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source	advec_mom_kernel.f90:214-215,advec_mom_kernel.f90:227-234,advec_mom_kernel.f90:237-240
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50 - 10.49
CQA cycles if no scalar integer	3.50 - 6.99
CQA cycles if FP arith vectorized	5.09 - 5.24
CQA cycles if fully vectorized	2.63 - 5.24
Front-end cycles	9.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	8.50
P3 cycles	8.50
P4 cycles	8.50
P5 cycles	8.50
P6 cycles	7.00
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	3.83
P11 cycles	3.50
P12 cycles	3.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	76.00
Nb loads	NA
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.79 - 1.62
Nb FLOP add-sub	5.00
Nb FLOP mul	5.00
Nb FLOP fma	2.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.06
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	19.32
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	23.44

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source file and lines	advec_mom_kernel.f90:212-240
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:212-215,227-240.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214-215,227-234,237-240.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.49 to 6.99 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.49 to 5.24 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.49 to 9.13 cycles (1.15x speedup).

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)
3: divide

The binary loop does not load or store any data.

General properties

nb instructions	76
nb uops	76
loop length	304
used w registers	12
used x registers	18
used b registers	0
used h registers	0
used s registers	4
used d registers	13
used q registers	0
used v registers	0
used z registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	8.50	8.50	8.50	8.50	7.00	7.00	7.00	7.00	3.83	3.50	3.67	0.00	0.00
cycles	2.00	2.00	8.50	8.50	8.50	8.50	7.00	7.00	7.00	7.00	3.83	3.50	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	9.50
Dispatch	8.50
DIV/SQRT	5.25-10.49
Overall L1	9.50-10.49

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	20%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	23%
load	25%
store	25%
mul	25%
add-sub	19%
fma	25%
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.49 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41c880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SUB X16, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X16, W17,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MADD X2, X16, X1, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X1, X22, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X16, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W16, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W6, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W6, W6, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X4, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W5, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X4, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 41c8a0 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x10b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FSUB D4, D2, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUB X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FMADD D4, D16, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D3, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X1, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.LE 41c820 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1030>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CSEL W19, W6, W3, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CSEL W27, W7, W5, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSEL W30, W3, W6, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X19, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X19, X19, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X11, X19, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D5, [X16, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MADD X16, X11, X19, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
FDIV D4, D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D5, [X16, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X16, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X16, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X11, X16, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D6, [X16, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X16, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X16, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X11, X16, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
FSUB D7, D5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D6, [X16, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D6, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D17, D6, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 41c880 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X19, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FABS D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D17, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CSEL W16, W6, W5, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMADD D19, D4, D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D18, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
SBFM X16, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X16, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D20, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D18, D18, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D16, D16, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D19, D19, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D18, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D16, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D7, D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMINNM D7, D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D16, D7, D16, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
B 41c880 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source file and lines	advec_mom_kernel.f90:212-240
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.49 to 6.99 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.49 to 9.13 cycles (1.15x speedup).

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)
3: divide

The binary loop does not load or store any data.

General properties

nb instructions	76
nb uops	76
loop length	304
used w registers	12
used x registers	18
used b registers	0
used h registers	0
used s registers	4
used d registers	13
used q registers	0
used v registers	0
used z registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	8.50	8.50	8.50	8.50	7.00	7.00	7.00	7.00	3.83	3.50	3.67	0.00	0.00
cycles	2.00	2.00	8.50	8.50	8.50	8.50	7.00	7.00	7.00	7.00	3.83	3.50	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	9.50
Dispatch	8.50
DIV/SQRT	5.25-10.49
Overall L1	9.50-10.49

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	20%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	23%
load	25%
store	25%
mul	25%
add-sub	19%
fma	25%
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.49 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41c880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SUB X16, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X16, W17,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MADD X2, X16, X1, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X1, X22, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X16, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W16, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W6, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W6, W6, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X4, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W5, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X4, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 41c8a0 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x10b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FSUB D4, D2, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUB X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FMADD D4, D16, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D3, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X1, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.LE 41c820 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1030>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CSEL W19, W6, W3, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CSEL W27, W7, W5, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CSEL W30, W3, W6, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X19, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X19, X19, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X11, X19, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D5, [X16, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MADD X16, X11, X19, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
FDIV D4, D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D5, [X16, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X16, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X16, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X11, X16, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D6, [X16, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X16, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X16, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X11, X16, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
FSUB D7, D5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR D6, [X16, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D6, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D17, D6, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 41c880 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X19, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FABS D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D17, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
CSEL W16, W6, W5, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMADD D19, D4, D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D18, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
SBFM X16, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X16, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D20, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D18, D18, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMUL D16, D16, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FDIV D19, D19, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FADD D18, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D16, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D7, D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMINNM D7, D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D16, D7, D16, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
B 41c880 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code