OV - exec - Loop 121

	Loop Id: 121	Module: exec	Source: advec_mom_kernel.f90:202-208	Coverage: 3.04%

0x41c6c4 SBFM	X7, X5, #0, #31

0x41c6c8 SUB	W27, W5, #1

0x41c6cc ADD	W6, W6, W16

0x41c6d0 ADD	W5, W5, W16

0x41c6d4 SUB	X7, X7, X24

0x41c6d8 SBFM	X27, X27, #0, #31

0x41c6dc LD1D	{Z2.D}, P2/Z, [X18, X7,LSL #3]    [6]

0x41c6e0 LD1D	{Z3.D}, P2/Z, [X0, X7,LSL #3]    [4]

0x41c6e4 ADD	X25, X7, X2

0x41c6e8 SUB	X27, X27, X24

0x41c6ec LD1D	{Z4.D}, P2/Z, [X19, X25,LSL #3]    [8]

0x41c6f0 FMUL	Z2.D, Z3.D, Z2.D

0x41c6f4 LD1D	{Z3.D}, P2/Z, [X1, X7,LSL #3]    [1]

0x41c6f8 FMLA	Z2.D, P1/M, Z4.D, Z3.D

0x41c6fc LD1D	{Z3.D}, P2/Z, [X18, X27,LSL #3]    [6]

0x41c700 LD1D	{Z4.D}, P2/Z, [X0, X27,LSL #3]    [4]

0x41c704 FMLA	Z2.D, P1/M, Z4.D, Z3.D

0x41c708 LD1D	{Z3.D}, P2/Z, [X1, X27,LSL #3]    [1]

0x41c70c LD1D	{Z4.D}, P2/Z, [X3, X27,LSL #3]    [5]

0x41c710 FMLA	Z2.D, P1/M, Z4.D, Z3.D

0x41c714 LD1D	{Z3.D}, P2/Z, [X4, X7,LSL #3]    [3]

0x41c718 FMUL	Z2.D, Z2.D, Z1.D

0x41c71c ST1D	{Z2.D}, P2, [X23, X25,LSL #3]    [9]

0x41c720 FSUB	Z2.D, Z2.D, Z3.D

0x41c724 LD1D	{Z3.D}, P2/Z, [X28, X25,LSL #3]    [2]

0x41c728 FADD	Z2.D, Z2.D, Z3.D

0x41c72c ST1D	{Z2.D}, P2, [X21, X25,LSL #3]    [7]

0x41c730 WHILELO	P2.D, W6, W17

0x41c734 B.MI	41c6c4

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 202 - 208

--------------------------------------------------------------------------------

202:         !$OMP SIMD

203:           DO j=x_min,x_max+1

204:             node_mass_post(j,k)=0.25_8*(density1(j  ,k-1)*post_vol(j  ,k-1)                     &

205:               +density1(j  ,k  )*post_vol(j  ,k  )                     &

206:               +density1(j-1,k-1)*post_vol(j-1,k-1)                     &

207:               +density1(j-1,k  )*post_vol(j-1,k  ))

208:             node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j,k-1)+node_flux(j,k)

Coverage (%)	Name	Module
►98.41+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	P10, P11,
Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source	advec_mom_kernel.f90:202-208
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	3.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.25
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	29.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.67
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	9.00
Vectorization ratio all	95.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	95.63
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	70.83
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	P10, P11,
Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source	advec_mom_kernel.f90:202-208
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	3.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.25
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	29.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.67
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	9.00
Vectorization ratio all	95.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	95.63
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	70.83
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source file and lines	advec_mom_kernel.f90:202-208
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:202-208.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU addition or subtraction instructions are used in vector version.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (12 inside FMA instructions)
20: multiply (12 inside FMA instructions)

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	29
nb uops	29
loop length	116
used w registers	5
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	4
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.63 cycles
front end	3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	3.50	3.50	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	3.50	3.50	3.50	3.50	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.63
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	92%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	66%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	70%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41c6c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X7, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB W27, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W6, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W5, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X7, X7, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X27, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z2.D}, P2/Z, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X0, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X25, X7, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X27, X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z4.D}, P2/Z, [X19, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X1, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z2.D, P1/M, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X0, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z2.D, P1/M, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X3, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z2.D, P1/M, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z2.D}, P2, [X23, X25,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FSUB Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X28, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z2.D}, P2, [X21, X25,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W6, W17	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 41c6c4 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0xed4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source file and lines	advec_mom_kernel.f90:202-208
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU addition or subtraction instructions are used in vector version.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (12 inside FMA instructions)
20: multiply (12 inside FMA instructions)

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	29
nb uops	29
loop length	116
used w registers	5
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	4
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.63 cycles
front end	3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	3.50	3.50	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	3.50	3.50	3.50	3.50	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.63
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	92%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	66%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	70%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41c6c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X7, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB W27, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W6, W6, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W5, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X7, X7, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X27, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z2.D}, P2/Z, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X0, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X25, X7, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X27, X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z4.D}, P2/Z, [X19, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X1, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z2.D, P1/M, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X0, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z2.D, P1/M, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X3, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z2.D, P1/M, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X4, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z2.D}, P2, [X23, X25,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FSUB Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X28, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z2.D}, P2, [X21, X25,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W6, W17	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 41c6c4 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0xed4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code