OV - exec - Loop 123

	Loop Id: 123	Module: exec	Source: advec_mom_kernel.f90:125-130	Coverage: 1.04%

  (124) 0x41c3e8 CMP	W9, W8

  (124) 0x41c3ec ADD	W9, W9, #1

  (124) 0x41c3f0 B.EQ	41cae8

  (124) 0x41c3f4 CBZ	W13, 41c3e8

  (124) 0x41c3f8 ADD	W18, W10, W9

  (124) 0x41c3fc LDR	X0, [SP, #128]

  (124) 0x41c400 SUB	W1, W11, #1

  (124) 0x41c404 SUB	X2, XZR, X15

  (124) 0x41c408 ORR	P1.B, P0/Z, P0.B, P0.B

  (124) 0x41c40c SUB	W17, W18, #1

  (124) 0x41c410 SBFM	X18, X18, #0, #31

  (124) 0x41c414 SBFM	X17, X17, #0, #31

  (124) 0x41c418 SUB	X18, X18, X26

  (124) 0x41c41c SUB	X17, X17, X26

  (124) 0x41c420 MUL	X17, X17, X0

  (124) 0x41c424 MUL	X18, X18, X0

  (124) 0x41c428 ADD	X17, X6, X17,LSL #3

  (124) 0x41c42c ADD	X0, X6, X18,LSL #3

  (124) 0x41c430 TBZ	W14, #0, 41c4a0

  (124) 0x41c434 ORR	W1, WZR, WZR

  (124) 0x41c438 HINT	#0

  (124) 0x41c43c HINT	#0

    (125) 0x41c440 ADD	W2, W11, W1

    (125) 0x41c444 ADD	W1, W1, #1

    (125) 0x41c448 SUB	W3, W2, #2

    (125) 0x41c44c SUB	W2, W2, #1

    (125) 0x41c450 CMP	W12, W1

    (125) 0x41c454 SBFM	X3, X3, #0, #31

    (125) 0x41c458 SBFM	X2, X2, #0, #31

    (125) 0x41c45c SUB	X3, X3, X24

    (125) 0x41c460 SUB	X2, X2, X24

    (125) 0x41c464 LDR	D2, [X17, X3,LSL #3]

    (125) 0x41c468 LDR	D4, [X17, X2,LSL #3]

    (125) 0x41c46c ADD	X3, X3, X18

    (125) 0x41c470 LDR	D3, [X6, X3,LSL #3]

    (125) 0x41c474 FADD	D2, D2, D4

    (125) 0x41c478 LDR	D4, [X0, X2,LSL #3]

    (125) 0x41c47c FADD	D3, D3, D4

    (125) 0x41c480 FADD	D2, D3, D2

    (125) 0x41c484 FMUL	D2, D2, D0

    (125) 0x41c488 STR	D2, [X5, X3,LSL #3]

    (125) 0x41c48c B.HI	41c440

  (124) 0x41c490 B	41c3e8

0x41c4a0 SUB	W3, W1, #1

0x41c4a4 SBFM	X4, X1, #0, #31

0x41c4a8 ADD	W2, W2, W15

0x41c4ac ADD	W1, W1, W15

0x41c4b0 SBFM	X3, X3, #0, #31

0x41c4b4 SUB	X4, X4, X24

0x41c4b8 SUB	X3, X3, X24

0x41c4bc LD1D	{Z4.D}, P1/Z, [X17, X4,LSL #3]

0x41c4c0 LD1D	{Z2.D}, P1/Z, [X17, X3,LSL #3]

0x41c4c4 ADD	X3, X3, X18

0x41c4c8 LD1D	{Z3.D}, P1/Z, [X6, X3,LSL #3]

0x41c4cc FADD	Z2.D, Z2.D, Z4.D

0x41c4d0 LD1D	{Z4.D}, P1/Z, [X0, X4,LSL #3]

0x41c4d4 FADD	Z3.D, Z3.D, Z4.D

0x41c4d8 FADD	Z2.D, Z3.D, Z2.D

0x41c4dc FMUL	Z2.D, Z2.D, Z1.D

0x41c4e0 ST1D	{Z2.D}, P1, [X5, X3,LSL #3]

0x41c4e4 WHILELO	P1.D, W2, W16

0x41c4e8 B.MI	41c4a0

0x41c4ec B	41c3e8

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 125 - 130

--------------------------------------------------------------------------------

125:         !$OMP DO

126:         DO k=y_min,y_max+1

127:         !$OMP SIMD

128:           DO j=x_min-2,x_max+2

129:             ! Find staggered mesh mass fluxes, nodal masses and volumes.

130:             node_flux(j,k)=0.25_8*(mass_flux_x(j,k-1  )+mass_flux_x(j  ,k)  &

Coverage (%)	Name	Module
►98.42+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue, P10, P11,
Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source	advec_mom_kernel.f90:127-127,advec_mom_kernel.f90:130-130
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	2.50
Front-end cycles	2.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.25
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	6.40
Nb FLOP add-sub	12.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	90.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	91.25
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	78.13
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue, P10, P11,
Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source	advec_mom_kernel.f90:127-127,advec_mom_kernel.f90:130-130
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	2.50
Front-end cycles	2.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.25
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	6.40
Nb FLOP add-sub	12.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	90.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	91.25
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	78.13
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source file and lines	advec_mom_kernel.f90:125-130
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:125-130.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:127,130.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 91% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU addition or subtraction instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

12: addition or subtraction
4: multiply

The binary loop is loading 128 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	20
nb uops	20
loop length	80
used w registers	5
used x registers	9
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	4
nb stack references	0
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.25	2.25	2.25	2.25	2.00	2.00	0.50	0.50	2.50	2.50	0.00	0.00	0.00
cycles	1.00	1.00	2.25	2.25	2.25	2.25	2.00	2.00	2.00	2.00	2.50	2.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Dispatch	2.50
Overall L1	2.50

Vectorization ratios

INT

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	100%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	91%
load	100%
store	100%
mul	100%
add-sub	78%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

53% of peak load performance is reached (51.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.25 cycles (1.11x speedup).

ASM code

In the binary file, the address of the loop is: 41c4a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SUB W3, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W1, W1, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X3, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X4, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X3, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z4.D}, P1/Z, [X17, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X3, X3, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z3.D}, P1/Z, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z2.D}, P1, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P1.D, W2, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 41c4a0 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0xcb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41c3e8 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par
Source file and lines	advec_mom_kernel.f90:125-130
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 91% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU addition or subtraction instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

12: addition or subtraction
4: multiply

The binary loop is loading 128 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	20
nb uops	20
loop length	80
used w registers	5
used x registers	9
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	4
nb stack references	0
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.25	2.25	2.25	2.25	2.00	2.00	0.50	0.50	2.50	2.50	0.00	0.00	0.00
cycles	1.00	1.00	2.25	2.25	2.25	2.25	2.00	2.00	2.00	2.00	2.50	2.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Dispatch	2.50
Overall L1	2.50

Vectorization ratios

INT

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	100%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	91%
load	100%
store	100%
mul	100%
add-sub	78%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

53% of peak load performance is reached (51.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 41c4a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SUB W3, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W1, W1, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X3, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X4, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X3, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z4.D}, P1/Z, [X17, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X3, X3, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z3.D}, P1/Z, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z2.D}, P1, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P1.D, W2, W16	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 41c4a0 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0xcb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41c3e8 <_QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code