OV - exec - Loop 19

	Loop Id: 19	Module: exec	Source: build_field.f90:122-130	Coverage: 0.03%

0x412cc0 LDRSW	X16, [X20]    [7]

0x412cc4 SUB	X15, X15, #1

0x412cc8 CMP	X15, #1

0x412ccc SUB	X16, X16, X10

0x412cd0 MADD	X16, X16, X12, X9

0x412cd4 LDR	X17, [X16]    [12]

0x412cd8 LDP	X18, X0, [X16, #24]    [12]

0x412cdc LDR	X16, [X16, #48]    [12]

0x412ce0 SUB	X16, X13, X16

0x412ce4 SUB	X17, X17, X18,LSL #3

0x412ce8 MUL	X16, X0, X16

0x412cec ADD	X16, X17, X16,LSL #3

0x412cf0 STR	XZR, [X16, X14]    [11]

0x412cf4 LDRSW	X16, [X20]    [7]

0x412cf8 SUB	X16, X16, X10

0x412cfc MADD	X16, X16, X12, X9

0x412d00 LDR	X17, [X16, #72]    [6]

0x412d04 LDP	X18, X0, [X16, #96]    [6]

0x412d08 LDR	X16, [X16, #120]    [6]

0x412d0c SUB	X16, X13, X16

0x412d10 SUB	X17, X17, X18,LSL #3

0x412d14 MUL	X16, X0, X16

0x412d18 ADD	X16, X17, X16,LSL #3

0x412d1c STR	XZR, [X16, X14]    [5]

0x412d20 LDRSW	X16, [X20]    [7]

0x412d24 SUB	X16, X16, X10

0x412d28 MADD	X16, X16, X12, X9

0x412d2c LDR	X17, [X16, #144]    [4]

0x412d30 LDP	X18, X0, [X16, #168]    [4]

0x412d34 LDR	X16, [X16, #192]    [4]

0x412d38 SUB	X16, X13, X16

0x412d3c SUB	X17, X17, X18,LSL #3

0x412d40 MUL	X16, X0, X16

0x412d44 ADD	X16, X17, X16,LSL #3

0x412d48 STR	XZR, [X16, X14]    [17]

0x412d4c LDRSW	X16, [X20]    [7]

0x412d50 SUB	X16, X16, X10

0x412d54 MADD	X16, X16, X12, X9

0x412d58 LDR	X17, [X16, #216]    [16]

0x412d5c LDP	X18, X0, [X16, #240]    [16]

0x412d60 LDR	X16, [X16, #264]    [16]

0x412d64 SUB	X16, X13, X16

0x412d68 SUB	X17, X17, X18,LSL #3

0x412d6c MUL	X16, X0, X16

0x412d70 ADD	X16, X17, X16,LSL #3

0x412d74 STR	XZR, [X16, X14]    [15]

0x412d78 LDRSW	X16, [X20]    [7]

0x412d7c SUB	X16, X16, X10

0x412d80 MADD	X16, X16, X12, X9

0x412d84 LDR	X17, [X16, #288]    [10]

0x412d88 LDP	X18, X0, [X16, #312]    [10]

0x412d8c LDR	X16, [X16, #336]    [10]

0x412d90 SUB	X16, X13, X16

0x412d94 SUB	X17, X17, X18,LSL #3

0x412d98 MUL	X16, X0, X16

0x412d9c ADD	X16, X17, X16,LSL #3

0x412da0 STR	XZR, [X16, X14]    [9]

0x412da4 LDRSW	X16, [X20]    [7]

0x412da8 SUB	X16, X16, X10

0x412dac MADD	X16, X16, X12, X9

0x412db0 LDR	X17, [X16, #360]    [8]

0x412db4 LDP	X18, X0, [X16, #384]    [8]

0x412db8 LDR	X16, [X16, #408]    [8]

0x412dbc SUB	X16, X13, X16

0x412dc0 SUB	X17, X17, X18,LSL #3

0x412dc4 MUL	X16, X0, X16

0x412dc8 ADD	X16, X17, X16,LSL #3

0x412dcc STR	XZR, [X16, X14]    [3]

0x412dd0 LDRSW	X16, [X20]    [7]

0x412dd4 SUB	X16, X16, X10

0x412dd8 MADD	X16, X16, X12, X9

0x412ddc LDR	X17, [X16, #432]    [2]

0x412de0 LDP	X18, X0, [X16, #456]    [2]

0x412de4 LDR	X16, [X16, #480]    [2]

0x412de8 SUB	X16, X13, X16

0x412dec SUB	X17, X17, X18,LSL #3

0x412df0 MUL	X16, X0, X16

0x412df4 ADD	X16, X17, X16,LSL #3

0x412df8 STR	XZR, [X16, X14]    [1]

0x412dfc LDRSW	X16, [X20]    [7]

0x412e00 SUB	X16, X16, X10

0x412e04 MADD	X16, X16, X12, X9

0x412e08 LDR	X17, [X16, #1968]    [14]

0x412e0c LDR	X18, [X16, #1992]    [14]

0x412e10 LDR	X0, [X16, #2000]    [14]

0x412e14 LDR	X16, [X16, #2016]    [14]

0x412e18 SUB	X16, X13, X16

0x412e1c SUB	X17, X17, X18,LSL #3

0x412e20 MUL	X16, X0, X16

0x412e24 ADD	X16, X17, X16,LSL #3

0x412e28 STR	XZR, [X16, X14]    [13]

0x412e2c ADD	X14, X14, #8

0x412e30 B.HI	412cc0

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90: 122 - 130

--------------------------------------------------------------------------------

122:       DO j=chunk%tiles(tile)%t_xmin-2,chunk%tiles(tile)%t_xmax+2

123:         chunk%tiles(tile)%field%density0(j,k)=0.0

124:         chunk%tiles(tile)%field%density1(j,k)=0.0

125:         chunk%tiles(tile)%field%energy0(j,k)=0.0

126:         chunk%tiles(tile)%field%energy1(j,k)=0.0

127:         chunk%tiles(tile)%field%pressure(j,k)=0.0

128:         chunk%tiles(tile)%field%viscosity(j,k)=0.0

129:         chunk%tiles(tile)%field%soundspeed(j,k)=0.0

130:         chunk%tiles(tile)%field%volume(j,k)=0.0

Coverage (%)	Name	Module
►99.34+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.42
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P10, P11, P12,
Function	build_field_..omp_par
Source	build_field.f90:122-130
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.67
CQA cycles if no scalar integer	13.67
CQA cycles if FP arith vectorized	13.67
CQA cycles if fully vectorized	4.00
Front-end cycles	11.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	12.75
P3 cycles	12.75
P4 cycles	12.75
P5 cycles	12.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	13.67
P11 cycles	13.67
P12 cycles	13.67
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	93.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.76
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	8.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	30.00
Vector-efficiency ratio load	35.29
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.42
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P10, P11, P12,
Function	build_field_..omp_par
Source	build_field.f90:122-130
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.67
CQA cycles if no scalar integer	13.67
CQA cycles if FP arith vectorized	13.67
CQA cycles if fully vectorized	4.00
Front-end cycles	11.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	12.75
P3 cycles	12.75
P4 cycles	12.75
P5 cycles	12.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	13.67
P11 cycles	13.67
P12 cycles	13.67
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	93.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.76
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	8.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	30.00
Vector-efficiency ratio load	35.29
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	build_field_..omp_par
Source file and lines	build_field.f90:122-130
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90:122-130.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.67 to 4.00 cycles (3.42x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)
Constant non-unit stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes.

General properties

nb instructions	93
nb uops	93
loop length	372
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.63 cycles
front end	11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	12.75	12.75	12.75	12.75	0.00	0.00	0.00	0.00	13.67	13.67	13.67	4.00	4.00
cycles	0.50	0.50	12.75	12.75	12.75	12.75	0.00	0.00	0.00	0.00	13.67	13.67	13.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.63
Dispatch	13.67
Data deps.	1.00
Overall L1	13.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	35%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.67 cycles. At this rate:

1% of peak load performance is reached (1.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 412cc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #360]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #384]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #408]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1968]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1992]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #2000]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #2016]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.HI 412cc0 <build_field_..omp_par+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	build_field_..omp_par
Source file and lines	build_field.f90:122-130
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)
Constant non-unit stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes.

General properties

nb instructions	93
nb uops	93
loop length	372
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.63 cycles
front end	11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	12.75	12.75	12.75	12.75	0.00	0.00	0.00	0.00	13.67	13.67	13.67	4.00	4.00
cycles	0.50	0.50	12.75	12.75	12.75	12.75	0.00	0.00	0.00	0.00	13.67	13.67	13.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.63
Dispatch	13.67
Data deps.	1.00
Overall L1	13.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	35%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.67 cycles. At this rate:

1% of peak load performance is reached (1.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 412cc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #360]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #384]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #408]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X18, X0, [X16, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X16, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1968]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1992]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #2000]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #2016]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.HI 412cc0 <build_field_..omp_par+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code